1 /* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License as 4 * published by the Free Software Foundation; either version 2 of 5 * the License, or (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 15 * MA 02111-1307 USA 16 */ 17 18 #include <config.h> 19 #include <common.h> 20 #include <net.h> 21 #include <asm/arch/hardware.h> 22 #include <asm/arch/spi.h> 23 24 /* 25 * Control Registers in Bank 0 26 */ 27 28 #define CTL_REG_ERDPTL 0x00 29 #define CTL_REG_ERDPTH 0x01 30 #define CTL_REG_EWRPTL 0x02 31 #define CTL_REG_EWRPTH 0x03 32 #define CTL_REG_ETXSTL 0x04 33 #define CTL_REG_ETXSTH 0x05 34 #define CTL_REG_ETXNDL 0x06 35 #define CTL_REG_ETXNDH 0x07 36 #define CTL_REG_ERXSTL 0x08 37 #define CTL_REG_ERXSTH 0x09 38 #define CTL_REG_ERXNDL 0x0A 39 #define CTL_REG_ERXNDH 0x0B 40 #define CTL_REG_ERXRDPTL 0x0C 41 #define CTL_REG_ERXRDPTH 0x0D 42 #define CTL_REG_ERXWRPTL 0x0E 43 #define CTL_REG_ERXWRPTH 0x0F 44 #define CTL_REG_EDMASTL 0x10 45 #define CTL_REG_EDMASTH 0x11 46 #define CTL_REG_EDMANDL 0x12 47 #define CTL_REG_EDMANDH 0x13 48 #define CTL_REG_EDMADSTL 0x14 49 #define CTL_REG_EDMADSTH 0x15 50 #define CTL_REG_EDMACSL 0x16 51 #define CTL_REG_EDMACSH 0x17 52 /* these are common in all banks */ 53 #define CTL_REG_EIE 0x1B 54 #define CTL_REG_EIR 0x1C 55 #define CTL_REG_ESTAT 0x1D 56 #define CTL_REG_ECON2 0x1E 57 #define CTL_REG_ECON1 0x1F 58 59 /* 60 * Control Registers in Bank 1 61 */ 62 63 #define CTL_REG_EHT0 0x00 64 #define CTL_REG_EHT1 0x01 65 #define CTL_REG_EHT2 0x02 66 #define CTL_REG_EHT3 0x03 67 #define CTL_REG_EHT4 0x04 68 #define CTL_REG_EHT5 0x05 69 #define CTL_REG_EHT6 0x06 70 #define CTL_REG_EHT7 0x07 71 #define CTL_REG_EPMM0 0x08 72 #define CTL_REG_EPMM1 0x09 73 #define CTL_REG_EPMM2 0x0A 74 #define CTL_REG_EPMM3 0x0B 75 #define CTL_REG_EPMM4 0x0C 76 #define CTL_REG_EPMM5 0x0D 77 #define CTL_REG_EPMM6 0x0E 78 #define CTL_REG_EPMM7 0x0F 79 #define CTL_REG_EPMCSL 0x10 80 #define CTL_REG_EPMCSH 0x11 81 #define CTL_REG_EPMOL 0x14 82 #define CTL_REG_EPMOH 0x15 83 #define CTL_REG_EWOLIE 0x16 84 #define CTL_REG_EWOLIR 0x17 85 #define CTL_REG_ERXFCON 0x18 86 #define CTL_REG_EPKTCNT 0x19 87 88 /* 89 * Control Registers in Bank 2 90 */ 91 92 #define CTL_REG_MACON1 0x00 93 #define CTL_REG_MACON2 0x01 94 #define CTL_REG_MACON3 0x02 95 #define CTL_REG_MACON4 0x03 96 #define CTL_REG_MABBIPG 0x04 97 #define CTL_REG_MAIPGL 0x06 98 #define CTL_REG_MAIPGH 0x07 99 #define CTL_REG_MACLCON1 0x08 100 #define CTL_REG_MACLCON2 0x09 101 #define CTL_REG_MAMXFLL 0x0A 102 #define CTL_REG_MAMXFLH 0x0B 103 #define CTL_REG_MAPHSUP 0x0D 104 #define CTL_REG_MICON 0x11 105 #define CTL_REG_MICMD 0x12 106 #define CTL_REG_MIREGADR 0x14 107 #define CTL_REG_MIWRL 0x16 108 #define CTL_REG_MIWRH 0x17 109 #define CTL_REG_MIRDL 0x18 110 #define CTL_REG_MIRDH 0x19 111 112 /* 113 * Control Registers in Bank 3 114 */ 115 116 #define CTL_REG_MAADR1 0x00 117 #define CTL_REG_MAADR0 0x01 118 #define CTL_REG_MAADR3 0x02 119 #define CTL_REG_MAADR2 0x03 120 #define CTL_REG_MAADR5 0x04 121 #define CTL_REG_MAADR4 0x05 122 #define CTL_REG_EBSTSD 0x06 123 #define CTL_REG_EBSTCON 0x07 124 #define CTL_REG_EBSTCSL 0x08 125 #define CTL_REG_EBSTCSH 0x09 126 #define CTL_REG_MISTAT 0x0A 127 #define CTL_REG_EREVID 0x12 128 #define CTL_REG_ECOCON 0x15 129 #define CTL_REG_EFLOCON 0x17 130 #define CTL_REG_EPAUSL 0x18 131 #define CTL_REG_EPAUSH 0x19 132 133 134 /* 135 * PHY Register 136 */ 137 138 #define PHY_REG_PHID1 0x02 139 #define PHY_REG_PHID2 0x03 140 /* taken from the Linux driver */ 141 #define PHY_REG_PHCON1 0x00 142 #define PHY_REG_PHCON2 0x10 143 #define PHY_REG_PHLCON 0x14 144 145 /* 146 * Receive Filter Register (ERXFCON) bits 147 */ 148 149 #define ENC_RFR_UCEN 0x80 150 #define ENC_RFR_ANDOR 0x40 151 #define ENC_RFR_CRCEN 0x20 152 #define ENC_RFR_PMEN 0x10 153 #define ENC_RFR_MPEN 0x08 154 #define ENC_RFR_HTEN 0x04 155 #define ENC_RFR_MCEN 0x02 156 #define ENC_RFR_BCEN 0x01 157 158 /* 159 * ECON1 Register Bits 160 */ 161 162 #define ENC_ECON1_TXRST 0x80 163 #define ENC_ECON1_RXRST 0x40 164 #define ENC_ECON1_DMAST 0x20 165 #define ENC_ECON1_CSUMEN 0x10 166 #define ENC_ECON1_TXRTS 0x08 167 #define ENC_ECON1_RXEN 0x04 168 #define ENC_ECON1_BSEL1 0x02 169 #define ENC_ECON1_BSEL0 0x01 170 171 /* 172 * ECON2 Register Bits 173 */ 174 #define ENC_ECON2_AUTOINC 0x80 175 #define ENC_ECON2_PKTDEC 0x40 176 #define ENC_ECON2_PWRSV 0x20 177 #define ENC_ECON2_VRPS 0x08 178 179 /* 180 * EIR Register Bits 181 */ 182 #define ENC_EIR_PKTIF 0x40 183 #define ENC_EIR_DMAIF 0x20 184 #define ENC_EIR_LINKIF 0x10 185 #define ENC_EIR_TXIF 0x08 186 #define ENC_EIR_WOLIF 0x04 187 #define ENC_EIR_TXERIF 0x02 188 #define ENC_EIR_RXERIF 0x01 189 190 /* 191 * ESTAT Register Bits 192 */ 193 194 #define ENC_ESTAT_INT 0x80 195 #define ENC_ESTAT_LATECOL 0x10 196 #define ENC_ESTAT_RXBUSY 0x04 197 #define ENC_ESTAT_TXABRT 0x02 198 #define ENC_ESTAT_CLKRDY 0x01 199 200 /* 201 * EIE Register Bits 202 */ 203 204 #define ENC_EIE_INTIE 0x80 205 #define ENC_EIE_PKTIE 0x40 206 #define ENC_EIE_DMAIE 0x20 207 #define ENC_EIE_LINKIE 0x10 208 #define ENC_EIE_TXIE 0x08 209 #define ENC_EIE_WOLIE 0x04 210 #define ENC_EIE_TXERIE 0x02 211 #define ENC_EIE_RXERIE 0x01 212 213 /* 214 * MACON1 Register Bits 215 */ 216 #define ENC_MACON1_LOOPBK 0x10 217 #define ENC_MACON1_TXPAUS 0x08 218 #define ENC_MACON1_RXPAUS 0x04 219 #define ENC_MACON1_PASSALL 0x02 220 #define ENC_MACON1_MARXEN 0x01 221 222 223 /* 224 * MACON2 Register Bits 225 */ 226 #define ENC_MACON2_MARST 0x80 227 #define ENC_MACON2_RNDRST 0x40 228 #define ENC_MACON2_MARXRST 0x08 229 #define ENC_MACON2_RFUNRST 0x04 230 #define ENC_MACON2_MATXRST 0x02 231 #define ENC_MACON2_TFUNRST 0x01 232 233 /* 234 * MACON3 Register Bits 235 */ 236 #define ENC_MACON3_PADCFG2 0x80 237 #define ENC_MACON3_PADCFG1 0x40 238 #define ENC_MACON3_PADCFG0 0x20 239 #define ENC_MACON3_TXCRCEN 0x10 240 #define ENC_MACON3_PHDRLEN 0x08 241 #define ENC_MACON3_HFRMEN 0x04 242 #define ENC_MACON3_FRMLNEN 0x02 243 #define ENC_MACON3_FULDPX 0x01 244 245 /* 246 * MICMD Register Bits 247 */ 248 #define ENC_MICMD_MIISCAN 0x02 249 #define ENC_MICMD_MIIRD 0x01 250 251 /* 252 * MISTAT Register Bits 253 */ 254 #define ENC_MISTAT_NVALID 0x04 255 #define ENC_MISTAT_SCAN 0x02 256 #define ENC_MISTAT_BUSY 0x01 257 258 /* 259 * PHID1 and PHID2 values 260 */ 261 #define ENC_PHID1_VALUE 0x0083 262 #define ENC_PHID2_VALUE 0x1400 263 #define ENC_PHID2_MASK 0xFC00 264 265 266 #define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */ 267 #define ENC_RESET 0x00020000 /* pin P1.17 */ 268 269 #define FAILSAFE_VALUE 5000 270 271 /* 272 * Controller memory layout: 273 * 274 * 0x0000 - 0x17ff 6k bytes receive buffer 275 * 0x1800 - 0x1fff 2k bytes transmit buffer 276 */ 277 /* Use the lower memory for receiver buffer. See errata pt. 5 */ 278 #define ENC_RX_BUF_START 0x0000 279 #define ENC_TX_BUF_START 0x1800 280 /* taken from the Linux driver */ 281 #define ENC_RX_BUF_END 0x17ff 282 #define ENC_TX_BUF_END 0x1fff 283 284 /* maximum frame length */ 285 #define ENC_MAX_FRM_LEN 1518 286 287 #define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS) 288 #define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS) 289 #define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8); 290 291 292 static unsigned char encReadReg (unsigned char regNo); 293 static void encWriteReg (unsigned char regNo, unsigned char data); 294 static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c); 295 static void encReadBuff (unsigned short length, unsigned char *pBuff); 296 static void encWriteBuff (unsigned short length, unsigned char *pBuff); 297 static void encBitSet (unsigned char regNo, unsigned char data); 298 static void encBitClr (unsigned char regNo, unsigned char data); 299 static void encReset (void); 300 static void encInit (unsigned char *pEthAddr); 301 static unsigned short phyRead (unsigned char addr); 302 static void phyWrite(unsigned char, unsigned short); 303 static void encPoll (void); 304 static void encRx (void); 305 306 #define m_nic_read(reg) encReadReg(reg) 307 #define m_nic_write(reg, data) encWriteReg(reg, data) 308 #define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count) 309 #define m_nic_read_data(len, buf) encReadBuff((len), (buf)) 310 #define m_nic_write_data(len, buf) encWriteBuff((len), (buf)) 311 312 /* bit field set */ 313 #define m_nic_bfs(reg, data) encBitSet(reg, data) 314 315 /* bit field clear */ 316 #define m_nic_bfc(reg, data) encBitClr(reg, data) 317 318 static unsigned char bank = 0; /* current bank in enc28j60 */ 319 static unsigned char next_pointer_lsb; 320 static unsigned char next_pointer_msb; 321 322 static unsigned char buffer[ENC_MAX_FRM_LEN]; 323 static int rxResetCounter = 0; 324 325 #define RX_RESET_COUNTER 1000; 326 327 /*----------------------------------------------------------------------------- 328 * Always returns 0 329 */ 330 int eth_init (bd_t * bis) 331 { 332 unsigned char estatVal; 333 334 /* configure GPIO */ 335 (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS; 336 (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET; 337 338 /* CS and RESET active low */ 339 PUT32 (IO1SET, ENC_SPI_SLAVE_CS); 340 PUT32 (IO1SET, ENC_RESET); 341 342 spi_init (); 343 344 /* taken from the Linux driver - dangerous stuff here! */ 345 /* Wait for CLKRDY to become set (i.e., check that we can communicate with 346 the ENC) */ 347 do 348 { 349 estatVal = m_nic_read(CTL_REG_ESTAT); 350 } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY)); 351 352 /* initialize controller */ 353 encReset (); 354 encInit (bis->bi_enetaddr); 355 356 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ 357 358 return 0; 359 } 360 361 int eth_send (volatile void *packet, int length) 362 { 363 /* check frame length, etc. */ 364 /* TODO: */ 365 366 /* switch to bank 0 */ 367 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 368 369 /* set EWRPT */ 370 m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff)); 371 m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8)); 372 373 /* set ETXND */ 374 m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF); 375 m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8); 376 377 /* set ETXST */ 378 m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF); 379 m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8); 380 381 /* write packet */ 382 m_nic_write_data (length, (unsigned char *) packet); 383 384 /* taken from the Linux driver */ 385 /* Verify that the internal transmit logic has not been altered by excessive 386 collisions. See Errata B4 12 and 14. 387 */ 388 if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) { 389 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST); 390 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST); 391 } 392 m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); 393 394 /* set ECON1.TXRTS */ 395 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS); 396 397 return 0; 398 } 399 400 401 /***************************************************************************** 402 * This function resets the receiver only. This function may be called from 403 * interrupt-context. 404 */ 405 static void encReceiverReset (void) 406 { 407 unsigned char econ1; 408 409 econ1 = m_nic_read (CTL_REG_ECON1); 410 if ((econ1 & ENC_ECON1_RXRST) == 0) { 411 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST); 412 rxResetCounter = RX_RESET_COUNTER; 413 } 414 } 415 416 /***************************************************************************** 417 * receiver reset timer 418 */ 419 static void encReceiverResetCallback (void) 420 { 421 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST); 422 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ 423 } 424 425 /*----------------------------------------------------------------------------- 426 * Check for received packets. Call NetReceive for each packet. The return 427 * value is ignored by the caller. 428 */ 429 int eth_rx (void) 430 { 431 if (rxResetCounter > 0 && --rxResetCounter == 0) { 432 encReceiverResetCallback (); 433 } 434 435 encPoll (); 436 437 return 0; 438 } 439 440 void eth_halt (void) 441 { 442 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */ 443 } 444 445 /*****************************************************************************/ 446 447 static void encPoll (void) 448 { 449 unsigned char eir_reg; 450 volatile unsigned char estat_reg; 451 unsigned char pkt_cnt; 452 453 #ifdef CONFIG_USE_IRQ 454 /* clear global interrupt enable bit in enc28j60 */ 455 m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE); 456 #endif 457 estat_reg = m_nic_read (CTL_REG_ESTAT); 458 459 eir_reg = m_nic_read (CTL_REG_EIR); 460 461 if (eir_reg & ENC_EIR_TXIF) { 462 /* clear TXIF bit in EIR */ 463 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF); 464 } 465 466 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ 467 468 /* move to bank 1 */ 469 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); 470 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); 471 472 /* read pktcnt */ 473 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); 474 475 if (pkt_cnt > 0) { 476 if ((eir_reg & ENC_EIR_PKTIF) == 0) { 477 /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */ 478 } 479 encRx (); 480 /* clear PKTIF bit in EIR, this should not need to be done but it 481 seems like we get problems if we do not */ 482 m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF); 483 } 484 485 if (eir_reg & ENC_EIR_RXERIF) { 486 printf ("encPoll: rx error\n"); 487 m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF); 488 } 489 if (eir_reg & ENC_EIR_TXERIF) { 490 printf ("encPoll: tx error\n"); 491 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF); 492 } 493 494 #ifdef CONFIG_USE_IRQ 495 /* set global interrupt enable bit in enc28j60 */ 496 m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); 497 #endif 498 } 499 500 static void encRx (void) 501 { 502 unsigned short pkt_len; 503 unsigned short copy_len; 504 unsigned short status; 505 unsigned char eir_reg; 506 unsigned char pkt_cnt = 0; 507 unsigned short rxbuf_rdpt; 508 509 /* switch to bank 0 */ 510 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 511 512 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); 513 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); 514 515 do { 516 m_nic_read_data (6, buffer); 517 next_pointer_lsb = buffer[0]; 518 next_pointer_msb = buffer[1]; 519 pkt_len = buffer[2]; 520 pkt_len |= (unsigned short) buffer[3] << 8; 521 status = buffer[4]; 522 status |= (unsigned short) buffer[5] << 8; 523 524 if (pkt_len <= ENC_MAX_FRM_LEN) 525 copy_len = pkt_len; 526 else 527 copy_len = 0; 528 529 if ((status & (1L << 7)) == 0) /* check Received Ok bit */ 530 copy_len = 0; 531 532 /* taken from the Linux driver */ 533 /* check if next pointer is resonable */ 534 if ((((unsigned int)next_pointer_msb << 8) | 535 (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START) 536 copy_len = 0; 537 538 if (copy_len > 0) { 539 m_nic_read_data (copy_len, buffer); 540 } 541 542 /* advance read pointer to next pointer */ 543 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); 544 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); 545 546 /* decrease packet counter */ 547 m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); 548 549 /* taken from the Linux driver */ 550 /* Only odd values should be written to ERXRDPTL, 551 * see errata B4 pt.13 552 */ 553 rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; 554 if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | 555 m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt > 556 (m_nic_read(CTL_REG_ERXNDH) << 8 | 557 m_nic_read(CTL_REG_ERXNDL)))) { 558 m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL)); 559 m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH)); 560 } else { 561 m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF); 562 m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8); 563 } 564 565 /* move to bank 1 */ 566 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); 567 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); 568 569 /* read pktcnt */ 570 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); 571 572 /* switch to bank 0 */ 573 m_nic_bfc (CTL_REG_ECON1, 574 (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 575 576 if (copy_len == 0) { 577 eir_reg = m_nic_read (CTL_REG_EIR); 578 encReceiverReset (); 579 printf ("eth_rx: copy_len=0\n"); 580 continue; 581 } 582 583 NetReceive ((unsigned char *) buffer, pkt_len); 584 585 eir_reg = m_nic_read (CTL_REG_EIR); 586 } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ 587 } 588 589 static void encWriteReg (unsigned char regNo, unsigned char data) 590 { 591 spi_lock (); 592 enc_cfg_spi (); 593 enc_enable (); 594 595 spi_write (0x40 | regNo); /* write in regNo */ 596 spi_write (data); 597 598 enc_disable (); 599 enc_enable (); 600 601 spi_write (0x1f); /* write reg 0x1f */ 602 603 enc_disable (); 604 spi_unlock (); 605 } 606 607 static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c) 608 { 609 unsigned char readback; 610 int i; 611 612 spi_lock (); 613 614 for (i = 0; i < c; i++) { 615 enc_cfg_spi (); 616 enc_enable (); 617 618 spi_write (0x40 | regNo); /* write in regNo */ 619 spi_write (data); 620 621 enc_disable (); 622 enc_enable (); 623 624 spi_write (0x1f); /* write reg 0x1f */ 625 626 enc_disable (); 627 628 spi_unlock (); /* we must unlock spi first */ 629 630 readback = encReadReg (regNo); 631 632 spi_lock (); 633 634 if (readback == data) 635 break; 636 } 637 spi_unlock (); 638 639 if (i == c) { 640 printf ("enc28j60: write reg %d failed\n", regNo); 641 } 642 } 643 644 static unsigned char encReadReg (unsigned char regNo) 645 { 646 unsigned char rxByte; 647 648 spi_lock (); 649 enc_cfg_spi (); 650 enc_enable (); 651 652 spi_write (0x1f); /* read reg 0x1f */ 653 654 bank = spi_read () & 0x3; 655 656 enc_disable (); 657 enc_enable (); 658 659 spi_write (regNo); 660 rxByte = spi_read (); 661 662 /* check if MAC or MII register */ 663 if (((bank == 2) && (regNo <= 0x1a)) || 664 ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) { 665 /* ignore first byte and read another byte */ 666 rxByte = spi_read (); 667 } 668 669 enc_disable (); 670 spi_unlock (); 671 672 return rxByte; 673 } 674 675 static void encReadBuff (unsigned short length, unsigned char *pBuff) 676 { 677 spi_lock (); 678 enc_cfg_spi (); 679 enc_enable (); 680 681 spi_write (0x20 | 0x1a); /* read buffer memory */ 682 683 while (length--) { 684 if (pBuff != NULL) 685 *pBuff++ = spi_read (); 686 else 687 spi_write (0); 688 } 689 690 enc_disable (); 691 spi_unlock (); 692 } 693 694 static void encWriteBuff (unsigned short length, unsigned char *pBuff) 695 { 696 spi_lock (); 697 enc_cfg_spi (); 698 enc_enable (); 699 700 spi_write (0x60 | 0x1a); /* write buffer memory */ 701 702 spi_write (0x00); /* control byte */ 703 704 while (length--) 705 spi_write (*pBuff++); 706 707 enc_disable (); 708 spi_unlock (); 709 } 710 711 static void encBitSet (unsigned char regNo, unsigned char data) 712 { 713 spi_lock (); 714 enc_cfg_spi (); 715 enc_enable (); 716 717 spi_write (0x80 | regNo); /* bit field set */ 718 spi_write (data); 719 720 enc_disable (); 721 spi_unlock (); 722 } 723 724 static void encBitClr (unsigned char regNo, unsigned char data) 725 { 726 spi_lock (); 727 enc_cfg_spi (); 728 enc_enable (); 729 730 spi_write (0xA0 | regNo); /* bit field clear */ 731 spi_write (data); 732 733 enc_disable (); 734 spi_unlock (); 735 } 736 737 static void encReset (void) 738 { 739 spi_lock (); 740 enc_cfg_spi (); 741 enc_enable (); 742 743 spi_write (0xff); /* soft reset */ 744 745 enc_disable (); 746 spi_unlock (); 747 748 /* sleep 1 ms. See errata pt. 2 */ 749 udelay (1000); 750 } 751 752 static void encInit (unsigned char *pEthAddr) 753 { 754 unsigned short phid1 = 0; 755 unsigned short phid2 = 0; 756 757 /* switch to bank 0 */ 758 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); 759 760 /* 761 * Setup the buffer space. The reset values are valid for the 762 * other pointers. 763 */ 764 /* We shall not write to ERXST, see errata pt. 5. Instead we 765 have to make sure that ENC_RX_BUS_START is 0. */ 766 m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1); 767 m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1); 768 769 /* taken from the Linux driver */ 770 m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1); 771 m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1); 772 773 m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1); 774 m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1); 775 776 next_pointer_lsb = (ENC_RX_BUF_START & 0xFF); 777 next_pointer_msb = (ENC_RX_BUF_START >> 8); 778 779 /* verify identification */ 780 phid1 = phyRead (PHY_REG_PHID1); 781 phid2 = phyRead (PHY_REG_PHID2); 782 783 if (phid1 != ENC_PHID1_VALUE 784 || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) { 785 printf ("ERROR: failed to identify controller\n"); 786 printf ("phid1 = %x, phid2 = %x\n", 787 phid1, (phid2 & ENC_PHID2_MASK)); 788 printf ("should be phid1 = %x, phid2 = %x\n", 789 ENC_PHID1_VALUE, ENC_PHID2_VALUE); 790 } 791 792 /* 793 * --- MAC Initialization --- 794 */ 795 796 /* Pull MAC out of Reset */ 797 798 /* switch to bank 2 */ 799 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); 800 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); 801 802 /* enable MAC to receive frames */ 803 /* added some bits from the Linux driver */ 804 m_nic_write_retry (CTL_REG_MACON1 805 ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS) 806 ,10); 807 808 /* configure pad, tx-crc and duplex */ 809 /* added a bit from the Linux driver */ 810 m_nic_write_retry (CTL_REG_MACON3 811 ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN) 812 ,10); 813 814 /* added 4 new lines from the Linux driver */ 815 /* Allow infinite deferals if the medium is continously busy */ 816 m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10); 817 818 /* Late collisions occur beyond 63 bytes */ 819 m_nic_write_retry(CTL_REG_MACLCON2, 63, 10); 820 821 /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */ 822 m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10); 823 824 /* 825 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended 826 * 0x0c for half-duplex. Nothing for full-duplex 827 */ 828 m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10); 829 830 /* set maximum frame length */ 831 m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10); 832 m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10); 833 834 /* 835 * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex 836 * and 0x15 for full duplex. 837 */ 838 m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10); 839 840 /* set MAC address */ 841 842 /* switch to bank 3 */ 843 m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1)); 844 845 m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1); 846 m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1); 847 m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1); 848 m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1); 849 m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1); 850 m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1); 851 852 /* 853 * PHY Initialization taken from the Linux driver 854 */ 855 856 /* Prevent automatic loopback of data beeing transmitted by setting 857 ENC_PHCON2_HDLDIS */ 858 phyWrite(PHY_REG_PHCON2, (1<<8)); 859 860 /* LEDs configuration 861 * LEDA: LACFG = 0100 -> display link status 862 * LEDB: LBCFG = 0111 -> display TX & RX activity 863 * STRCH = 1 -> LED pulses 864 */ 865 phyWrite(PHY_REG_PHLCON, 0x0472); 866 867 /* Reset PDPXMD-bit => half duplex */ 868 phyWrite(PHY_REG_PHCON1, 0); 869 870 /* 871 * Receive settings 872 */ 873 874 #ifdef CONFIG_USE_IRQ 875 /* enable interrupts */ 876 m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE); 877 m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE); 878 m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE); 879 m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE); 880 m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); 881 #endif 882 } 883 884 /***************************************************************************** 885 * 886 * Description: 887 * Read PHY registers. 888 * 889 * NOTE! This function will change to Bank 2. 890 * 891 * Params: 892 * [in] addr address of the register to read 893 * 894 * Returns: 895 * The value in the register 896 */ 897 static unsigned short phyRead (unsigned char addr) 898 { 899 unsigned short ret = 0; 900 901 /* move to bank 2 */ 902 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); 903 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); 904 905 /* write address to MIREGADR */ 906 m_nic_write (CTL_REG_MIREGADR, addr); 907 908 /* set MICMD.MIIRD */ 909 m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD); 910 911 /* taken from the Linux driver */ 912 /* move to bank 3 */ 913 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); 914 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 915 916 /* poll MISTAT.BUSY bit until operation is complete */ 917 while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { 918 static int cnt = 0; 919 920 if (cnt++ >= 1000) { 921 /* GJ - this seems extremely dangerous! */ 922 /* printf("#"); */ 923 cnt = 0; 924 } 925 } 926 927 /* taken from the Linux driver */ 928 /* move to bank 2 */ 929 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); 930 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 931 932 /* clear MICMD.MIIRD */ 933 m_nic_write (CTL_REG_MICMD, 0); 934 935 ret = (m_nic_read (CTL_REG_MIRDH) << 8); 936 ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF); 937 938 return ret; 939 } 940 941 /***************************************************************************** 942 * 943 * Taken from the Linux driver. 944 * Description: 945 * Write PHY registers. 946 * 947 * NOTE! This function will change to Bank 3. 948 * 949 * Params: 950 * [in] addr address of the register to write to 951 * [in] data to be written 952 * 953 * Returns: 954 * None 955 */ 956 static void phyWrite(unsigned char addr, unsigned short data) 957 { 958 /* move to bank 2 */ 959 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); 960 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 961 962 /* write address to MIREGADR */ 963 m_nic_write(CTL_REG_MIREGADR, addr); 964 965 m_nic_write(CTL_REG_MIWRL, data & 0xff); 966 m_nic_write(CTL_REG_MIWRH, data >> 8); 967 968 /* move to bank 3 */ 969 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); 970 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); 971 972 /* poll MISTAT.BUSY bit until operation is complete */ 973 while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { 974 static int cnt = 0; 975 976 if(cnt++ >= 1000) { 977 cnt = 0; 978 } 979 } 980 } 981