1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 * SPDX-License-Identifier: GPL-2.0+ 13 14 Contact Information: 15 Linux NICS <linux.nics@intel.com> 16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 17 18 *******************************************************************************/ 19 /* 20 * Copyright (C) Archway Digital Solutions. 21 * 22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 23 * 2/9/2002 24 * 25 * Copyright (C) Linux Networx. 26 * Massive upgrade to work with the new intel gigabit NICs. 27 * <ebiederman at lnxi dot com> 28 * 29 * Copyright 2011 Freescale Semiconductor, Inc. 30 */ 31 32 #include <common.h> 33 #include <dm.h> 34 #include <errno.h> 35 #include <pci.h> 36 #include "e1000.h" 37 38 #define TOUT_LOOP 100000 39 40 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) 41 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 42 43 #define E1000_DEFAULT_PCI_PBA 0x00000030 44 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 45 46 /* NIC specific static variables go here */ 47 48 /* Intel i210 needs the DMA descriptor rings aligned to 128b */ 49 #define E1000_BUFFER_ALIGN 128 50 51 /* 52 * TODO(sjg@chromium.org): Even with driver model we share these buffers. 53 * Concurrent receiving on multiple active Ethernet devices will not work. 54 * Normally U-Boot does not support this anyway. To fix it in this driver, 55 * move these buffers and the tx/rx pointers to struct e1000_hw. 56 */ 57 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 58 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 59 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 60 61 static int tx_tail; 62 static int rx_tail, rx_last; 63 #ifdef CONFIG_DM_ETH 64 static int num_cards; /* Number of E1000 devices seen so far */ 65 #endif 66 67 static struct pci_device_id e1000_supported[] = { 68 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, 69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, 70 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, 71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, 72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, 73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, 74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, 75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, 76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, 77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, 78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, 79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, 80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, 81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, 82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, 83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, 84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, 85 /* E1000 PCIe card */ 86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, 87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, 88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, 89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, 90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, 91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, 92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, 93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, 94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, 95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, 96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, 97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, 98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, 99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, 100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, 101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, 102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, 103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, 104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, 105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, 106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, 107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, 111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, 112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, 113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, 114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, 115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, 116 117 {} 118 }; 119 120 /* Function forward declarations */ 121 static int e1000_setup_link(struct e1000_hw *hw); 122 static int e1000_setup_fiber_link(struct e1000_hw *hw); 123 static int e1000_setup_copper_link(struct e1000_hw *hw); 124 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 125 static void e1000_config_collision_dist(struct e1000_hw *hw); 126 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 127 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 128 static int e1000_check_for_link(struct e1000_hw *hw); 129 static int e1000_wait_autoneg(struct e1000_hw *hw); 130 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 131 uint16_t * duplex); 132 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 133 uint16_t * phy_data); 134 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 135 uint16_t phy_data); 136 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 137 static int e1000_phy_reset(struct e1000_hw *hw); 138 static int e1000_detect_gig_phy(struct e1000_hw *hw); 139 static void e1000_set_media_type(struct e1000_hw *hw); 140 141 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 142 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 143 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 144 145 #ifndef CONFIG_E1000_NO_NVM 146 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 147 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 148 uint16_t words, 149 uint16_t *data); 150 /****************************************************************************** 151 * Raises the EEPROM's clock input. 152 * 153 * hw - Struct containing variables accessed by shared code 154 * eecd - EECD's current value 155 *****************************************************************************/ 156 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 157 { 158 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 159 * wait 50 microseconds. 160 */ 161 *eecd = *eecd | E1000_EECD_SK; 162 E1000_WRITE_REG(hw, EECD, *eecd); 163 E1000_WRITE_FLUSH(hw); 164 udelay(50); 165 } 166 167 /****************************************************************************** 168 * Lowers the EEPROM's clock input. 169 * 170 * hw - Struct containing variables accessed by shared code 171 * eecd - EECD's current value 172 *****************************************************************************/ 173 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 174 { 175 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 176 * wait 50 microseconds. 177 */ 178 *eecd = *eecd & ~E1000_EECD_SK; 179 E1000_WRITE_REG(hw, EECD, *eecd); 180 E1000_WRITE_FLUSH(hw); 181 udelay(50); 182 } 183 184 /****************************************************************************** 185 * Shift data bits out to the EEPROM. 186 * 187 * hw - Struct containing variables accessed by shared code 188 * data - data to send to the EEPROM 189 * count - number of bits to shift out 190 *****************************************************************************/ 191 static void 192 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 193 { 194 uint32_t eecd; 195 uint32_t mask; 196 197 /* We need to shift "count" bits out to the EEPROM. So, value in the 198 * "data" parameter will be shifted out to the EEPROM one bit at a time. 199 * In order to do this, "data" must be broken down into bits. 200 */ 201 mask = 0x01 << (count - 1); 202 eecd = E1000_READ_REG(hw, EECD); 203 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 204 do { 205 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 206 * and then raising and then lowering the clock (the SK bit controls 207 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 208 * by setting "DI" to "0" and then raising and then lowering the clock. 209 */ 210 eecd &= ~E1000_EECD_DI; 211 212 if (data & mask) 213 eecd |= E1000_EECD_DI; 214 215 E1000_WRITE_REG(hw, EECD, eecd); 216 E1000_WRITE_FLUSH(hw); 217 218 udelay(50); 219 220 e1000_raise_ee_clk(hw, &eecd); 221 e1000_lower_ee_clk(hw, &eecd); 222 223 mask = mask >> 1; 224 225 } while (mask); 226 227 /* We leave the "DI" bit set to "0" when we leave this routine. */ 228 eecd &= ~E1000_EECD_DI; 229 E1000_WRITE_REG(hw, EECD, eecd); 230 } 231 232 /****************************************************************************** 233 * Shift data bits in from the EEPROM 234 * 235 * hw - Struct containing variables accessed by shared code 236 *****************************************************************************/ 237 static uint16_t 238 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 239 { 240 uint32_t eecd; 241 uint32_t i; 242 uint16_t data; 243 244 /* In order to read a register from the EEPROM, we need to shift 'count' 245 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 246 * input to the EEPROM (setting the SK bit), and then reading the 247 * value of the "DO" bit. During this "shifting in" process the 248 * "DI" bit should always be clear. 249 */ 250 251 eecd = E1000_READ_REG(hw, EECD); 252 253 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 254 data = 0; 255 256 for (i = 0; i < count; i++) { 257 data = data << 1; 258 e1000_raise_ee_clk(hw, &eecd); 259 260 eecd = E1000_READ_REG(hw, EECD); 261 262 eecd &= ~(E1000_EECD_DI); 263 if (eecd & E1000_EECD_DO) 264 data |= 1; 265 266 e1000_lower_ee_clk(hw, &eecd); 267 } 268 269 return data; 270 } 271 272 /****************************************************************************** 273 * Returns EEPROM to a "standby" state 274 * 275 * hw - Struct containing variables accessed by shared code 276 *****************************************************************************/ 277 void e1000_standby_eeprom(struct e1000_hw *hw) 278 { 279 struct e1000_eeprom_info *eeprom = &hw->eeprom; 280 uint32_t eecd; 281 282 eecd = E1000_READ_REG(hw, EECD); 283 284 if (eeprom->type == e1000_eeprom_microwire) { 285 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 286 E1000_WRITE_REG(hw, EECD, eecd); 287 E1000_WRITE_FLUSH(hw); 288 udelay(eeprom->delay_usec); 289 290 /* Clock high */ 291 eecd |= E1000_EECD_SK; 292 E1000_WRITE_REG(hw, EECD, eecd); 293 E1000_WRITE_FLUSH(hw); 294 udelay(eeprom->delay_usec); 295 296 /* Select EEPROM */ 297 eecd |= E1000_EECD_CS; 298 E1000_WRITE_REG(hw, EECD, eecd); 299 E1000_WRITE_FLUSH(hw); 300 udelay(eeprom->delay_usec); 301 302 /* Clock low */ 303 eecd &= ~E1000_EECD_SK; 304 E1000_WRITE_REG(hw, EECD, eecd); 305 E1000_WRITE_FLUSH(hw); 306 udelay(eeprom->delay_usec); 307 } else if (eeprom->type == e1000_eeprom_spi) { 308 /* Toggle CS to flush commands */ 309 eecd |= E1000_EECD_CS; 310 E1000_WRITE_REG(hw, EECD, eecd); 311 E1000_WRITE_FLUSH(hw); 312 udelay(eeprom->delay_usec); 313 eecd &= ~E1000_EECD_CS; 314 E1000_WRITE_REG(hw, EECD, eecd); 315 E1000_WRITE_FLUSH(hw); 316 udelay(eeprom->delay_usec); 317 } 318 } 319 320 /*************************************************************************** 321 * Description: Determines if the onboard NVM is FLASH or EEPROM. 322 * 323 * hw - Struct containing variables accessed by shared code 324 ****************************************************************************/ 325 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 326 { 327 uint32_t eecd = 0; 328 329 DEBUGFUNC(); 330 331 if (hw->mac_type == e1000_ich8lan) 332 return false; 333 334 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 335 eecd = E1000_READ_REG(hw, EECD); 336 337 /* Isolate bits 15 & 16 */ 338 eecd = ((eecd >> 15) & 0x03); 339 340 /* If both bits are set, device is Flash type */ 341 if (eecd == 0x03) 342 return false; 343 } 344 return true; 345 } 346 347 /****************************************************************************** 348 * Prepares EEPROM for access 349 * 350 * hw - Struct containing variables accessed by shared code 351 * 352 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 353 * function should be called before issuing a command to the EEPROM. 354 *****************************************************************************/ 355 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 356 { 357 struct e1000_eeprom_info *eeprom = &hw->eeprom; 358 uint32_t eecd, i = 0; 359 360 DEBUGFUNC(); 361 362 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 363 return -E1000_ERR_SWFW_SYNC; 364 eecd = E1000_READ_REG(hw, EECD); 365 366 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 367 /* Request EEPROM Access */ 368 if (hw->mac_type > e1000_82544) { 369 eecd |= E1000_EECD_REQ; 370 E1000_WRITE_REG(hw, EECD, eecd); 371 eecd = E1000_READ_REG(hw, EECD); 372 while ((!(eecd & E1000_EECD_GNT)) && 373 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 374 i++; 375 udelay(5); 376 eecd = E1000_READ_REG(hw, EECD); 377 } 378 if (!(eecd & E1000_EECD_GNT)) { 379 eecd &= ~E1000_EECD_REQ; 380 E1000_WRITE_REG(hw, EECD, eecd); 381 DEBUGOUT("Could not acquire EEPROM grant\n"); 382 return -E1000_ERR_EEPROM; 383 } 384 } 385 } 386 387 /* Setup EEPROM for Read/Write */ 388 389 if (eeprom->type == e1000_eeprom_microwire) { 390 /* Clear SK and DI */ 391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 392 E1000_WRITE_REG(hw, EECD, eecd); 393 394 /* Set CS */ 395 eecd |= E1000_EECD_CS; 396 E1000_WRITE_REG(hw, EECD, eecd); 397 } else if (eeprom->type == e1000_eeprom_spi) { 398 /* Clear SK and CS */ 399 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 400 E1000_WRITE_REG(hw, EECD, eecd); 401 udelay(1); 402 } 403 404 return E1000_SUCCESS; 405 } 406 407 /****************************************************************************** 408 * Sets up eeprom variables in the hw struct. Must be called after mac_type 409 * is configured. Additionally, if this is ICH8, the flash controller GbE 410 * registers must be mapped, or this will crash. 411 * 412 * hw - Struct containing variables accessed by shared code 413 *****************************************************************************/ 414 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 415 { 416 struct e1000_eeprom_info *eeprom = &hw->eeprom; 417 uint32_t eecd; 418 int32_t ret_val = E1000_SUCCESS; 419 uint16_t eeprom_size; 420 421 if (hw->mac_type == e1000_igb) 422 eecd = E1000_READ_REG(hw, I210_EECD); 423 else 424 eecd = E1000_READ_REG(hw, EECD); 425 426 DEBUGFUNC(); 427 428 switch (hw->mac_type) { 429 case e1000_82542_rev2_0: 430 case e1000_82542_rev2_1: 431 case e1000_82543: 432 case e1000_82544: 433 eeprom->type = e1000_eeprom_microwire; 434 eeprom->word_size = 64; 435 eeprom->opcode_bits = 3; 436 eeprom->address_bits = 6; 437 eeprom->delay_usec = 50; 438 eeprom->use_eerd = false; 439 eeprom->use_eewr = false; 440 break; 441 case e1000_82540: 442 case e1000_82545: 443 case e1000_82545_rev_3: 444 case e1000_82546: 445 case e1000_82546_rev_3: 446 eeprom->type = e1000_eeprom_microwire; 447 eeprom->opcode_bits = 3; 448 eeprom->delay_usec = 50; 449 if (eecd & E1000_EECD_SIZE) { 450 eeprom->word_size = 256; 451 eeprom->address_bits = 8; 452 } else { 453 eeprom->word_size = 64; 454 eeprom->address_bits = 6; 455 } 456 eeprom->use_eerd = false; 457 eeprom->use_eewr = false; 458 break; 459 case e1000_82541: 460 case e1000_82541_rev_2: 461 case e1000_82547: 462 case e1000_82547_rev_2: 463 if (eecd & E1000_EECD_TYPE) { 464 eeprom->type = e1000_eeprom_spi; 465 eeprom->opcode_bits = 8; 466 eeprom->delay_usec = 1; 467 if (eecd & E1000_EECD_ADDR_BITS) { 468 eeprom->page_size = 32; 469 eeprom->address_bits = 16; 470 } else { 471 eeprom->page_size = 8; 472 eeprom->address_bits = 8; 473 } 474 } else { 475 eeprom->type = e1000_eeprom_microwire; 476 eeprom->opcode_bits = 3; 477 eeprom->delay_usec = 50; 478 if (eecd & E1000_EECD_ADDR_BITS) { 479 eeprom->word_size = 256; 480 eeprom->address_bits = 8; 481 } else { 482 eeprom->word_size = 64; 483 eeprom->address_bits = 6; 484 } 485 } 486 eeprom->use_eerd = false; 487 eeprom->use_eewr = false; 488 break; 489 case e1000_82571: 490 case e1000_82572: 491 eeprom->type = e1000_eeprom_spi; 492 eeprom->opcode_bits = 8; 493 eeprom->delay_usec = 1; 494 if (eecd & E1000_EECD_ADDR_BITS) { 495 eeprom->page_size = 32; 496 eeprom->address_bits = 16; 497 } else { 498 eeprom->page_size = 8; 499 eeprom->address_bits = 8; 500 } 501 eeprom->use_eerd = false; 502 eeprom->use_eewr = false; 503 break; 504 case e1000_82573: 505 case e1000_82574: 506 eeprom->type = e1000_eeprom_spi; 507 eeprom->opcode_bits = 8; 508 eeprom->delay_usec = 1; 509 if (eecd & E1000_EECD_ADDR_BITS) { 510 eeprom->page_size = 32; 511 eeprom->address_bits = 16; 512 } else { 513 eeprom->page_size = 8; 514 eeprom->address_bits = 8; 515 } 516 if (e1000_is_onboard_nvm_eeprom(hw) == false) { 517 eeprom->use_eerd = true; 518 eeprom->use_eewr = true; 519 520 eeprom->type = e1000_eeprom_flash; 521 eeprom->word_size = 2048; 522 523 /* Ensure that the Autonomous FLASH update bit is cleared due to 524 * Flash update issue on parts which use a FLASH for NVM. */ 525 eecd &= ~E1000_EECD_AUPDEN; 526 E1000_WRITE_REG(hw, EECD, eecd); 527 } 528 break; 529 case e1000_80003es2lan: 530 eeprom->type = e1000_eeprom_spi; 531 eeprom->opcode_bits = 8; 532 eeprom->delay_usec = 1; 533 if (eecd & E1000_EECD_ADDR_BITS) { 534 eeprom->page_size = 32; 535 eeprom->address_bits = 16; 536 } else { 537 eeprom->page_size = 8; 538 eeprom->address_bits = 8; 539 } 540 eeprom->use_eerd = true; 541 eeprom->use_eewr = false; 542 break; 543 case e1000_igb: 544 /* i210 has 4k of iNVM mapped as EEPROM */ 545 eeprom->type = e1000_eeprom_invm; 546 eeprom->opcode_bits = 8; 547 eeprom->delay_usec = 1; 548 eeprom->page_size = 32; 549 eeprom->address_bits = 16; 550 eeprom->use_eerd = true; 551 eeprom->use_eewr = false; 552 break; 553 554 /* ich8lan does not support currently. if needed, please 555 * add corresponding code and functions. 556 */ 557 #if 0 558 case e1000_ich8lan: 559 { 560 int32_t i = 0; 561 562 eeprom->type = e1000_eeprom_ich8; 563 eeprom->use_eerd = false; 564 eeprom->use_eewr = false; 565 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 566 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, 567 ICH_FLASH_GFPREG); 568 /* Zero the shadow RAM structure. But don't load it from NVM 569 * so as to save time for driver init */ 570 if (hw->eeprom_shadow_ram != NULL) { 571 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 572 hw->eeprom_shadow_ram[i].modified = false; 573 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 574 } 575 } 576 577 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 578 ICH_FLASH_SECTOR_SIZE; 579 580 hw->flash_bank_size = ((flash_size >> 16) 581 & ICH_GFPREG_BASE_MASK) + 1; 582 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 583 584 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 585 586 hw->flash_bank_size /= 2 * sizeof(uint16_t); 587 break; 588 } 589 #endif 590 default: 591 break; 592 } 593 594 if (eeprom->type == e1000_eeprom_spi || 595 eeprom->type == e1000_eeprom_invm) { 596 /* eeprom_size will be an enum [0..8] that maps 597 * to eeprom sizes 128B to 598 * 32KB (incremented by powers of 2). 599 */ 600 if (hw->mac_type <= e1000_82547_rev_2) { 601 /* Set to default value for initial eeprom read. */ 602 eeprom->word_size = 64; 603 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 604 &eeprom_size); 605 if (ret_val) 606 return ret_val; 607 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 608 >> EEPROM_SIZE_SHIFT; 609 /* 256B eeprom size was not supported in earlier 610 * hardware, so we bump eeprom_size up one to 611 * ensure that "1" (which maps to 256B) is never 612 * the result used in the shifting logic below. */ 613 if (eeprom_size) 614 eeprom_size++; 615 } else { 616 eeprom_size = (uint16_t)((eecd & 617 E1000_EECD_SIZE_EX_MASK) >> 618 E1000_EECD_SIZE_EX_SHIFT); 619 } 620 621 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 622 } 623 return ret_val; 624 } 625 626 /****************************************************************************** 627 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 628 * 629 * hw - Struct containing variables accessed by shared code 630 *****************************************************************************/ 631 static int32_t 632 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 633 { 634 uint32_t attempts = 100000; 635 uint32_t i, reg = 0; 636 int32_t done = E1000_ERR_EEPROM; 637 638 for (i = 0; i < attempts; i++) { 639 if (eerd == E1000_EEPROM_POLL_READ) { 640 if (hw->mac_type == e1000_igb) 641 reg = E1000_READ_REG(hw, I210_EERD); 642 else 643 reg = E1000_READ_REG(hw, EERD); 644 } else { 645 if (hw->mac_type == e1000_igb) 646 reg = E1000_READ_REG(hw, I210_EEWR); 647 else 648 reg = E1000_READ_REG(hw, EEWR); 649 } 650 651 if (reg & E1000_EEPROM_RW_REG_DONE) { 652 done = E1000_SUCCESS; 653 break; 654 } 655 udelay(5); 656 } 657 658 return done; 659 } 660 661 /****************************************************************************** 662 * Reads a 16 bit word from the EEPROM using the EERD register. 663 * 664 * hw - Struct containing variables accessed by shared code 665 * offset - offset of word in the EEPROM to read 666 * data - word read from the EEPROM 667 * words - number of words to read 668 *****************************************************************************/ 669 static int32_t 670 e1000_read_eeprom_eerd(struct e1000_hw *hw, 671 uint16_t offset, 672 uint16_t words, 673 uint16_t *data) 674 { 675 uint32_t i, eerd = 0; 676 int32_t error = 0; 677 678 for (i = 0; i < words; i++) { 679 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 680 E1000_EEPROM_RW_REG_START; 681 682 if (hw->mac_type == e1000_igb) 683 E1000_WRITE_REG(hw, I210_EERD, eerd); 684 else 685 E1000_WRITE_REG(hw, EERD, eerd); 686 687 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 688 689 if (error) 690 break; 691 692 if (hw->mac_type == e1000_igb) { 693 data[i] = (E1000_READ_REG(hw, I210_EERD) >> 694 E1000_EEPROM_RW_REG_DATA); 695 } else { 696 data[i] = (E1000_READ_REG(hw, EERD) >> 697 E1000_EEPROM_RW_REG_DATA); 698 } 699 700 } 701 702 return error; 703 } 704 705 void e1000_release_eeprom(struct e1000_hw *hw) 706 { 707 uint32_t eecd; 708 709 DEBUGFUNC(); 710 711 eecd = E1000_READ_REG(hw, EECD); 712 713 if (hw->eeprom.type == e1000_eeprom_spi) { 714 eecd |= E1000_EECD_CS; /* Pull CS high */ 715 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 716 717 E1000_WRITE_REG(hw, EECD, eecd); 718 719 udelay(hw->eeprom.delay_usec); 720 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 721 /* cleanup eeprom */ 722 723 /* CS on Microwire is active-high */ 724 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 725 726 E1000_WRITE_REG(hw, EECD, eecd); 727 728 /* Rising edge of clock */ 729 eecd |= E1000_EECD_SK; 730 E1000_WRITE_REG(hw, EECD, eecd); 731 E1000_WRITE_FLUSH(hw); 732 udelay(hw->eeprom.delay_usec); 733 734 /* Falling edge of clock */ 735 eecd &= ~E1000_EECD_SK; 736 E1000_WRITE_REG(hw, EECD, eecd); 737 E1000_WRITE_FLUSH(hw); 738 udelay(hw->eeprom.delay_usec); 739 } 740 741 /* Stop requesting EEPROM access */ 742 if (hw->mac_type > e1000_82544) { 743 eecd &= ~E1000_EECD_REQ; 744 E1000_WRITE_REG(hw, EECD, eecd); 745 } 746 747 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 748 } 749 750 /****************************************************************************** 751 * Reads a 16 bit word from the EEPROM. 752 * 753 * hw - Struct containing variables accessed by shared code 754 *****************************************************************************/ 755 static int32_t 756 e1000_spi_eeprom_ready(struct e1000_hw *hw) 757 { 758 uint16_t retry_count = 0; 759 uint8_t spi_stat_reg; 760 761 DEBUGFUNC(); 762 763 /* Read "Status Register" repeatedly until the LSB is cleared. The 764 * EEPROM will signal that the command has been completed by clearing 765 * bit 0 of the internal status register. If it's not cleared within 766 * 5 milliseconds, then error out. 767 */ 768 retry_count = 0; 769 do { 770 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 771 hw->eeprom.opcode_bits); 772 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 773 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 774 break; 775 776 udelay(5); 777 retry_count += 5; 778 779 e1000_standby_eeprom(hw); 780 } while (retry_count < EEPROM_MAX_RETRY_SPI); 781 782 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 783 * only 0-5mSec on 5V devices) 784 */ 785 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 786 DEBUGOUT("SPI EEPROM Status error\n"); 787 return -E1000_ERR_EEPROM; 788 } 789 790 return E1000_SUCCESS; 791 } 792 793 /****************************************************************************** 794 * Reads a 16 bit word from the EEPROM. 795 * 796 * hw - Struct containing variables accessed by shared code 797 * offset - offset of word in the EEPROM to read 798 * data - word read from the EEPROM 799 *****************************************************************************/ 800 static int32_t 801 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 802 uint16_t words, uint16_t *data) 803 { 804 struct e1000_eeprom_info *eeprom = &hw->eeprom; 805 uint32_t i = 0; 806 807 DEBUGFUNC(); 808 809 /* If eeprom is not yet detected, do so now */ 810 if (eeprom->word_size == 0) 811 e1000_init_eeprom_params(hw); 812 813 /* A check for invalid values: offset too large, too many words, 814 * and not enough words. 815 */ 816 if ((offset >= eeprom->word_size) || 817 (words > eeprom->word_size - offset) || 818 (words == 0)) { 819 DEBUGOUT("\"words\" parameter out of bounds." 820 "Words = %d, size = %d\n", offset, eeprom->word_size); 821 return -E1000_ERR_EEPROM; 822 } 823 824 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 825 * directly. In this case, we need to acquire the EEPROM so that 826 * FW or other port software does not interrupt. 827 */ 828 if (e1000_is_onboard_nvm_eeprom(hw) == true && 829 hw->eeprom.use_eerd == false) { 830 831 /* Prepare the EEPROM for bit-bang reading */ 832 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 833 return -E1000_ERR_EEPROM; 834 } 835 836 /* Eerd register EEPROM access requires no eeprom aquire/release */ 837 if (eeprom->use_eerd == true) 838 return e1000_read_eeprom_eerd(hw, offset, words, data); 839 840 /* ich8lan does not support currently. if needed, please 841 * add corresponding code and functions. 842 */ 843 #if 0 844 /* ICH EEPROM access is done via the ICH flash controller */ 845 if (eeprom->type == e1000_eeprom_ich8) 846 return e1000_read_eeprom_ich8(hw, offset, words, data); 847 #endif 848 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 849 * acquired the EEPROM at this point, so any returns should relase it */ 850 if (eeprom->type == e1000_eeprom_spi) { 851 uint16_t word_in; 852 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 853 854 if (e1000_spi_eeprom_ready(hw)) { 855 e1000_release_eeprom(hw); 856 return -E1000_ERR_EEPROM; 857 } 858 859 e1000_standby_eeprom(hw); 860 861 /* Some SPI eeproms use the 8th address bit embedded in 862 * the opcode */ 863 if ((eeprom->address_bits == 8) && (offset >= 128)) 864 read_opcode |= EEPROM_A8_OPCODE_SPI; 865 866 /* Send the READ command (opcode + addr) */ 867 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 868 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 869 eeprom->address_bits); 870 871 /* Read the data. The address of the eeprom internally 872 * increments with each byte (spi) being read, saving on the 873 * overhead of eeprom setup and tear-down. The address 874 * counter will roll over if reading beyond the size of 875 * the eeprom, thus allowing the entire memory to be read 876 * starting from any offset. */ 877 for (i = 0; i < words; i++) { 878 word_in = e1000_shift_in_ee_bits(hw, 16); 879 data[i] = (word_in >> 8) | (word_in << 8); 880 } 881 } else if (eeprom->type == e1000_eeprom_microwire) { 882 for (i = 0; i < words; i++) { 883 /* Send the READ command (opcode + addr) */ 884 e1000_shift_out_ee_bits(hw, 885 EEPROM_READ_OPCODE_MICROWIRE, 886 eeprom->opcode_bits); 887 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 888 eeprom->address_bits); 889 890 /* Read the data. For microwire, each word requires 891 * the overhead of eeprom setup and tear-down. */ 892 data[i] = e1000_shift_in_ee_bits(hw, 16); 893 e1000_standby_eeprom(hw); 894 } 895 } 896 897 /* End this read operation */ 898 e1000_release_eeprom(hw); 899 900 return E1000_SUCCESS; 901 } 902 903 /****************************************************************************** 904 * Verifies that the EEPROM has a valid checksum 905 * 906 * hw - Struct containing variables accessed by shared code 907 * 908 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 909 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 910 * valid. 911 *****************************************************************************/ 912 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 913 { 914 uint16_t i, checksum, checksum_reg, *buf; 915 916 DEBUGFUNC(); 917 918 /* Allocate a temporary buffer */ 919 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 920 if (!buf) { 921 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); 922 return -E1000_ERR_EEPROM; 923 } 924 925 /* Read the EEPROM */ 926 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 927 E1000_ERR(hw, "Unable to read EEPROM!\n"); 928 return -E1000_ERR_EEPROM; 929 } 930 931 /* Compute the checksum */ 932 checksum = 0; 933 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 934 checksum += buf[i]; 935 checksum = ((uint16_t)EEPROM_SUM) - checksum; 936 checksum_reg = buf[i]; 937 938 /* Verify it! */ 939 if (checksum == checksum_reg) 940 return 0; 941 942 /* Hrm, verification failed, print an error */ 943 E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); 944 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", 945 checksum_reg, checksum); 946 947 return -E1000_ERR_EEPROM; 948 } 949 #endif /* CONFIG_E1000_NO_NVM */ 950 951 /***************************************************************************** 952 * Set PHY to class A mode 953 * Assumes the following operations will follow to enable the new class mode. 954 * 1. Do a PHY soft reset 955 * 2. Restart auto-negotiation or force link. 956 * 957 * hw - Struct containing variables accessed by shared code 958 ****************************************************************************/ 959 static int32_t 960 e1000_set_phy_mode(struct e1000_hw *hw) 961 { 962 #ifndef CONFIG_E1000_NO_NVM 963 int32_t ret_val; 964 uint16_t eeprom_data; 965 966 DEBUGFUNC(); 967 968 if ((hw->mac_type == e1000_82545_rev_3) && 969 (hw->media_type == e1000_media_type_copper)) { 970 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 971 1, &eeprom_data); 972 if (ret_val) 973 return ret_val; 974 975 if ((eeprom_data != EEPROM_RESERVED_WORD) && 976 (eeprom_data & EEPROM_PHY_CLASS_A)) { 977 ret_val = e1000_write_phy_reg(hw, 978 M88E1000_PHY_PAGE_SELECT, 0x000B); 979 if (ret_val) 980 return ret_val; 981 ret_val = e1000_write_phy_reg(hw, 982 M88E1000_PHY_GEN_CONTROL, 0x8104); 983 if (ret_val) 984 return ret_val; 985 986 hw->phy_reset_disable = false; 987 } 988 } 989 #endif 990 return E1000_SUCCESS; 991 } 992 993 #ifndef CONFIG_E1000_NO_NVM 994 /*************************************************************************** 995 * 996 * Obtaining software semaphore bit (SMBI) before resetting PHY. 997 * 998 * hw: Struct containing variables accessed by shared code 999 * 1000 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 1001 * E1000_SUCCESS at any other case. 1002 * 1003 ***************************************************************************/ 1004 static int32_t 1005 e1000_get_software_semaphore(struct e1000_hw *hw) 1006 { 1007 int32_t timeout = hw->eeprom.word_size + 1; 1008 uint32_t swsm; 1009 1010 DEBUGFUNC(); 1011 1012 if (hw->mac_type != e1000_80003es2lan) 1013 return E1000_SUCCESS; 1014 1015 while (timeout) { 1016 swsm = E1000_READ_REG(hw, SWSM); 1017 /* If SMBI bit cleared, it is now set and we hold 1018 * the semaphore */ 1019 if (!(swsm & E1000_SWSM_SMBI)) 1020 break; 1021 mdelay(1); 1022 timeout--; 1023 } 1024 1025 if (!timeout) { 1026 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1027 return -E1000_ERR_RESET; 1028 } 1029 1030 return E1000_SUCCESS; 1031 } 1032 #endif 1033 1034 /*************************************************************************** 1035 * This function clears HW semaphore bits. 1036 * 1037 * hw: Struct containing variables accessed by shared code 1038 * 1039 * returns: - None. 1040 * 1041 ***************************************************************************/ 1042 static void 1043 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1044 { 1045 #ifndef CONFIG_E1000_NO_NVM 1046 uint32_t swsm; 1047 1048 DEBUGFUNC(); 1049 1050 if (!hw->eeprom_semaphore_present) 1051 return; 1052 1053 swsm = E1000_READ_REG(hw, SWSM); 1054 if (hw->mac_type == e1000_80003es2lan) { 1055 /* Release both semaphores. */ 1056 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1057 } else 1058 swsm &= ~(E1000_SWSM_SWESMBI); 1059 E1000_WRITE_REG(hw, SWSM, swsm); 1060 #endif 1061 } 1062 1063 /*************************************************************************** 1064 * 1065 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1066 * adapter or Eeprom access. 1067 * 1068 * hw: Struct containing variables accessed by shared code 1069 * 1070 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1071 * E1000_SUCCESS at any other case. 1072 * 1073 ***************************************************************************/ 1074 static int32_t 1075 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1076 { 1077 #ifndef CONFIG_E1000_NO_NVM 1078 int32_t timeout; 1079 uint32_t swsm; 1080 1081 DEBUGFUNC(); 1082 1083 if (!hw->eeprom_semaphore_present) 1084 return E1000_SUCCESS; 1085 1086 if (hw->mac_type == e1000_80003es2lan) { 1087 /* Get the SW semaphore. */ 1088 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1089 return -E1000_ERR_EEPROM; 1090 } 1091 1092 /* Get the FW semaphore. */ 1093 timeout = hw->eeprom.word_size + 1; 1094 while (timeout) { 1095 swsm = E1000_READ_REG(hw, SWSM); 1096 swsm |= E1000_SWSM_SWESMBI; 1097 E1000_WRITE_REG(hw, SWSM, swsm); 1098 /* if we managed to set the bit we got the semaphore. */ 1099 swsm = E1000_READ_REG(hw, SWSM); 1100 if (swsm & E1000_SWSM_SWESMBI) 1101 break; 1102 1103 udelay(50); 1104 timeout--; 1105 } 1106 1107 if (!timeout) { 1108 /* Release semaphores */ 1109 e1000_put_hw_eeprom_semaphore(hw); 1110 DEBUGOUT("Driver can't access the Eeprom - " 1111 "SWESMBI bit is set.\n"); 1112 return -E1000_ERR_EEPROM; 1113 } 1114 #endif 1115 return E1000_SUCCESS; 1116 } 1117 1118 /* Take ownership of the PHY */ 1119 static int32_t 1120 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1121 { 1122 uint32_t swfw_sync = 0; 1123 uint32_t swmask = mask; 1124 uint32_t fwmask = mask << 16; 1125 int32_t timeout = 200; 1126 1127 DEBUGFUNC(); 1128 while (timeout) { 1129 if (e1000_get_hw_eeprom_semaphore(hw)) 1130 return -E1000_ERR_SWFW_SYNC; 1131 1132 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1133 if (!(swfw_sync & (fwmask | swmask))) 1134 break; 1135 1136 /* firmware currently using resource (fwmask) */ 1137 /* or other software thread currently using resource (swmask) */ 1138 e1000_put_hw_eeprom_semaphore(hw); 1139 mdelay(5); 1140 timeout--; 1141 } 1142 1143 if (!timeout) { 1144 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1145 return -E1000_ERR_SWFW_SYNC; 1146 } 1147 1148 swfw_sync |= swmask; 1149 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1150 1151 e1000_put_hw_eeprom_semaphore(hw); 1152 return E1000_SUCCESS; 1153 } 1154 1155 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 1156 { 1157 uint32_t swfw_sync = 0; 1158 1159 DEBUGFUNC(); 1160 while (e1000_get_hw_eeprom_semaphore(hw)) 1161 ; /* Empty */ 1162 1163 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1164 swfw_sync &= ~mask; 1165 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1166 1167 e1000_put_hw_eeprom_semaphore(hw); 1168 } 1169 1170 static bool e1000_is_second_port(struct e1000_hw *hw) 1171 { 1172 switch (hw->mac_type) { 1173 case e1000_80003es2lan: 1174 case e1000_82546: 1175 case e1000_82571: 1176 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1177 return true; 1178 /* Fallthrough */ 1179 default: 1180 return false; 1181 } 1182 } 1183 1184 #ifndef CONFIG_E1000_NO_NVM 1185 /****************************************************************************** 1186 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1187 * second function of dual function devices 1188 * 1189 * nic - Struct containing variables accessed by shared code 1190 *****************************************************************************/ 1191 static int 1192 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) 1193 { 1194 uint16_t offset; 1195 uint16_t eeprom_data; 1196 uint32_t reg_data = 0; 1197 int i; 1198 1199 DEBUGFUNC(); 1200 1201 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1202 offset = i >> 1; 1203 if (hw->mac_type == e1000_igb) { 1204 /* i210 preloads MAC address into RAL/RAH registers */ 1205 if (offset == 0) 1206 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 1207 else if (offset == 1) 1208 reg_data >>= 16; 1209 else if (offset == 2) 1210 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 1211 eeprom_data = reg_data & 0xffff; 1212 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1213 DEBUGOUT("EEPROM Read Error\n"); 1214 return -E1000_ERR_EEPROM; 1215 } 1216 enetaddr[i] = eeprom_data & 0xff; 1217 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1218 } 1219 1220 /* Invert the last bit if this is the second device */ 1221 if (e1000_is_second_port(hw)) 1222 enetaddr[5] ^= 1; 1223 1224 #ifdef CONFIG_E1000_FALLBACK_MAC 1225 if (!is_valid_ethaddr(nic->enetaddr)) { 1226 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; 1227 1228 memcpy(enetaddr, fb_mac, NODE_ADDRESS_SIZE); 1229 } 1230 #endif 1231 return 0; 1232 } 1233 #endif 1234 1235 /****************************************************************************** 1236 * Initializes receive address filters. 1237 * 1238 * hw - Struct containing variables accessed by shared code 1239 * 1240 * Places the MAC address in receive address register 0 and clears the rest 1241 * of the receive addresss registers. Clears the multicast table. Assumes 1242 * the receiver is in reset when the routine is called. 1243 *****************************************************************************/ 1244 static void 1245 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) 1246 { 1247 uint32_t i; 1248 uint32_t addr_low; 1249 uint32_t addr_high; 1250 1251 DEBUGFUNC(); 1252 1253 /* Setup the receive address. */ 1254 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1255 addr_low = (enetaddr[0] | 1256 (enetaddr[1] << 8) | 1257 (enetaddr[2] << 16) | (enetaddr[3] << 24)); 1258 1259 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); 1260 1261 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1262 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1263 1264 /* Zero out the other 15 receive addresses. */ 1265 DEBUGOUT("Clearing RAR[1-15]\n"); 1266 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1267 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1268 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1269 } 1270 } 1271 1272 /****************************************************************************** 1273 * Clears the VLAN filer table 1274 * 1275 * hw - Struct containing variables accessed by shared code 1276 *****************************************************************************/ 1277 static void 1278 e1000_clear_vfta(struct e1000_hw *hw) 1279 { 1280 uint32_t offset; 1281 1282 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1283 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1284 } 1285 1286 /****************************************************************************** 1287 * Set the mac type member in the hw struct. 1288 * 1289 * hw - Struct containing variables accessed by shared code 1290 *****************************************************************************/ 1291 int32_t 1292 e1000_set_mac_type(struct e1000_hw *hw) 1293 { 1294 DEBUGFUNC(); 1295 1296 switch (hw->device_id) { 1297 case E1000_DEV_ID_82542: 1298 switch (hw->revision_id) { 1299 case E1000_82542_2_0_REV_ID: 1300 hw->mac_type = e1000_82542_rev2_0; 1301 break; 1302 case E1000_82542_2_1_REV_ID: 1303 hw->mac_type = e1000_82542_rev2_1; 1304 break; 1305 default: 1306 /* Invalid 82542 revision ID */ 1307 return -E1000_ERR_MAC_TYPE; 1308 } 1309 break; 1310 case E1000_DEV_ID_82543GC_FIBER: 1311 case E1000_DEV_ID_82543GC_COPPER: 1312 hw->mac_type = e1000_82543; 1313 break; 1314 case E1000_DEV_ID_82544EI_COPPER: 1315 case E1000_DEV_ID_82544EI_FIBER: 1316 case E1000_DEV_ID_82544GC_COPPER: 1317 case E1000_DEV_ID_82544GC_LOM: 1318 hw->mac_type = e1000_82544; 1319 break; 1320 case E1000_DEV_ID_82540EM: 1321 case E1000_DEV_ID_82540EM_LOM: 1322 case E1000_DEV_ID_82540EP: 1323 case E1000_DEV_ID_82540EP_LOM: 1324 case E1000_DEV_ID_82540EP_LP: 1325 hw->mac_type = e1000_82540; 1326 break; 1327 case E1000_DEV_ID_82545EM_COPPER: 1328 case E1000_DEV_ID_82545EM_FIBER: 1329 hw->mac_type = e1000_82545; 1330 break; 1331 case E1000_DEV_ID_82545GM_COPPER: 1332 case E1000_DEV_ID_82545GM_FIBER: 1333 case E1000_DEV_ID_82545GM_SERDES: 1334 hw->mac_type = e1000_82545_rev_3; 1335 break; 1336 case E1000_DEV_ID_82546EB_COPPER: 1337 case E1000_DEV_ID_82546EB_FIBER: 1338 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1339 hw->mac_type = e1000_82546; 1340 break; 1341 case E1000_DEV_ID_82546GB_COPPER: 1342 case E1000_DEV_ID_82546GB_FIBER: 1343 case E1000_DEV_ID_82546GB_SERDES: 1344 case E1000_DEV_ID_82546GB_PCIE: 1345 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1346 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1347 hw->mac_type = e1000_82546_rev_3; 1348 break; 1349 case E1000_DEV_ID_82541EI: 1350 case E1000_DEV_ID_82541EI_MOBILE: 1351 case E1000_DEV_ID_82541ER_LOM: 1352 hw->mac_type = e1000_82541; 1353 break; 1354 case E1000_DEV_ID_82541ER: 1355 case E1000_DEV_ID_82541GI: 1356 case E1000_DEV_ID_82541GI_LF: 1357 case E1000_DEV_ID_82541GI_MOBILE: 1358 hw->mac_type = e1000_82541_rev_2; 1359 break; 1360 case E1000_DEV_ID_82547EI: 1361 case E1000_DEV_ID_82547EI_MOBILE: 1362 hw->mac_type = e1000_82547; 1363 break; 1364 case E1000_DEV_ID_82547GI: 1365 hw->mac_type = e1000_82547_rev_2; 1366 break; 1367 case E1000_DEV_ID_82571EB_COPPER: 1368 case E1000_DEV_ID_82571EB_FIBER: 1369 case E1000_DEV_ID_82571EB_SERDES: 1370 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1371 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1372 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1373 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1374 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1375 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1376 hw->mac_type = e1000_82571; 1377 break; 1378 case E1000_DEV_ID_82572EI_COPPER: 1379 case E1000_DEV_ID_82572EI_FIBER: 1380 case E1000_DEV_ID_82572EI_SERDES: 1381 case E1000_DEV_ID_82572EI: 1382 hw->mac_type = e1000_82572; 1383 break; 1384 case E1000_DEV_ID_82573E: 1385 case E1000_DEV_ID_82573E_IAMT: 1386 case E1000_DEV_ID_82573L: 1387 hw->mac_type = e1000_82573; 1388 break; 1389 case E1000_DEV_ID_82574L: 1390 hw->mac_type = e1000_82574; 1391 break; 1392 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1393 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1394 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1395 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1396 hw->mac_type = e1000_80003es2lan; 1397 break; 1398 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1399 case E1000_DEV_ID_ICH8_IGP_AMT: 1400 case E1000_DEV_ID_ICH8_IGP_C: 1401 case E1000_DEV_ID_ICH8_IFE: 1402 case E1000_DEV_ID_ICH8_IFE_GT: 1403 case E1000_DEV_ID_ICH8_IFE_G: 1404 case E1000_DEV_ID_ICH8_IGP_M: 1405 hw->mac_type = e1000_ich8lan; 1406 break; 1407 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: 1408 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: 1409 case PCI_DEVICE_ID_INTEL_I210_COPPER: 1410 case PCI_DEVICE_ID_INTEL_I211_COPPER: 1411 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 1412 case PCI_DEVICE_ID_INTEL_I210_SERDES: 1413 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 1414 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 1415 hw->mac_type = e1000_igb; 1416 break; 1417 default: 1418 /* Should never have loaded on this device */ 1419 return -E1000_ERR_MAC_TYPE; 1420 } 1421 return E1000_SUCCESS; 1422 } 1423 1424 /****************************************************************************** 1425 * Reset the transmit and receive units; mask and clear all interrupts. 1426 * 1427 * hw - Struct containing variables accessed by shared code 1428 *****************************************************************************/ 1429 void 1430 e1000_reset_hw(struct e1000_hw *hw) 1431 { 1432 uint32_t ctrl; 1433 uint32_t ctrl_ext; 1434 uint32_t manc; 1435 uint32_t pba = 0; 1436 uint32_t reg; 1437 1438 DEBUGFUNC(); 1439 1440 /* get the correct pba value for both PCI and PCIe*/ 1441 if (hw->mac_type < e1000_82571) 1442 pba = E1000_DEFAULT_PCI_PBA; 1443 else 1444 pba = E1000_DEFAULT_PCIE_PBA; 1445 1446 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1447 if (hw->mac_type == e1000_82542_rev2_0) { 1448 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1449 pci_write_config_word(hw->pdev, PCI_COMMAND, 1450 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1451 } 1452 1453 /* Clear interrupt mask to stop board from generating interrupts */ 1454 DEBUGOUT("Masking off all interrupts\n"); 1455 if (hw->mac_type == e1000_igb) 1456 E1000_WRITE_REG(hw, I210_IAM, 0); 1457 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1458 1459 /* Disable the Transmit and Receive units. Then delay to allow 1460 * any pending transactions to complete before we hit the MAC with 1461 * the global reset. 1462 */ 1463 E1000_WRITE_REG(hw, RCTL, 0); 1464 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1465 E1000_WRITE_FLUSH(hw); 1466 1467 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1468 hw->tbi_compatibility_on = false; 1469 1470 /* Delay to allow any outstanding PCI transactions to complete before 1471 * resetting the device 1472 */ 1473 mdelay(10); 1474 1475 /* Issue a global reset to the MAC. This will reset the chip's 1476 * transmit, receive, DMA, and link units. It will not effect 1477 * the current PCI configuration. The global reset bit is self- 1478 * clearing, and should clear within a microsecond. 1479 */ 1480 DEBUGOUT("Issuing a global reset to MAC\n"); 1481 ctrl = E1000_READ_REG(hw, CTRL); 1482 1483 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1484 1485 /* Force a reload from the EEPROM if necessary */ 1486 if (hw->mac_type == e1000_igb) { 1487 mdelay(20); 1488 reg = E1000_READ_REG(hw, STATUS); 1489 if (reg & E1000_STATUS_PF_RST_DONE) 1490 DEBUGOUT("PF OK\n"); 1491 reg = E1000_READ_REG(hw, I210_EECD); 1492 if (reg & E1000_EECD_AUTO_RD) 1493 DEBUGOUT("EEC OK\n"); 1494 } else if (hw->mac_type < e1000_82540) { 1495 /* Wait for reset to complete */ 1496 udelay(10); 1497 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1498 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1499 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1500 E1000_WRITE_FLUSH(hw); 1501 /* Wait for EEPROM reload */ 1502 mdelay(2); 1503 } else { 1504 /* Wait for EEPROM reload (it happens automatically) */ 1505 mdelay(4); 1506 /* Dissable HW ARPs on ASF enabled adapters */ 1507 manc = E1000_READ_REG(hw, MANC); 1508 manc &= ~(E1000_MANC_ARP_EN); 1509 E1000_WRITE_REG(hw, MANC, manc); 1510 } 1511 1512 /* Clear interrupt mask to stop board from generating interrupts */ 1513 DEBUGOUT("Masking off all interrupts\n"); 1514 if (hw->mac_type == e1000_igb) 1515 E1000_WRITE_REG(hw, I210_IAM, 0); 1516 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1517 1518 /* Clear any pending interrupt events. */ 1519 E1000_READ_REG(hw, ICR); 1520 1521 /* If MWI was previously enabled, reenable it. */ 1522 if (hw->mac_type == e1000_82542_rev2_0) { 1523 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1524 } 1525 if (hw->mac_type != e1000_igb) 1526 E1000_WRITE_REG(hw, PBA, pba); 1527 } 1528 1529 /****************************************************************************** 1530 * 1531 * Initialize a number of hardware-dependent bits 1532 * 1533 * hw: Struct containing variables accessed by shared code 1534 * 1535 * This function contains hardware limitation workarounds for PCI-E adapters 1536 * 1537 *****************************************************************************/ 1538 static void 1539 e1000_initialize_hardware_bits(struct e1000_hw *hw) 1540 { 1541 if ((hw->mac_type >= e1000_82571) && 1542 (!hw->initialize_hw_bits_disable)) { 1543 /* Settings common to all PCI-express silicon */ 1544 uint32_t reg_ctrl, reg_ctrl_ext; 1545 uint32_t reg_tarc0, reg_tarc1; 1546 uint32_t reg_tctl; 1547 uint32_t reg_txdctl, reg_txdctl1; 1548 1549 /* link autonegotiation/sync workarounds */ 1550 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1551 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1552 1553 /* Enable not-done TX descriptor counting */ 1554 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1555 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1556 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1557 1558 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1559 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1560 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1561 1562 /* IGB is cool */ 1563 if (hw->mac_type == e1000_igb) 1564 return; 1565 1566 switch (hw->mac_type) { 1567 case e1000_82571: 1568 case e1000_82572: 1569 /* Clear PHY TX compatible mode bits */ 1570 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1571 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1572 1573 /* link autonegotiation/sync workarounds */ 1574 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1575 1576 /* TX ring control fixes */ 1577 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1578 1579 /* Multiple read bit is reversed polarity */ 1580 reg_tctl = E1000_READ_REG(hw, TCTL); 1581 if (reg_tctl & E1000_TCTL_MULR) 1582 reg_tarc1 &= ~(1 << 28); 1583 else 1584 reg_tarc1 |= (1 << 28); 1585 1586 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1587 break; 1588 case e1000_82573: 1589 case e1000_82574: 1590 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1591 reg_ctrl_ext &= ~(1 << 23); 1592 reg_ctrl_ext |= (1 << 22); 1593 1594 /* TX byte count fix */ 1595 reg_ctrl = E1000_READ_REG(hw, CTRL); 1596 reg_ctrl &= ~(1 << 29); 1597 1598 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1599 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1600 break; 1601 case e1000_80003es2lan: 1602 /* improve small packet performace for fiber/serdes */ 1603 if ((hw->media_type == e1000_media_type_fiber) 1604 || (hw->media_type == 1605 e1000_media_type_internal_serdes)) { 1606 reg_tarc0 &= ~(1 << 20); 1607 } 1608 1609 /* Multiple read bit is reversed polarity */ 1610 reg_tctl = E1000_READ_REG(hw, TCTL); 1611 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1612 if (reg_tctl & E1000_TCTL_MULR) 1613 reg_tarc1 &= ~(1 << 28); 1614 else 1615 reg_tarc1 |= (1 << 28); 1616 1617 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1618 break; 1619 case e1000_ich8lan: 1620 /* Reduce concurrent DMA requests to 3 from 4 */ 1621 if ((hw->revision_id < 3) || 1622 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1623 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1624 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1625 1626 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1627 reg_ctrl_ext |= (1 << 22); 1628 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1629 1630 /* workaround TX hang with TSO=on */ 1631 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1632 1633 /* Multiple read bit is reversed polarity */ 1634 reg_tctl = E1000_READ_REG(hw, TCTL); 1635 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1636 if (reg_tctl & E1000_TCTL_MULR) 1637 reg_tarc1 &= ~(1 << 28); 1638 else 1639 reg_tarc1 |= (1 << 28); 1640 1641 /* workaround TX hang with TSO=on */ 1642 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1643 1644 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1645 break; 1646 default: 1647 break; 1648 } 1649 1650 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1651 } 1652 } 1653 1654 /****************************************************************************** 1655 * Performs basic configuration of the adapter. 1656 * 1657 * hw - Struct containing variables accessed by shared code 1658 * 1659 * Assumes that the controller has previously been reset and is in a 1660 * post-reset uninitialized state. Initializes the receive address registers, 1661 * multicast table, and VLAN filter table. Calls routines to setup link 1662 * configuration and flow control settings. Clears all on-chip counters. Leaves 1663 * the transmit and receive units disabled and uninitialized. 1664 *****************************************************************************/ 1665 static int 1666 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) 1667 { 1668 uint32_t ctrl; 1669 uint32_t i; 1670 int32_t ret_val; 1671 uint16_t pcix_cmd_word; 1672 uint16_t pcix_stat_hi_word; 1673 uint16_t cmd_mmrbc; 1674 uint16_t stat_mmrbc; 1675 uint32_t mta_size; 1676 uint32_t reg_data; 1677 uint32_t ctrl_ext; 1678 DEBUGFUNC(); 1679 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1680 if ((hw->mac_type == e1000_ich8lan) && 1681 ((hw->revision_id < 3) || 1682 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1683 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1684 reg_data = E1000_READ_REG(hw, STATUS); 1685 reg_data &= ~0x80000000; 1686 E1000_WRITE_REG(hw, STATUS, reg_data); 1687 } 1688 /* Do not need initialize Identification LED */ 1689 1690 /* Set the media type and TBI compatibility */ 1691 e1000_set_media_type(hw); 1692 1693 /* Must be called after e1000_set_media_type 1694 * because media_type is used */ 1695 e1000_initialize_hardware_bits(hw); 1696 1697 /* Disabling VLAN filtering. */ 1698 DEBUGOUT("Initializing the IEEE VLAN\n"); 1699 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1700 if (hw->mac_type != e1000_ich8lan) { 1701 if (hw->mac_type < e1000_82545_rev_3) 1702 E1000_WRITE_REG(hw, VET, 0); 1703 e1000_clear_vfta(hw); 1704 } 1705 1706 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1707 if (hw->mac_type == e1000_82542_rev2_0) { 1708 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1709 pci_write_config_word(hw->pdev, PCI_COMMAND, 1710 hw-> 1711 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1712 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1713 E1000_WRITE_FLUSH(hw); 1714 mdelay(5); 1715 } 1716 1717 /* Setup the receive address. This involves initializing all of the Receive 1718 * Address Registers (RARs 0 - 15). 1719 */ 1720 e1000_init_rx_addrs(hw, enetaddr); 1721 1722 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1723 if (hw->mac_type == e1000_82542_rev2_0) { 1724 E1000_WRITE_REG(hw, RCTL, 0); 1725 E1000_WRITE_FLUSH(hw); 1726 mdelay(1); 1727 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1728 } 1729 1730 /* Zero out the Multicast HASH table */ 1731 DEBUGOUT("Zeroing the MTA\n"); 1732 mta_size = E1000_MC_TBL_SIZE; 1733 if (hw->mac_type == e1000_ich8lan) 1734 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1735 for (i = 0; i < mta_size; i++) { 1736 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1737 /* use write flush to prevent Memory Write Block (MWB) from 1738 * occuring when accessing our register space */ 1739 E1000_WRITE_FLUSH(hw); 1740 } 1741 #if 0 1742 /* Set the PCI priority bit correctly in the CTRL register. This 1743 * determines if the adapter gives priority to receives, or if it 1744 * gives equal priority to transmits and receives. Valid only on 1745 * 82542 and 82543 silicon. 1746 */ 1747 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 1748 ctrl = E1000_READ_REG(hw, CTRL); 1749 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1750 } 1751 #endif 1752 switch (hw->mac_type) { 1753 case e1000_82545_rev_3: 1754 case e1000_82546_rev_3: 1755 case e1000_igb: 1756 break; 1757 default: 1758 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1759 if (hw->bus_type == e1000_bus_type_pcix) { 1760 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1761 &pcix_cmd_word); 1762 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 1763 &pcix_stat_hi_word); 1764 cmd_mmrbc = 1765 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1766 PCIX_COMMAND_MMRBC_SHIFT; 1767 stat_mmrbc = 1768 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1769 PCIX_STATUS_HI_MMRBC_SHIFT; 1770 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1771 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1772 if (cmd_mmrbc > stat_mmrbc) { 1773 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1774 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1775 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 1776 pcix_cmd_word); 1777 } 1778 } 1779 break; 1780 } 1781 1782 /* More time needed for PHY to initialize */ 1783 if (hw->mac_type == e1000_ich8lan) 1784 mdelay(15); 1785 if (hw->mac_type == e1000_igb) 1786 mdelay(15); 1787 1788 /* Call a subroutine to configure the link and setup flow control. */ 1789 ret_val = e1000_setup_link(hw); 1790 1791 /* Set the transmit descriptor write-back policy */ 1792 if (hw->mac_type > e1000_82544) { 1793 ctrl = E1000_READ_REG(hw, TXDCTL); 1794 ctrl = 1795 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1796 E1000_TXDCTL_FULL_TX_DESC_WB; 1797 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1798 } 1799 1800 /* Set the receive descriptor write back policy */ 1801 if (hw->mac_type >= e1000_82571) { 1802 ctrl = E1000_READ_REG(hw, RXDCTL); 1803 ctrl = 1804 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1805 E1000_RXDCTL_FULL_RX_DESC_WB; 1806 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1807 } 1808 1809 switch (hw->mac_type) { 1810 default: 1811 break; 1812 case e1000_80003es2lan: 1813 /* Enable retransmit on late collisions */ 1814 reg_data = E1000_READ_REG(hw, TCTL); 1815 reg_data |= E1000_TCTL_RTLC; 1816 E1000_WRITE_REG(hw, TCTL, reg_data); 1817 1818 /* Configure Gigabit Carry Extend Padding */ 1819 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1820 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1821 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1822 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1823 1824 /* Configure Transmit Inter-Packet Gap */ 1825 reg_data = E1000_READ_REG(hw, TIPG); 1826 reg_data &= ~E1000_TIPG_IPGT_MASK; 1827 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1828 E1000_WRITE_REG(hw, TIPG, reg_data); 1829 1830 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1831 reg_data &= ~0x00100000; 1832 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1833 /* Fall through */ 1834 case e1000_82571: 1835 case e1000_82572: 1836 case e1000_ich8lan: 1837 ctrl = E1000_READ_REG(hw, TXDCTL1); 1838 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 1839 | E1000_TXDCTL_FULL_TX_DESC_WB; 1840 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1841 break; 1842 case e1000_82573: 1843 case e1000_82574: 1844 reg_data = E1000_READ_REG(hw, GCR); 1845 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1846 E1000_WRITE_REG(hw, GCR, reg_data); 1847 case e1000_igb: 1848 break; 1849 } 1850 1851 #if 0 1852 /* Clear all of the statistics registers (clear on read). It is 1853 * important that we do this after we have tried to establish link 1854 * because the symbol error count will increment wildly if there 1855 * is no link. 1856 */ 1857 e1000_clear_hw_cntrs(hw); 1858 1859 /* ICH8 No-snoop bits are opposite polarity. 1860 * Set to snoop by default after reset. */ 1861 if (hw->mac_type == e1000_ich8lan) 1862 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); 1863 #endif 1864 1865 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1866 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1867 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1868 /* Relaxed ordering must be disabled to avoid a parity 1869 * error crash in a PCI slot. */ 1870 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1871 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1872 } 1873 1874 return ret_val; 1875 } 1876 1877 /****************************************************************************** 1878 * Configures flow control and link settings. 1879 * 1880 * hw - Struct containing variables accessed by shared code 1881 * 1882 * Determines which flow control settings to use. Calls the apropriate media- 1883 * specific link configuration function. Configures the flow control settings. 1884 * Assuming the adapter has a valid link partner, a valid link should be 1885 * established. Assumes the hardware has previously been reset and the 1886 * transmitter and receiver are not enabled. 1887 *****************************************************************************/ 1888 static int 1889 e1000_setup_link(struct e1000_hw *hw) 1890 { 1891 int32_t ret_val; 1892 #ifndef CONFIG_E1000_NO_NVM 1893 uint32_t ctrl_ext; 1894 uint16_t eeprom_data; 1895 #endif 1896 1897 DEBUGFUNC(); 1898 1899 /* In the case of the phy reset being blocked, we already have a link. 1900 * We do not have to set it up again. */ 1901 if (e1000_check_phy_reset_block(hw)) 1902 return E1000_SUCCESS; 1903 1904 #ifndef CONFIG_E1000_NO_NVM 1905 /* Read and store word 0x0F of the EEPROM. This word contains bits 1906 * that determine the hardware's default PAUSE (flow control) mode, 1907 * a bit that determines whether the HW defaults to enabling or 1908 * disabling auto-negotiation, and the direction of the 1909 * SW defined pins. If there is no SW over-ride of the flow 1910 * control setting, then the variable hw->fc will 1911 * be initialized based on a value in the EEPROM. 1912 */ 1913 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 1914 &eeprom_data) < 0) { 1915 DEBUGOUT("EEPROM Read Error\n"); 1916 return -E1000_ERR_EEPROM; 1917 } 1918 #endif 1919 if (hw->fc == e1000_fc_default) { 1920 switch (hw->mac_type) { 1921 case e1000_ich8lan: 1922 case e1000_82573: 1923 case e1000_82574: 1924 case e1000_igb: 1925 hw->fc = e1000_fc_full; 1926 break; 1927 default: 1928 #ifndef CONFIG_E1000_NO_NVM 1929 ret_val = e1000_read_eeprom(hw, 1930 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 1931 if (ret_val) { 1932 DEBUGOUT("EEPROM Read Error\n"); 1933 return -E1000_ERR_EEPROM; 1934 } 1935 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1936 hw->fc = e1000_fc_none; 1937 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1938 EEPROM_WORD0F_ASM_DIR) 1939 hw->fc = e1000_fc_tx_pause; 1940 else 1941 #endif 1942 hw->fc = e1000_fc_full; 1943 break; 1944 } 1945 } 1946 1947 /* We want to save off the original Flow Control configuration just 1948 * in case we get disconnected and then reconnected into a different 1949 * hub or switch with different Flow Control capabilities. 1950 */ 1951 if (hw->mac_type == e1000_82542_rev2_0) 1952 hw->fc &= (~e1000_fc_tx_pause); 1953 1954 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1955 hw->fc &= (~e1000_fc_rx_pause); 1956 1957 hw->original_fc = hw->fc; 1958 1959 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 1960 1961 #ifndef CONFIG_E1000_NO_NVM 1962 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1963 * polarity value for the SW controlled pins, and setup the 1964 * Extended Device Control reg with that info. 1965 * This is needed because one of the SW controlled pins is used for 1966 * signal detection. So this should be done before e1000_setup_pcs_link() 1967 * or e1000_phy_setup() is called. 1968 */ 1969 if (hw->mac_type == e1000_82543) { 1970 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1971 SWDPIO__EXT_SHIFT); 1972 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1973 } 1974 #endif 1975 1976 /* Call the necessary subroutine to configure the link. */ 1977 ret_val = (hw->media_type == e1000_media_type_fiber) ? 1978 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); 1979 if (ret_val < 0) { 1980 return ret_val; 1981 } 1982 1983 /* Initialize the flow control address, type, and PAUSE timer 1984 * registers to their default values. This is done even if flow 1985 * control is disabled, because it does not hurt anything to 1986 * initialize these registers. 1987 */ 1988 DEBUGOUT("Initializing the Flow Control address, type" 1989 "and timer regs\n"); 1990 1991 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1992 if (hw->mac_type != e1000_ich8lan) { 1993 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1994 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1995 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1996 } 1997 1998 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1999 2000 /* Set the flow control receive threshold registers. Normally, 2001 * these registers will be set to a default threshold that may be 2002 * adjusted later by the driver's runtime code. However, if the 2003 * ability to transmit pause frames in not enabled, then these 2004 * registers will be set to 0. 2005 */ 2006 if (!(hw->fc & e1000_fc_tx_pause)) { 2007 E1000_WRITE_REG(hw, FCRTL, 0); 2008 E1000_WRITE_REG(hw, FCRTH, 0); 2009 } else { 2010 /* We need to set up the Receive Threshold high and low water marks 2011 * as well as (optionally) enabling the transmission of XON frames. 2012 */ 2013 if (hw->fc_send_xon) { 2014 E1000_WRITE_REG(hw, FCRTL, 2015 (hw->fc_low_water | E1000_FCRTL_XONE)); 2016 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2017 } else { 2018 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 2019 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2020 } 2021 } 2022 return ret_val; 2023 } 2024 2025 /****************************************************************************** 2026 * Sets up link for a fiber based adapter 2027 * 2028 * hw - Struct containing variables accessed by shared code 2029 * 2030 * Manipulates Physical Coding Sublayer functions in order to configure 2031 * link. Assumes the hardware has been previously reset and the transmitter 2032 * and receiver are not enabled. 2033 *****************************************************************************/ 2034 static int 2035 e1000_setup_fiber_link(struct e1000_hw *hw) 2036 { 2037 uint32_t ctrl; 2038 uint32_t status; 2039 uint32_t txcw = 0; 2040 uint32_t i; 2041 uint32_t signal; 2042 int32_t ret_val; 2043 2044 DEBUGFUNC(); 2045 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 2046 * set when the optics detect a signal. On older adapters, it will be 2047 * cleared when there is a signal 2048 */ 2049 ctrl = E1000_READ_REG(hw, CTRL); 2050 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 2051 signal = E1000_CTRL_SWDPIN1; 2052 else 2053 signal = 0; 2054 2055 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, 2056 ctrl); 2057 /* Take the link out of reset */ 2058 ctrl &= ~(E1000_CTRL_LRST); 2059 2060 e1000_config_collision_dist(hw); 2061 2062 /* Check for a software override of the flow control settings, and setup 2063 * the device accordingly. If auto-negotiation is enabled, then software 2064 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 2065 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 2066 * auto-negotiation is disabled, then software will have to manually 2067 * configure the two flow control enable bits in the CTRL register. 2068 * 2069 * The possible values of the "fc" parameter are: 2070 * 0: Flow control is completely disabled 2071 * 1: Rx flow control is enabled (we can receive pause frames, but 2072 * not send pause frames). 2073 * 2: Tx flow control is enabled (we can send pause frames but we do 2074 * not support receiving pause frames). 2075 * 3: Both Rx and TX flow control (symmetric) are enabled. 2076 */ 2077 switch (hw->fc) { 2078 case e1000_fc_none: 2079 /* Flow control is completely disabled by a software over-ride. */ 2080 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2081 break; 2082 case e1000_fc_rx_pause: 2083 /* RX Flow control is enabled and TX Flow control is disabled by a 2084 * software over-ride. Since there really isn't a way to advertise 2085 * that we are capable of RX Pause ONLY, we will advertise that we 2086 * support both symmetric and asymmetric RX PAUSE. Later, we will 2087 * disable the adapter's ability to send PAUSE frames. 2088 */ 2089 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2090 break; 2091 case e1000_fc_tx_pause: 2092 /* TX Flow control is enabled, and RX Flow control is disabled, by a 2093 * software over-ride. 2094 */ 2095 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2096 break; 2097 case e1000_fc_full: 2098 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 2099 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2100 break; 2101 default: 2102 DEBUGOUT("Flow control param set incorrectly\n"); 2103 return -E1000_ERR_CONFIG; 2104 break; 2105 } 2106 2107 /* Since auto-negotiation is enabled, take the link out of reset (the link 2108 * will be in reset, because we previously reset the chip). This will 2109 * restart auto-negotiation. If auto-neogtiation is successful then the 2110 * link-up status bit will be set and the flow control enable bits (RFCE 2111 * and TFCE) will be set according to their negotiated value. 2112 */ 2113 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2114 2115 E1000_WRITE_REG(hw, TXCW, txcw); 2116 E1000_WRITE_REG(hw, CTRL, ctrl); 2117 E1000_WRITE_FLUSH(hw); 2118 2119 hw->txcw = txcw; 2120 mdelay(1); 2121 2122 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2123 * indication in the Device Status Register. Time-out if a link isn't 2124 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2125 * less than 500 milliseconds even if the other end is doing it in SW). 2126 */ 2127 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2128 DEBUGOUT("Looking for Link\n"); 2129 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2130 mdelay(10); 2131 status = E1000_READ_REG(hw, STATUS); 2132 if (status & E1000_STATUS_LU) 2133 break; 2134 } 2135 if (i == (LINK_UP_TIMEOUT / 10)) { 2136 /* AutoNeg failed to achieve a link, so we'll call 2137 * e1000_check_for_link. This routine will force the link up if we 2138 * detect a signal. This will allow us to communicate with 2139 * non-autonegotiating link partners. 2140 */ 2141 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2142 hw->autoneg_failed = 1; 2143 ret_val = e1000_check_for_link(hw); 2144 if (ret_val < 0) { 2145 DEBUGOUT("Error while checking for link\n"); 2146 return ret_val; 2147 } 2148 hw->autoneg_failed = 0; 2149 } else { 2150 hw->autoneg_failed = 0; 2151 DEBUGOUT("Valid Link Found\n"); 2152 } 2153 } else { 2154 DEBUGOUT("No Signal Detected\n"); 2155 return -E1000_ERR_NOLINK; 2156 } 2157 return 0; 2158 } 2159 2160 /****************************************************************************** 2161 * Make sure we have a valid PHY and change PHY mode before link setup. 2162 * 2163 * hw - Struct containing variables accessed by shared code 2164 ******************************************************************************/ 2165 static int32_t 2166 e1000_copper_link_preconfig(struct e1000_hw *hw) 2167 { 2168 uint32_t ctrl; 2169 int32_t ret_val; 2170 uint16_t phy_data; 2171 2172 DEBUGFUNC(); 2173 2174 ctrl = E1000_READ_REG(hw, CTRL); 2175 /* With 82543, we need to force speed and duplex on the MAC equal to what 2176 * the PHY speed and duplex configuration is. In addition, we need to 2177 * perform a hardware reset on the PHY to take it out of reset. 2178 */ 2179 if (hw->mac_type > e1000_82543) { 2180 ctrl |= E1000_CTRL_SLU; 2181 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2182 E1000_WRITE_REG(hw, CTRL, ctrl); 2183 } else { 2184 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2185 | E1000_CTRL_SLU); 2186 E1000_WRITE_REG(hw, CTRL, ctrl); 2187 ret_val = e1000_phy_hw_reset(hw); 2188 if (ret_val) 2189 return ret_val; 2190 } 2191 2192 /* Make sure we have a valid PHY */ 2193 ret_val = e1000_detect_gig_phy(hw); 2194 if (ret_val) { 2195 DEBUGOUT("Error, did not detect valid phy.\n"); 2196 return ret_val; 2197 } 2198 DEBUGOUT("Phy ID = %x\n", hw->phy_id); 2199 2200 /* Set PHY to class A mode (if necessary) */ 2201 ret_val = e1000_set_phy_mode(hw); 2202 if (ret_val) 2203 return ret_val; 2204 if ((hw->mac_type == e1000_82545_rev_3) || 2205 (hw->mac_type == e1000_82546_rev_3)) { 2206 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2207 &phy_data); 2208 phy_data |= 0x00000008; 2209 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2210 phy_data); 2211 } 2212 2213 if (hw->mac_type <= e1000_82543 || 2214 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2215 hw->mac_type == e1000_82541_rev_2 2216 || hw->mac_type == e1000_82547_rev_2) 2217 hw->phy_reset_disable = false; 2218 2219 return E1000_SUCCESS; 2220 } 2221 2222 /***************************************************************************** 2223 * 2224 * This function sets the lplu state according to the active flag. When 2225 * activating lplu this function also disables smart speed and vise versa. 2226 * lplu will not be activated unless the device autonegotiation advertisment 2227 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2228 * hw: Struct containing variables accessed by shared code 2229 * active - true to enable lplu false to disable lplu. 2230 * 2231 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2232 * E1000_SUCCESS at any other case. 2233 * 2234 ****************************************************************************/ 2235 2236 static int32_t 2237 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2238 { 2239 uint32_t phy_ctrl = 0; 2240 int32_t ret_val; 2241 uint16_t phy_data; 2242 DEBUGFUNC(); 2243 2244 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2245 && hw->phy_type != e1000_phy_igp_3) 2246 return E1000_SUCCESS; 2247 2248 /* During driver activity LPLU should not be used or it will attain link 2249 * from the lowest speeds starting from 10Mbps. The capability is used 2250 * for Dx transitions and states */ 2251 if (hw->mac_type == e1000_82541_rev_2 2252 || hw->mac_type == e1000_82547_rev_2) { 2253 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2254 &phy_data); 2255 if (ret_val) 2256 return ret_val; 2257 } else if (hw->mac_type == e1000_ich8lan) { 2258 /* MAC writes into PHY register based on the state transition 2259 * and start auto-negotiation. SW driver can overwrite the 2260 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2261 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2262 } else { 2263 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2264 &phy_data); 2265 if (ret_val) 2266 return ret_val; 2267 } 2268 2269 if (!active) { 2270 if (hw->mac_type == e1000_82541_rev_2 || 2271 hw->mac_type == e1000_82547_rev_2) { 2272 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2273 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2274 phy_data); 2275 if (ret_val) 2276 return ret_val; 2277 } else { 2278 if (hw->mac_type == e1000_ich8lan) { 2279 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2280 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2281 } else { 2282 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2283 ret_val = e1000_write_phy_reg(hw, 2284 IGP02E1000_PHY_POWER_MGMT, phy_data); 2285 if (ret_val) 2286 return ret_val; 2287 } 2288 } 2289 2290 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2291 * Dx states where the power conservation is most important. During 2292 * driver activity we should enable SmartSpeed, so performance is 2293 * maintained. */ 2294 if (hw->smart_speed == e1000_smart_speed_on) { 2295 ret_val = e1000_read_phy_reg(hw, 2296 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2297 if (ret_val) 2298 return ret_val; 2299 2300 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2301 ret_val = e1000_write_phy_reg(hw, 2302 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2303 if (ret_val) 2304 return ret_val; 2305 } else if (hw->smart_speed == e1000_smart_speed_off) { 2306 ret_val = e1000_read_phy_reg(hw, 2307 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2308 if (ret_val) 2309 return ret_val; 2310 2311 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2312 ret_val = e1000_write_phy_reg(hw, 2313 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2314 if (ret_val) 2315 return ret_val; 2316 } 2317 2318 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2319 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2320 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2321 2322 if (hw->mac_type == e1000_82541_rev_2 || 2323 hw->mac_type == e1000_82547_rev_2) { 2324 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2325 ret_val = e1000_write_phy_reg(hw, 2326 IGP01E1000_GMII_FIFO, phy_data); 2327 if (ret_val) 2328 return ret_val; 2329 } else { 2330 if (hw->mac_type == e1000_ich8lan) { 2331 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2332 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2333 } else { 2334 phy_data |= IGP02E1000_PM_D3_LPLU; 2335 ret_val = e1000_write_phy_reg(hw, 2336 IGP02E1000_PHY_POWER_MGMT, phy_data); 2337 if (ret_val) 2338 return ret_val; 2339 } 2340 } 2341 2342 /* When LPLU is enabled we should disable SmartSpeed */ 2343 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2344 &phy_data); 2345 if (ret_val) 2346 return ret_val; 2347 2348 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2349 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2350 phy_data); 2351 if (ret_val) 2352 return ret_val; 2353 } 2354 return E1000_SUCCESS; 2355 } 2356 2357 /***************************************************************************** 2358 * 2359 * This function sets the lplu d0 state according to the active flag. When 2360 * activating lplu this function also disables smart speed and vise versa. 2361 * lplu will not be activated unless the device autonegotiation advertisment 2362 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2363 * hw: Struct containing variables accessed by shared code 2364 * active - true to enable lplu false to disable lplu. 2365 * 2366 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2367 * E1000_SUCCESS at any other case. 2368 * 2369 ****************************************************************************/ 2370 2371 static int32_t 2372 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2373 { 2374 uint32_t phy_ctrl = 0; 2375 int32_t ret_val; 2376 uint16_t phy_data; 2377 DEBUGFUNC(); 2378 2379 if (hw->mac_type <= e1000_82547_rev_2) 2380 return E1000_SUCCESS; 2381 2382 if (hw->mac_type == e1000_ich8lan) { 2383 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2384 } else if (hw->mac_type == e1000_igb) { 2385 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2386 } else { 2387 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2388 &phy_data); 2389 if (ret_val) 2390 return ret_val; 2391 } 2392 2393 if (!active) { 2394 if (hw->mac_type == e1000_ich8lan) { 2395 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2396 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2397 } else if (hw->mac_type == e1000_igb) { 2398 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2399 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2400 } else { 2401 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2402 ret_val = e1000_write_phy_reg(hw, 2403 IGP02E1000_PHY_POWER_MGMT, phy_data); 2404 if (ret_val) 2405 return ret_val; 2406 } 2407 2408 if (hw->mac_type == e1000_igb) 2409 return E1000_SUCCESS; 2410 2411 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2412 * Dx states where the power conservation is most important. During 2413 * driver activity we should enable SmartSpeed, so performance is 2414 * maintained. */ 2415 if (hw->smart_speed == e1000_smart_speed_on) { 2416 ret_val = e1000_read_phy_reg(hw, 2417 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2418 if (ret_val) 2419 return ret_val; 2420 2421 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2422 ret_val = e1000_write_phy_reg(hw, 2423 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2424 if (ret_val) 2425 return ret_val; 2426 } else if (hw->smart_speed == e1000_smart_speed_off) { 2427 ret_val = e1000_read_phy_reg(hw, 2428 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2429 if (ret_val) 2430 return ret_val; 2431 2432 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2433 ret_val = e1000_write_phy_reg(hw, 2434 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2435 if (ret_val) 2436 return ret_val; 2437 } 2438 2439 2440 } else { 2441 2442 if (hw->mac_type == e1000_ich8lan) { 2443 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2444 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2445 } else if (hw->mac_type == e1000_igb) { 2446 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2447 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2448 } else { 2449 phy_data |= IGP02E1000_PM_D0_LPLU; 2450 ret_val = e1000_write_phy_reg(hw, 2451 IGP02E1000_PHY_POWER_MGMT, phy_data); 2452 if (ret_val) 2453 return ret_val; 2454 } 2455 2456 if (hw->mac_type == e1000_igb) 2457 return E1000_SUCCESS; 2458 2459 /* When LPLU is enabled we should disable SmartSpeed */ 2460 ret_val = e1000_read_phy_reg(hw, 2461 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2462 if (ret_val) 2463 return ret_val; 2464 2465 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2466 ret_val = e1000_write_phy_reg(hw, 2467 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2468 if (ret_val) 2469 return ret_val; 2470 2471 } 2472 return E1000_SUCCESS; 2473 } 2474 2475 /******************************************************************** 2476 * Copper link setup for e1000_phy_igp series. 2477 * 2478 * hw - Struct containing variables accessed by shared code 2479 *********************************************************************/ 2480 static int32_t 2481 e1000_copper_link_igp_setup(struct e1000_hw *hw) 2482 { 2483 uint32_t led_ctrl; 2484 int32_t ret_val; 2485 uint16_t phy_data; 2486 2487 DEBUGFUNC(); 2488 2489 if (hw->phy_reset_disable) 2490 return E1000_SUCCESS; 2491 2492 ret_val = e1000_phy_reset(hw); 2493 if (ret_val) { 2494 DEBUGOUT("Error Resetting the PHY\n"); 2495 return ret_val; 2496 } 2497 2498 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2499 mdelay(15); 2500 if (hw->mac_type != e1000_ich8lan) { 2501 /* Configure activity LED after PHY reset */ 2502 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2503 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2504 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2505 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2506 } 2507 2508 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2509 if (hw->phy_type == e1000_phy_igp) { 2510 /* disable lplu d3 during driver init */ 2511 ret_val = e1000_set_d3_lplu_state(hw, false); 2512 if (ret_val) { 2513 DEBUGOUT("Error Disabling LPLU D3\n"); 2514 return ret_val; 2515 } 2516 } 2517 2518 /* disable lplu d0 during driver init */ 2519 ret_val = e1000_set_d0_lplu_state(hw, false); 2520 if (ret_val) { 2521 DEBUGOUT("Error Disabling LPLU D0\n"); 2522 return ret_val; 2523 } 2524 /* Configure mdi-mdix settings */ 2525 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2526 if (ret_val) 2527 return ret_val; 2528 2529 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2530 hw->dsp_config_state = e1000_dsp_config_disabled; 2531 /* Force MDI for earlier revs of the IGP PHY */ 2532 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2533 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2534 hw->mdix = 1; 2535 2536 } else { 2537 hw->dsp_config_state = e1000_dsp_config_enabled; 2538 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2539 2540 switch (hw->mdix) { 2541 case 1: 2542 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2543 break; 2544 case 2: 2545 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2546 break; 2547 case 0: 2548 default: 2549 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2550 break; 2551 } 2552 } 2553 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2554 if (ret_val) 2555 return ret_val; 2556 2557 /* set auto-master slave resolution settings */ 2558 if (hw->autoneg) { 2559 e1000_ms_type phy_ms_setting = hw->master_slave; 2560 2561 if (hw->ffe_config_state == e1000_ffe_config_active) 2562 hw->ffe_config_state = e1000_ffe_config_enabled; 2563 2564 if (hw->dsp_config_state == e1000_dsp_config_activated) 2565 hw->dsp_config_state = e1000_dsp_config_enabled; 2566 2567 /* when autonegotiation advertisment is only 1000Mbps then we 2568 * should disable SmartSpeed and enable Auto MasterSlave 2569 * resolution as hardware default. */ 2570 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2571 /* Disable SmartSpeed */ 2572 ret_val = e1000_read_phy_reg(hw, 2573 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2574 if (ret_val) 2575 return ret_val; 2576 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2577 ret_val = e1000_write_phy_reg(hw, 2578 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2579 if (ret_val) 2580 return ret_val; 2581 /* Set auto Master/Slave resolution process */ 2582 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2583 &phy_data); 2584 if (ret_val) 2585 return ret_val; 2586 phy_data &= ~CR_1000T_MS_ENABLE; 2587 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2588 phy_data); 2589 if (ret_val) 2590 return ret_val; 2591 } 2592 2593 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2594 if (ret_val) 2595 return ret_val; 2596 2597 /* load defaults for future use */ 2598 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2599 ((phy_data & CR_1000T_MS_VALUE) ? 2600 e1000_ms_force_master : 2601 e1000_ms_force_slave) : 2602 e1000_ms_auto; 2603 2604 switch (phy_ms_setting) { 2605 case e1000_ms_force_master: 2606 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2607 break; 2608 case e1000_ms_force_slave: 2609 phy_data |= CR_1000T_MS_ENABLE; 2610 phy_data &= ~(CR_1000T_MS_VALUE); 2611 break; 2612 case e1000_ms_auto: 2613 phy_data &= ~CR_1000T_MS_ENABLE; 2614 default: 2615 break; 2616 } 2617 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2618 if (ret_val) 2619 return ret_val; 2620 } 2621 2622 return E1000_SUCCESS; 2623 } 2624 2625 /***************************************************************************** 2626 * This function checks the mode of the firmware. 2627 * 2628 * returns - true when the mode is IAMT or false. 2629 ****************************************************************************/ 2630 bool 2631 e1000_check_mng_mode(struct e1000_hw *hw) 2632 { 2633 uint32_t fwsm; 2634 DEBUGFUNC(); 2635 2636 fwsm = E1000_READ_REG(hw, FWSM); 2637 2638 if (hw->mac_type == e1000_ich8lan) { 2639 if ((fwsm & E1000_FWSM_MODE_MASK) == 2640 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2641 return true; 2642 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2643 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2644 return true; 2645 2646 return false; 2647 } 2648 2649 static int32_t 2650 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2651 { 2652 uint16_t swfw = E1000_SWFW_PHY0_SM; 2653 uint32_t reg_val; 2654 DEBUGFUNC(); 2655 2656 if (e1000_is_second_port(hw)) 2657 swfw = E1000_SWFW_PHY1_SM; 2658 2659 if (e1000_swfw_sync_acquire(hw, swfw)) 2660 return -E1000_ERR_SWFW_SYNC; 2661 2662 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2663 & E1000_KUMCTRLSTA_OFFSET) | data; 2664 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2665 udelay(2); 2666 2667 return E1000_SUCCESS; 2668 } 2669 2670 static int32_t 2671 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2672 { 2673 uint16_t swfw = E1000_SWFW_PHY0_SM; 2674 uint32_t reg_val; 2675 DEBUGFUNC(); 2676 2677 if (e1000_is_second_port(hw)) 2678 swfw = E1000_SWFW_PHY1_SM; 2679 2680 if (e1000_swfw_sync_acquire(hw, swfw)) { 2681 debug("%s[%i]\n", __func__, __LINE__); 2682 return -E1000_ERR_SWFW_SYNC; 2683 } 2684 2685 /* Write register address */ 2686 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2687 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2688 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2689 udelay(2); 2690 2691 /* Read the data returned */ 2692 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2693 *data = (uint16_t)reg_val; 2694 2695 return E1000_SUCCESS; 2696 } 2697 2698 /******************************************************************** 2699 * Copper link setup for e1000_phy_gg82563 series. 2700 * 2701 * hw - Struct containing variables accessed by shared code 2702 *********************************************************************/ 2703 static int32_t 2704 e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2705 { 2706 int32_t ret_val; 2707 uint16_t phy_data; 2708 uint32_t reg_data; 2709 2710 DEBUGFUNC(); 2711 2712 if (!hw->phy_reset_disable) { 2713 /* Enable CRS on TX for half-duplex operation. */ 2714 ret_val = e1000_read_phy_reg(hw, 2715 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2716 if (ret_val) 2717 return ret_val; 2718 2719 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2720 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2721 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2722 2723 ret_val = e1000_write_phy_reg(hw, 2724 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2725 if (ret_val) 2726 return ret_val; 2727 2728 /* Options: 2729 * MDI/MDI-X = 0 (default) 2730 * 0 - Auto for all speeds 2731 * 1 - MDI mode 2732 * 2 - MDI-X mode 2733 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2734 */ 2735 ret_val = e1000_read_phy_reg(hw, 2736 GG82563_PHY_SPEC_CTRL, &phy_data); 2737 if (ret_val) 2738 return ret_val; 2739 2740 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2741 2742 switch (hw->mdix) { 2743 case 1: 2744 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2745 break; 2746 case 2: 2747 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2748 break; 2749 case 0: 2750 default: 2751 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2752 break; 2753 } 2754 2755 /* Options: 2756 * disable_polarity_correction = 0 (default) 2757 * Automatic Correction for Reversed Cable Polarity 2758 * 0 - Disabled 2759 * 1 - Enabled 2760 */ 2761 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2762 ret_val = e1000_write_phy_reg(hw, 2763 GG82563_PHY_SPEC_CTRL, phy_data); 2764 2765 if (ret_val) 2766 return ret_val; 2767 2768 /* SW Reset the PHY so all changes take effect */ 2769 ret_val = e1000_phy_reset(hw); 2770 if (ret_val) { 2771 DEBUGOUT("Error Resetting the PHY\n"); 2772 return ret_val; 2773 } 2774 } /* phy_reset_disable */ 2775 2776 if (hw->mac_type == e1000_80003es2lan) { 2777 /* Bypass RX and TX FIFO's */ 2778 ret_val = e1000_write_kmrn_reg(hw, 2779 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2780 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2781 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2782 if (ret_val) 2783 return ret_val; 2784 2785 ret_val = e1000_read_phy_reg(hw, 2786 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2787 if (ret_val) 2788 return ret_val; 2789 2790 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2791 ret_val = e1000_write_phy_reg(hw, 2792 GG82563_PHY_SPEC_CTRL_2, phy_data); 2793 2794 if (ret_val) 2795 return ret_val; 2796 2797 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2798 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2799 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2800 2801 ret_val = e1000_read_phy_reg(hw, 2802 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2803 if (ret_val) 2804 return ret_val; 2805 2806 /* Do not init these registers when the HW is in IAMT mode, since the 2807 * firmware will have already initialized them. We only initialize 2808 * them if the HW is not in IAMT mode. 2809 */ 2810 if (e1000_check_mng_mode(hw) == false) { 2811 /* Enable Electrical Idle on the PHY */ 2812 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2813 ret_val = e1000_write_phy_reg(hw, 2814 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2815 if (ret_val) 2816 return ret_val; 2817 2818 ret_val = e1000_read_phy_reg(hw, 2819 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2820 if (ret_val) 2821 return ret_val; 2822 2823 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2824 ret_val = e1000_write_phy_reg(hw, 2825 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2826 2827 if (ret_val) 2828 return ret_val; 2829 } 2830 2831 /* Workaround: Disable padding in Kumeran interface in the MAC 2832 * and in the PHY to avoid CRC errors. 2833 */ 2834 ret_val = e1000_read_phy_reg(hw, 2835 GG82563_PHY_INBAND_CTRL, &phy_data); 2836 if (ret_val) 2837 return ret_val; 2838 phy_data |= GG82563_ICR_DIS_PADDING; 2839 ret_val = e1000_write_phy_reg(hw, 2840 GG82563_PHY_INBAND_CTRL, phy_data); 2841 if (ret_val) 2842 return ret_val; 2843 } 2844 return E1000_SUCCESS; 2845 } 2846 2847 /******************************************************************** 2848 * Copper link setup for e1000_phy_m88 series. 2849 * 2850 * hw - Struct containing variables accessed by shared code 2851 *********************************************************************/ 2852 static int32_t 2853 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 2854 { 2855 int32_t ret_val; 2856 uint16_t phy_data; 2857 2858 DEBUGFUNC(); 2859 2860 if (hw->phy_reset_disable) 2861 return E1000_SUCCESS; 2862 2863 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2864 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2865 if (ret_val) 2866 return ret_val; 2867 2868 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2869 2870 /* Options: 2871 * MDI/MDI-X = 0 (default) 2872 * 0 - Auto for all speeds 2873 * 1 - MDI mode 2874 * 2 - MDI-X mode 2875 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2876 */ 2877 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2878 2879 switch (hw->mdix) { 2880 case 1: 2881 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2882 break; 2883 case 2: 2884 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2885 break; 2886 case 3: 2887 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2888 break; 2889 case 0: 2890 default: 2891 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2892 break; 2893 } 2894 2895 /* Options: 2896 * disable_polarity_correction = 0 (default) 2897 * Automatic Correction for Reversed Cable Polarity 2898 * 0 - Disabled 2899 * 1 - Enabled 2900 */ 2901 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2902 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2903 if (ret_val) 2904 return ret_val; 2905 2906 if (hw->phy_revision < M88E1011_I_REV_4) { 2907 /* Force TX_CLK in the Extended PHY Specific Control Register 2908 * to 25MHz clock. 2909 */ 2910 ret_val = e1000_read_phy_reg(hw, 2911 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2912 if (ret_val) 2913 return ret_val; 2914 2915 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2916 2917 if ((hw->phy_revision == E1000_REVISION_2) && 2918 (hw->phy_id == M88E1111_I_PHY_ID)) { 2919 /* Vidalia Phy, set the downshift counter to 5x */ 2920 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2921 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2922 ret_val = e1000_write_phy_reg(hw, 2923 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2924 if (ret_val) 2925 return ret_val; 2926 } else { 2927 /* Configure Master and Slave downshift values */ 2928 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 2929 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2930 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 2931 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2932 ret_val = e1000_write_phy_reg(hw, 2933 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2934 if (ret_val) 2935 return ret_val; 2936 } 2937 } 2938 2939 /* SW Reset the PHY so all changes take effect */ 2940 ret_val = e1000_phy_reset(hw); 2941 if (ret_val) { 2942 DEBUGOUT("Error Resetting the PHY\n"); 2943 return ret_val; 2944 } 2945 2946 return E1000_SUCCESS; 2947 } 2948 2949 /******************************************************************** 2950 * Setup auto-negotiation and flow control advertisements, 2951 * and then perform auto-negotiation. 2952 * 2953 * hw - Struct containing variables accessed by shared code 2954 *********************************************************************/ 2955 static int32_t 2956 e1000_copper_link_autoneg(struct e1000_hw *hw) 2957 { 2958 int32_t ret_val; 2959 uint16_t phy_data; 2960 2961 DEBUGFUNC(); 2962 2963 /* Perform some bounds checking on the hw->autoneg_advertised 2964 * parameter. If this variable is zero, then set it to the default. 2965 */ 2966 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2967 2968 /* If autoneg_advertised is zero, we assume it was not defaulted 2969 * by the calling code so we set to advertise full capability. 2970 */ 2971 if (hw->autoneg_advertised == 0) 2972 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2973 2974 /* IFE phy only supports 10/100 */ 2975 if (hw->phy_type == e1000_phy_ife) 2976 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2977 2978 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2979 ret_val = e1000_phy_setup_autoneg(hw); 2980 if (ret_val) { 2981 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2982 return ret_val; 2983 } 2984 DEBUGOUT("Restarting Auto-Neg\n"); 2985 2986 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 2987 * the Auto Neg Restart bit in the PHY control register. 2988 */ 2989 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2990 if (ret_val) 2991 return ret_val; 2992 2993 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2994 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2995 if (ret_val) 2996 return ret_val; 2997 2998 /* Does the user want to wait for Auto-Neg to complete here, or 2999 * check at a later time (for example, callback routine). 3000 */ 3001 /* If we do not wait for autonegtation to complete I 3002 * do not see a valid link status. 3003 * wait_autoneg_complete = 1 . 3004 */ 3005 if (hw->wait_autoneg_complete) { 3006 ret_val = e1000_wait_autoneg(hw); 3007 if (ret_val) { 3008 DEBUGOUT("Error while waiting for autoneg" 3009 "to complete\n"); 3010 return ret_val; 3011 } 3012 } 3013 3014 hw->get_link_status = true; 3015 3016 return E1000_SUCCESS; 3017 } 3018 3019 /****************************************************************************** 3020 * Config the MAC and the PHY after link is up. 3021 * 1) Set up the MAC to the current PHY speed/duplex 3022 * if we are on 82543. If we 3023 * are on newer silicon, we only need to configure 3024 * collision distance in the Transmit Control Register. 3025 * 2) Set up flow control on the MAC to that established with 3026 * the link partner. 3027 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3028 * 3029 * hw - Struct containing variables accessed by shared code 3030 ******************************************************************************/ 3031 static int32_t 3032 e1000_copper_link_postconfig(struct e1000_hw *hw) 3033 { 3034 int32_t ret_val; 3035 DEBUGFUNC(); 3036 3037 if (hw->mac_type >= e1000_82544) { 3038 e1000_config_collision_dist(hw); 3039 } else { 3040 ret_val = e1000_config_mac_to_phy(hw); 3041 if (ret_val) { 3042 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3043 return ret_val; 3044 } 3045 } 3046 ret_val = e1000_config_fc_after_link_up(hw); 3047 if (ret_val) { 3048 DEBUGOUT("Error Configuring Flow Control\n"); 3049 return ret_val; 3050 } 3051 return E1000_SUCCESS; 3052 } 3053 3054 /****************************************************************************** 3055 * Detects which PHY is present and setup the speed and duplex 3056 * 3057 * hw - Struct containing variables accessed by shared code 3058 ******************************************************************************/ 3059 static int 3060 e1000_setup_copper_link(struct e1000_hw *hw) 3061 { 3062 int32_t ret_val; 3063 uint16_t i; 3064 uint16_t phy_data; 3065 uint16_t reg_data; 3066 3067 DEBUGFUNC(); 3068 3069 switch (hw->mac_type) { 3070 case e1000_80003es2lan: 3071 case e1000_ich8lan: 3072 /* Set the mac to wait the maximum time between each 3073 * iteration and increase the max iterations when 3074 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3075 ret_val = e1000_write_kmrn_reg(hw, 3076 GG82563_REG(0x34, 4), 0xFFFF); 3077 if (ret_val) 3078 return ret_val; 3079 ret_val = e1000_read_kmrn_reg(hw, 3080 GG82563_REG(0x34, 9), ®_data); 3081 if (ret_val) 3082 return ret_val; 3083 reg_data |= 0x3F; 3084 ret_val = e1000_write_kmrn_reg(hw, 3085 GG82563_REG(0x34, 9), reg_data); 3086 if (ret_val) 3087 return ret_val; 3088 default: 3089 break; 3090 } 3091 3092 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3093 ret_val = e1000_copper_link_preconfig(hw); 3094 if (ret_val) 3095 return ret_val; 3096 switch (hw->mac_type) { 3097 case e1000_80003es2lan: 3098 /* Kumeran registers are written-only */ 3099 reg_data = 3100 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3101 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3102 ret_val = e1000_write_kmrn_reg(hw, 3103 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3104 if (ret_val) 3105 return ret_val; 3106 break; 3107 default: 3108 break; 3109 } 3110 3111 if (hw->phy_type == e1000_phy_igp || 3112 hw->phy_type == e1000_phy_igp_3 || 3113 hw->phy_type == e1000_phy_igp_2) { 3114 ret_val = e1000_copper_link_igp_setup(hw); 3115 if (ret_val) 3116 return ret_val; 3117 } else if (hw->phy_type == e1000_phy_m88 || 3118 hw->phy_type == e1000_phy_igb) { 3119 ret_val = e1000_copper_link_mgp_setup(hw); 3120 if (ret_val) 3121 return ret_val; 3122 } else if (hw->phy_type == e1000_phy_gg82563) { 3123 ret_val = e1000_copper_link_ggp_setup(hw); 3124 if (ret_val) 3125 return ret_val; 3126 } 3127 3128 /* always auto */ 3129 /* Setup autoneg and flow control advertisement 3130 * and perform autonegotiation */ 3131 ret_val = e1000_copper_link_autoneg(hw); 3132 if (ret_val) 3133 return ret_val; 3134 3135 /* Check link status. Wait up to 100 microseconds for link to become 3136 * valid. 3137 */ 3138 for (i = 0; i < 10; i++) { 3139 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3140 if (ret_val) 3141 return ret_val; 3142 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3143 if (ret_val) 3144 return ret_val; 3145 3146 if (phy_data & MII_SR_LINK_STATUS) { 3147 /* Config the MAC and PHY after link is up */ 3148 ret_val = e1000_copper_link_postconfig(hw); 3149 if (ret_val) 3150 return ret_val; 3151 3152 DEBUGOUT("Valid link established!!!\n"); 3153 return E1000_SUCCESS; 3154 } 3155 udelay(10); 3156 } 3157 3158 DEBUGOUT("Unable to establish link!!!\n"); 3159 return E1000_SUCCESS; 3160 } 3161 3162 /****************************************************************************** 3163 * Configures PHY autoneg and flow control advertisement settings 3164 * 3165 * hw - Struct containing variables accessed by shared code 3166 ******************************************************************************/ 3167 int32_t 3168 e1000_phy_setup_autoneg(struct e1000_hw *hw) 3169 { 3170 int32_t ret_val; 3171 uint16_t mii_autoneg_adv_reg; 3172 uint16_t mii_1000t_ctrl_reg; 3173 3174 DEBUGFUNC(); 3175 3176 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3177 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3178 if (ret_val) 3179 return ret_val; 3180 3181 if (hw->phy_type != e1000_phy_ife) { 3182 /* Read the MII 1000Base-T Control Register (Address 9). */ 3183 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3184 &mii_1000t_ctrl_reg); 3185 if (ret_val) 3186 return ret_val; 3187 } else 3188 mii_1000t_ctrl_reg = 0; 3189 3190 /* Need to parse both autoneg_advertised and fc and set up 3191 * the appropriate PHY registers. First we will parse for 3192 * autoneg_advertised software override. Since we can advertise 3193 * a plethora of combinations, we need to check each bit 3194 * individually. 3195 */ 3196 3197 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3198 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3199 * the 1000Base-T Control Register (Address 9). 3200 */ 3201 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3202 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3203 3204 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3205 3206 /* Do we want to advertise 10 Mb Half Duplex? */ 3207 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3208 DEBUGOUT("Advertise 10mb Half duplex\n"); 3209 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3210 } 3211 3212 /* Do we want to advertise 10 Mb Full Duplex? */ 3213 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3214 DEBUGOUT("Advertise 10mb Full duplex\n"); 3215 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3216 } 3217 3218 /* Do we want to advertise 100 Mb Half Duplex? */ 3219 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3220 DEBUGOUT("Advertise 100mb Half duplex\n"); 3221 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3222 } 3223 3224 /* Do we want to advertise 100 Mb Full Duplex? */ 3225 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3226 DEBUGOUT("Advertise 100mb Full duplex\n"); 3227 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3228 } 3229 3230 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3231 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3232 DEBUGOUT 3233 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3234 } 3235 3236 /* Do we want to advertise 1000 Mb Full Duplex? */ 3237 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3238 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3239 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3240 } 3241 3242 /* Check for a software override of the flow control settings, and 3243 * setup the PHY advertisement registers accordingly. If 3244 * auto-negotiation is enabled, then software will have to set the 3245 * "PAUSE" bits to the correct value in the Auto-Negotiation 3246 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3247 * 3248 * The possible values of the "fc" parameter are: 3249 * 0: Flow control is completely disabled 3250 * 1: Rx flow control is enabled (we can receive pause frames 3251 * but not send pause frames). 3252 * 2: Tx flow control is enabled (we can send pause frames 3253 * but we do not support receiving pause frames). 3254 * 3: Both Rx and TX flow control (symmetric) are enabled. 3255 * other: No software override. The flow control configuration 3256 * in the EEPROM is used. 3257 */ 3258 switch (hw->fc) { 3259 case e1000_fc_none: /* 0 */ 3260 /* Flow control (RX & TX) is completely disabled by a 3261 * software over-ride. 3262 */ 3263 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3264 break; 3265 case e1000_fc_rx_pause: /* 1 */ 3266 /* RX Flow control is enabled, and TX Flow control is 3267 * disabled, by a software over-ride. 3268 */ 3269 /* Since there really isn't a way to advertise that we are 3270 * capable of RX Pause ONLY, we will advertise that we 3271 * support both symmetric and asymmetric RX PAUSE. Later 3272 * (in e1000_config_fc_after_link_up) we will disable the 3273 *hw's ability to send PAUSE frames. 3274 */ 3275 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3276 break; 3277 case e1000_fc_tx_pause: /* 2 */ 3278 /* TX Flow control is enabled, and RX Flow control is 3279 * disabled, by a software over-ride. 3280 */ 3281 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3282 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3283 break; 3284 case e1000_fc_full: /* 3 */ 3285 /* Flow control (both RX and TX) is enabled by a software 3286 * over-ride. 3287 */ 3288 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3289 break; 3290 default: 3291 DEBUGOUT("Flow control param set incorrectly\n"); 3292 return -E1000_ERR_CONFIG; 3293 } 3294 3295 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3296 if (ret_val) 3297 return ret_val; 3298 3299 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3300 3301 if (hw->phy_type != e1000_phy_ife) { 3302 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3303 mii_1000t_ctrl_reg); 3304 if (ret_val) 3305 return ret_val; 3306 } 3307 3308 return E1000_SUCCESS; 3309 } 3310 3311 /****************************************************************************** 3312 * Sets the collision distance in the Transmit Control register 3313 * 3314 * hw - Struct containing variables accessed by shared code 3315 * 3316 * Link should have been established previously. Reads the speed and duplex 3317 * information from the Device Status register. 3318 ******************************************************************************/ 3319 static void 3320 e1000_config_collision_dist(struct e1000_hw *hw) 3321 { 3322 uint32_t tctl, coll_dist; 3323 3324 DEBUGFUNC(); 3325 3326 if (hw->mac_type < e1000_82543) 3327 coll_dist = E1000_COLLISION_DISTANCE_82542; 3328 else 3329 coll_dist = E1000_COLLISION_DISTANCE; 3330 3331 tctl = E1000_READ_REG(hw, TCTL); 3332 3333 tctl &= ~E1000_TCTL_COLD; 3334 tctl |= coll_dist << E1000_COLD_SHIFT; 3335 3336 E1000_WRITE_REG(hw, TCTL, tctl); 3337 E1000_WRITE_FLUSH(hw); 3338 } 3339 3340 /****************************************************************************** 3341 * Sets MAC speed and duplex settings to reflect the those in the PHY 3342 * 3343 * hw - Struct containing variables accessed by shared code 3344 * mii_reg - data to write to the MII control register 3345 * 3346 * The contents of the PHY register containing the needed information need to 3347 * be passed in. 3348 ******************************************************************************/ 3349 static int 3350 e1000_config_mac_to_phy(struct e1000_hw *hw) 3351 { 3352 uint32_t ctrl; 3353 uint16_t phy_data; 3354 3355 DEBUGFUNC(); 3356 3357 /* Read the Device Control Register and set the bits to Force Speed 3358 * and Duplex. 3359 */ 3360 ctrl = E1000_READ_REG(hw, CTRL); 3361 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3362 ctrl &= ~(E1000_CTRL_ILOS); 3363 ctrl |= (E1000_CTRL_SPD_SEL); 3364 3365 /* Set up duplex in the Device Control and Transmit Control 3366 * registers depending on negotiated values. 3367 */ 3368 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3369 DEBUGOUT("PHY Read Error\n"); 3370 return -E1000_ERR_PHY; 3371 } 3372 if (phy_data & M88E1000_PSSR_DPLX) 3373 ctrl |= E1000_CTRL_FD; 3374 else 3375 ctrl &= ~E1000_CTRL_FD; 3376 3377 e1000_config_collision_dist(hw); 3378 3379 /* Set up speed in the Device Control register depending on 3380 * negotiated values. 3381 */ 3382 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3383 ctrl |= E1000_CTRL_SPD_1000; 3384 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3385 ctrl |= E1000_CTRL_SPD_100; 3386 /* Write the configured values back to the Device Control Reg. */ 3387 E1000_WRITE_REG(hw, CTRL, ctrl); 3388 return 0; 3389 } 3390 3391 /****************************************************************************** 3392 * Forces the MAC's flow control settings. 3393 * 3394 * hw - Struct containing variables accessed by shared code 3395 * 3396 * Sets the TFCE and RFCE bits in the device control register to reflect 3397 * the adapter settings. TFCE and RFCE need to be explicitly set by 3398 * software when a Copper PHY is used because autonegotiation is managed 3399 * by the PHY rather than the MAC. Software must also configure these 3400 * bits when link is forced on a fiber connection. 3401 *****************************************************************************/ 3402 static int 3403 e1000_force_mac_fc(struct e1000_hw *hw) 3404 { 3405 uint32_t ctrl; 3406 3407 DEBUGFUNC(); 3408 3409 /* Get the current configuration of the Device Control Register */ 3410 ctrl = E1000_READ_REG(hw, CTRL); 3411 3412 /* Because we didn't get link via the internal auto-negotiation 3413 * mechanism (we either forced link or we got link via PHY 3414 * auto-neg), we have to manually enable/disable transmit an 3415 * receive flow control. 3416 * 3417 * The "Case" statement below enables/disable flow control 3418 * according to the "hw->fc" parameter. 3419 * 3420 * The possible values of the "fc" parameter are: 3421 * 0: Flow control is completely disabled 3422 * 1: Rx flow control is enabled (we can receive pause 3423 * frames but not send pause frames). 3424 * 2: Tx flow control is enabled (we can send pause frames 3425 * frames but we do not receive pause frames). 3426 * 3: Both Rx and TX flow control (symmetric) is enabled. 3427 * other: No other values should be possible at this point. 3428 */ 3429 3430 switch (hw->fc) { 3431 case e1000_fc_none: 3432 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3433 break; 3434 case e1000_fc_rx_pause: 3435 ctrl &= (~E1000_CTRL_TFCE); 3436 ctrl |= E1000_CTRL_RFCE; 3437 break; 3438 case e1000_fc_tx_pause: 3439 ctrl &= (~E1000_CTRL_RFCE); 3440 ctrl |= E1000_CTRL_TFCE; 3441 break; 3442 case e1000_fc_full: 3443 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3444 break; 3445 default: 3446 DEBUGOUT("Flow control param set incorrectly\n"); 3447 return -E1000_ERR_CONFIG; 3448 } 3449 3450 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3451 if (hw->mac_type == e1000_82542_rev2_0) 3452 ctrl &= (~E1000_CTRL_TFCE); 3453 3454 E1000_WRITE_REG(hw, CTRL, ctrl); 3455 return 0; 3456 } 3457 3458 /****************************************************************************** 3459 * Configures flow control settings after link is established 3460 * 3461 * hw - Struct containing variables accessed by shared code 3462 * 3463 * Should be called immediately after a valid link has been established. 3464 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3465 * and autonegotiation is enabled, the MAC flow control settings will be set 3466 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3467 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3468 *****************************************************************************/ 3469 static int32_t 3470 e1000_config_fc_after_link_up(struct e1000_hw *hw) 3471 { 3472 int32_t ret_val; 3473 uint16_t mii_status_reg; 3474 uint16_t mii_nway_adv_reg; 3475 uint16_t mii_nway_lp_ability_reg; 3476 uint16_t speed; 3477 uint16_t duplex; 3478 3479 DEBUGFUNC(); 3480 3481 /* Check for the case where we have fiber media and auto-neg failed 3482 * so we had to force link. In this case, we need to force the 3483 * configuration of the MAC to match the "fc" parameter. 3484 */ 3485 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3486 || ((hw->media_type == e1000_media_type_internal_serdes) 3487 && (hw->autoneg_failed)) 3488 || ((hw->media_type == e1000_media_type_copper) 3489 && (!hw->autoneg))) { 3490 ret_val = e1000_force_mac_fc(hw); 3491 if (ret_val < 0) { 3492 DEBUGOUT("Error forcing flow control settings\n"); 3493 return ret_val; 3494 } 3495 } 3496 3497 /* Check for the case where we have copper media and auto-neg is 3498 * enabled. In this case, we need to check and see if Auto-Neg 3499 * has completed, and if so, how the PHY and link partner has 3500 * flow control configured. 3501 */ 3502 if (hw->media_type == e1000_media_type_copper) { 3503 /* Read the MII Status Register and check to see if AutoNeg 3504 * has completed. We read this twice because this reg has 3505 * some "sticky" (latched) bits. 3506 */ 3507 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3508 DEBUGOUT("PHY Read Error\n"); 3509 return -E1000_ERR_PHY; 3510 } 3511 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3512 DEBUGOUT("PHY Read Error\n"); 3513 return -E1000_ERR_PHY; 3514 } 3515 3516 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3517 /* The AutoNeg process has completed, so we now need to 3518 * read both the Auto Negotiation Advertisement Register 3519 * (Address 4) and the Auto_Negotiation Base Page Ability 3520 * Register (Address 5) to determine how flow control was 3521 * negotiated. 3522 */ 3523 if (e1000_read_phy_reg 3524 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3525 DEBUGOUT("PHY Read Error\n"); 3526 return -E1000_ERR_PHY; 3527 } 3528 if (e1000_read_phy_reg 3529 (hw, PHY_LP_ABILITY, 3530 &mii_nway_lp_ability_reg) < 0) { 3531 DEBUGOUT("PHY Read Error\n"); 3532 return -E1000_ERR_PHY; 3533 } 3534 3535 /* Two bits in the Auto Negotiation Advertisement Register 3536 * (Address 4) and two bits in the Auto Negotiation Base 3537 * Page Ability Register (Address 5) determine flow control 3538 * for both the PHY and the link partner. The following 3539 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3540 * 1999, describes these PAUSE resolution bits and how flow 3541 * control is determined based upon these settings. 3542 * NOTE: DC = Don't Care 3543 * 3544 * LOCAL DEVICE | LINK PARTNER 3545 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3546 *-------|---------|-------|---------|-------------------- 3547 * 0 | 0 | DC | DC | e1000_fc_none 3548 * 0 | 1 | 0 | DC | e1000_fc_none 3549 * 0 | 1 | 1 | 0 | e1000_fc_none 3550 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3551 * 1 | 0 | 0 | DC | e1000_fc_none 3552 * 1 | DC | 1 | DC | e1000_fc_full 3553 * 1 | 1 | 0 | 0 | e1000_fc_none 3554 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3555 * 3556 */ 3557 /* Are both PAUSE bits set to 1? If so, this implies 3558 * Symmetric Flow Control is enabled at both ends. The 3559 * ASM_DIR bits are irrelevant per the spec. 3560 * 3561 * For Symmetric Flow Control: 3562 * 3563 * LOCAL DEVICE | LINK PARTNER 3564 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3565 *-------|---------|-------|---------|-------------------- 3566 * 1 | DC | 1 | DC | e1000_fc_full 3567 * 3568 */ 3569 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3570 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3571 /* Now we need to check if the user selected RX ONLY 3572 * of pause frames. In this case, we had to advertise 3573 * FULL flow control because we could not advertise RX 3574 * ONLY. Hence, we must now check to see if we need to 3575 * turn OFF the TRANSMISSION of PAUSE frames. 3576 */ 3577 if (hw->original_fc == e1000_fc_full) { 3578 hw->fc = e1000_fc_full; 3579 DEBUGOUT("Flow Control = FULL.\r\n"); 3580 } else { 3581 hw->fc = e1000_fc_rx_pause; 3582 DEBUGOUT 3583 ("Flow Control = RX PAUSE frames only.\r\n"); 3584 } 3585 } 3586 /* For receiving PAUSE frames ONLY. 3587 * 3588 * LOCAL DEVICE | LINK PARTNER 3589 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3590 *-------|---------|-------|---------|-------------------- 3591 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3592 * 3593 */ 3594 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3595 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3596 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3597 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3598 { 3599 hw->fc = e1000_fc_tx_pause; 3600 DEBUGOUT 3601 ("Flow Control = TX PAUSE frames only.\r\n"); 3602 } 3603 /* For transmitting PAUSE frames ONLY. 3604 * 3605 * LOCAL DEVICE | LINK PARTNER 3606 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3607 *-------|---------|-------|---------|-------------------- 3608 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3609 * 3610 */ 3611 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3612 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3613 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3614 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3615 { 3616 hw->fc = e1000_fc_rx_pause; 3617 DEBUGOUT 3618 ("Flow Control = RX PAUSE frames only.\r\n"); 3619 } 3620 /* Per the IEEE spec, at this point flow control should be 3621 * disabled. However, we want to consider that we could 3622 * be connected to a legacy switch that doesn't advertise 3623 * desired flow control, but can be forced on the link 3624 * partner. So if we advertised no flow control, that is 3625 * what we will resolve to. If we advertised some kind of 3626 * receive capability (Rx Pause Only or Full Flow Control) 3627 * and the link partner advertised none, we will configure 3628 * ourselves to enable Rx Flow Control only. We can do 3629 * this safely for two reasons: If the link partner really 3630 * didn't want flow control enabled, and we enable Rx, no 3631 * harm done since we won't be receiving any PAUSE frames 3632 * anyway. If the intent on the link partner was to have 3633 * flow control enabled, then by us enabling RX only, we 3634 * can at least receive pause frames and process them. 3635 * This is a good idea because in most cases, since we are 3636 * predominantly a server NIC, more times than not we will 3637 * be asked to delay transmission of packets than asking 3638 * our link partner to pause transmission of frames. 3639 */ 3640 else if (hw->original_fc == e1000_fc_none || 3641 hw->original_fc == e1000_fc_tx_pause) { 3642 hw->fc = e1000_fc_none; 3643 DEBUGOUT("Flow Control = NONE.\r\n"); 3644 } else { 3645 hw->fc = e1000_fc_rx_pause; 3646 DEBUGOUT 3647 ("Flow Control = RX PAUSE frames only.\r\n"); 3648 } 3649 3650 /* Now we need to do one last check... If we auto- 3651 * negotiated to HALF DUPLEX, flow control should not be 3652 * enabled per IEEE 802.3 spec. 3653 */ 3654 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3655 3656 if (duplex == HALF_DUPLEX) 3657 hw->fc = e1000_fc_none; 3658 3659 /* Now we call a subroutine to actually force the MAC 3660 * controller to use the correct flow control settings. 3661 */ 3662 ret_val = e1000_force_mac_fc(hw); 3663 if (ret_val < 0) { 3664 DEBUGOUT 3665 ("Error forcing flow control settings\n"); 3666 return ret_val; 3667 } 3668 } else { 3669 DEBUGOUT 3670 ("Copper PHY and Auto Neg has not completed.\r\n"); 3671 } 3672 } 3673 return E1000_SUCCESS; 3674 } 3675 3676 /****************************************************************************** 3677 * Checks to see if the link status of the hardware has changed. 3678 * 3679 * hw - Struct containing variables accessed by shared code 3680 * 3681 * Called by any function that needs to check the link status of the adapter. 3682 *****************************************************************************/ 3683 static int 3684 e1000_check_for_link(struct e1000_hw *hw) 3685 { 3686 uint32_t rxcw; 3687 uint32_t ctrl; 3688 uint32_t status; 3689 uint32_t rctl; 3690 uint32_t signal; 3691 int32_t ret_val; 3692 uint16_t phy_data; 3693 uint16_t lp_capability; 3694 3695 DEBUGFUNC(); 3696 3697 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3698 * set when the optics detect a signal. On older adapters, it will be 3699 * cleared when there is a signal 3700 */ 3701 ctrl = E1000_READ_REG(hw, CTRL); 3702 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3703 signal = E1000_CTRL_SWDPIN1; 3704 else 3705 signal = 0; 3706 3707 status = E1000_READ_REG(hw, STATUS); 3708 rxcw = E1000_READ_REG(hw, RXCW); 3709 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3710 3711 /* If we have a copper PHY then we only want to go out to the PHY 3712 * registers to see if Auto-Neg has completed and/or if our link 3713 * status has changed. The get_link_status flag will be set if we 3714 * receive a Link Status Change interrupt or we have Rx Sequence 3715 * Errors. 3716 */ 3717 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3718 /* First we want to see if the MII Status Register reports 3719 * link. If so, then we want to get the current speed/duplex 3720 * of the PHY. 3721 * Read the register twice since the link bit is sticky. 3722 */ 3723 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3724 DEBUGOUT("PHY Read Error\n"); 3725 return -E1000_ERR_PHY; 3726 } 3727 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3728 DEBUGOUT("PHY Read Error\n"); 3729 return -E1000_ERR_PHY; 3730 } 3731 3732 if (phy_data & MII_SR_LINK_STATUS) { 3733 hw->get_link_status = false; 3734 } else { 3735 /* No link detected */ 3736 return -E1000_ERR_NOLINK; 3737 } 3738 3739 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3740 * have Si on board that is 82544 or newer, Auto 3741 * Speed Detection takes care of MAC speed/duplex 3742 * configuration. So we only need to configure Collision 3743 * Distance in the MAC. Otherwise, we need to force 3744 * speed/duplex on the MAC to the current PHY speed/duplex 3745 * settings. 3746 */ 3747 if (hw->mac_type >= e1000_82544) 3748 e1000_config_collision_dist(hw); 3749 else { 3750 ret_val = e1000_config_mac_to_phy(hw); 3751 if (ret_val < 0) { 3752 DEBUGOUT 3753 ("Error configuring MAC to PHY settings\n"); 3754 return ret_val; 3755 } 3756 } 3757 3758 /* Configure Flow Control now that Auto-Neg has completed. First, we 3759 * need to restore the desired flow control settings because we may 3760 * have had to re-autoneg with a different link partner. 3761 */ 3762 ret_val = e1000_config_fc_after_link_up(hw); 3763 if (ret_val < 0) { 3764 DEBUGOUT("Error configuring flow control\n"); 3765 return ret_val; 3766 } 3767 3768 /* At this point we know that we are on copper and we have 3769 * auto-negotiated link. These are conditions for checking the link 3770 * parter capability register. We use the link partner capability to 3771 * determine if TBI Compatibility needs to be turned on or off. If 3772 * the link partner advertises any speed in addition to Gigabit, then 3773 * we assume that they are GMII-based, and TBI compatibility is not 3774 * needed. If no other speeds are advertised, we assume the link 3775 * partner is TBI-based, and we turn on TBI Compatibility. 3776 */ 3777 if (hw->tbi_compatibility_en) { 3778 if (e1000_read_phy_reg 3779 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3780 DEBUGOUT("PHY Read Error\n"); 3781 return -E1000_ERR_PHY; 3782 } 3783 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3784 NWAY_LPAR_10T_FD_CAPS | 3785 NWAY_LPAR_100TX_HD_CAPS | 3786 NWAY_LPAR_100TX_FD_CAPS | 3787 NWAY_LPAR_100T4_CAPS)) { 3788 /* If our link partner advertises anything in addition to 3789 * gigabit, we do not need to enable TBI compatibility. 3790 */ 3791 if (hw->tbi_compatibility_on) { 3792 /* If we previously were in the mode, turn it off. */ 3793 rctl = E1000_READ_REG(hw, RCTL); 3794 rctl &= ~E1000_RCTL_SBP; 3795 E1000_WRITE_REG(hw, RCTL, rctl); 3796 hw->tbi_compatibility_on = false; 3797 } 3798 } else { 3799 /* If TBI compatibility is was previously off, turn it on. For 3800 * compatibility with a TBI link partner, we will store bad 3801 * packets. Some frames have an additional byte on the end and 3802 * will look like CRC errors to to the hardware. 3803 */ 3804 if (!hw->tbi_compatibility_on) { 3805 hw->tbi_compatibility_on = true; 3806 rctl = E1000_READ_REG(hw, RCTL); 3807 rctl |= E1000_RCTL_SBP; 3808 E1000_WRITE_REG(hw, RCTL, rctl); 3809 } 3810 } 3811 } 3812 } 3813 /* If we don't have link (auto-negotiation failed or link partner cannot 3814 * auto-negotiate), the cable is plugged in (we have signal), and our 3815 * link partner is not trying to auto-negotiate with us (we are receiving 3816 * idles or data), we need to force link up. We also need to give 3817 * auto-negotiation time to complete, in case the cable was just plugged 3818 * in. The autoneg_failed flag does this. 3819 */ 3820 else if ((hw->media_type == e1000_media_type_fiber) && 3821 (!(status & E1000_STATUS_LU)) && 3822 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3823 (!(rxcw & E1000_RXCW_C))) { 3824 if (hw->autoneg_failed == 0) { 3825 hw->autoneg_failed = 1; 3826 return 0; 3827 } 3828 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3829 3830 /* Disable auto-negotiation in the TXCW register */ 3831 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3832 3833 /* Force link-up and also force full-duplex. */ 3834 ctrl = E1000_READ_REG(hw, CTRL); 3835 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3836 E1000_WRITE_REG(hw, CTRL, ctrl); 3837 3838 /* Configure Flow Control after forcing link up. */ 3839 ret_val = e1000_config_fc_after_link_up(hw); 3840 if (ret_val < 0) { 3841 DEBUGOUT("Error configuring flow control\n"); 3842 return ret_val; 3843 } 3844 } 3845 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3846 * auto-negotiation in the TXCW register and disable forced link in the 3847 * Device Control register in an attempt to auto-negotiate with our link 3848 * partner. 3849 */ 3850 else if ((hw->media_type == e1000_media_type_fiber) && 3851 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3852 DEBUGOUT 3853 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 3854 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3855 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3856 } 3857 return 0; 3858 } 3859 3860 /****************************************************************************** 3861 * Configure the MAC-to-PHY interface for 10/100Mbps 3862 * 3863 * hw - Struct containing variables accessed by shared code 3864 ******************************************************************************/ 3865 static int32_t 3866 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 3867 { 3868 int32_t ret_val = E1000_SUCCESS; 3869 uint32_t tipg; 3870 uint16_t reg_data; 3871 3872 DEBUGFUNC(); 3873 3874 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3875 ret_val = e1000_write_kmrn_reg(hw, 3876 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3877 if (ret_val) 3878 return ret_val; 3879 3880 /* Configure Transmit Inter-Packet Gap */ 3881 tipg = E1000_READ_REG(hw, TIPG); 3882 tipg &= ~E1000_TIPG_IPGT_MASK; 3883 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3884 E1000_WRITE_REG(hw, TIPG, tipg); 3885 3886 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3887 3888 if (ret_val) 3889 return ret_val; 3890 3891 if (duplex == HALF_DUPLEX) 3892 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3893 else 3894 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3895 3896 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3897 3898 return ret_val; 3899 } 3900 3901 static int32_t 3902 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 3903 { 3904 int32_t ret_val = E1000_SUCCESS; 3905 uint16_t reg_data; 3906 uint32_t tipg; 3907 3908 DEBUGFUNC(); 3909 3910 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3911 ret_val = e1000_write_kmrn_reg(hw, 3912 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 3913 if (ret_val) 3914 return ret_val; 3915 3916 /* Configure Transmit Inter-Packet Gap */ 3917 tipg = E1000_READ_REG(hw, TIPG); 3918 tipg &= ~E1000_TIPG_IPGT_MASK; 3919 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3920 E1000_WRITE_REG(hw, TIPG, tipg); 3921 3922 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3923 3924 if (ret_val) 3925 return ret_val; 3926 3927 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3928 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3929 3930 return ret_val; 3931 } 3932 3933 /****************************************************************************** 3934 * Detects the current speed and duplex settings of the hardware. 3935 * 3936 * hw - Struct containing variables accessed by shared code 3937 * speed - Speed of the connection 3938 * duplex - Duplex setting of the connection 3939 *****************************************************************************/ 3940 static int 3941 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 3942 uint16_t *duplex) 3943 { 3944 uint32_t status; 3945 int32_t ret_val; 3946 uint16_t phy_data; 3947 3948 DEBUGFUNC(); 3949 3950 if (hw->mac_type >= e1000_82543) { 3951 status = E1000_READ_REG(hw, STATUS); 3952 if (status & E1000_STATUS_SPEED_1000) { 3953 *speed = SPEED_1000; 3954 DEBUGOUT("1000 Mbs, "); 3955 } else if (status & E1000_STATUS_SPEED_100) { 3956 *speed = SPEED_100; 3957 DEBUGOUT("100 Mbs, "); 3958 } else { 3959 *speed = SPEED_10; 3960 DEBUGOUT("10 Mbs, "); 3961 } 3962 3963 if (status & E1000_STATUS_FD) { 3964 *duplex = FULL_DUPLEX; 3965 DEBUGOUT("Full Duplex\r\n"); 3966 } else { 3967 *duplex = HALF_DUPLEX; 3968 DEBUGOUT(" Half Duplex\r\n"); 3969 } 3970 } else { 3971 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 3972 *speed = SPEED_1000; 3973 *duplex = FULL_DUPLEX; 3974 } 3975 3976 /* IGP01 PHY may advertise full duplex operation after speed downgrade 3977 * even if it is operating at half duplex. Here we set the duplex 3978 * settings to match the duplex in the link partner's capabilities. 3979 */ 3980 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3981 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3982 if (ret_val) 3983 return ret_val; 3984 3985 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3986 *duplex = HALF_DUPLEX; 3987 else { 3988 ret_val = e1000_read_phy_reg(hw, 3989 PHY_LP_ABILITY, &phy_data); 3990 if (ret_val) 3991 return ret_val; 3992 if ((*speed == SPEED_100 && 3993 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 3994 || (*speed == SPEED_10 3995 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3996 *duplex = HALF_DUPLEX; 3997 } 3998 } 3999 4000 if ((hw->mac_type == e1000_80003es2lan) && 4001 (hw->media_type == e1000_media_type_copper)) { 4002 if (*speed == SPEED_1000) 4003 ret_val = e1000_configure_kmrn_for_1000(hw); 4004 else 4005 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 4006 if (ret_val) 4007 return ret_val; 4008 } 4009 return E1000_SUCCESS; 4010 } 4011 4012 /****************************************************************************** 4013 * Blocks until autoneg completes or times out (~4.5 seconds) 4014 * 4015 * hw - Struct containing variables accessed by shared code 4016 ******************************************************************************/ 4017 static int 4018 e1000_wait_autoneg(struct e1000_hw *hw) 4019 { 4020 uint16_t i; 4021 uint16_t phy_data; 4022 4023 DEBUGFUNC(); 4024 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4025 4026 /* We will wait for autoneg to complete or timeout to expire. */ 4027 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4028 /* Read the MII Status Register and wait for Auto-Neg 4029 * Complete bit to be set. 4030 */ 4031 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4032 DEBUGOUT("PHY Read Error\n"); 4033 return -E1000_ERR_PHY; 4034 } 4035 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4036 DEBUGOUT("PHY Read Error\n"); 4037 return -E1000_ERR_PHY; 4038 } 4039 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4040 DEBUGOUT("Auto-Neg complete.\n"); 4041 return 0; 4042 } 4043 mdelay(100); 4044 } 4045 DEBUGOUT("Auto-Neg timedout.\n"); 4046 return -E1000_ERR_TIMEOUT; 4047 } 4048 4049 /****************************************************************************** 4050 * Raises the Management Data Clock 4051 * 4052 * hw - Struct containing variables accessed by shared code 4053 * ctrl - Device control register's current value 4054 ******************************************************************************/ 4055 static void 4056 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4057 { 4058 /* Raise the clock input to the Management Data Clock (by setting the MDC 4059 * bit), and then delay 2 microseconds. 4060 */ 4061 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4062 E1000_WRITE_FLUSH(hw); 4063 udelay(2); 4064 } 4065 4066 /****************************************************************************** 4067 * Lowers the Management Data Clock 4068 * 4069 * hw - Struct containing variables accessed by shared code 4070 * ctrl - Device control register's current value 4071 ******************************************************************************/ 4072 static void 4073 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4074 { 4075 /* Lower the clock input to the Management Data Clock (by clearing the MDC 4076 * bit), and then delay 2 microseconds. 4077 */ 4078 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4079 E1000_WRITE_FLUSH(hw); 4080 udelay(2); 4081 } 4082 4083 /****************************************************************************** 4084 * Shifts data bits out to the PHY 4085 * 4086 * hw - Struct containing variables accessed by shared code 4087 * data - Data to send out to the PHY 4088 * count - Number of bits to shift out 4089 * 4090 * Bits are shifted out in MSB to LSB order. 4091 ******************************************************************************/ 4092 static void 4093 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 4094 { 4095 uint32_t ctrl; 4096 uint32_t mask; 4097 4098 /* We need to shift "count" number of bits out to the PHY. So, the value 4099 * in the "data" parameter will be shifted out to the PHY one bit at a 4100 * time. In order to do this, "data" must be broken down into bits. 4101 */ 4102 mask = 0x01; 4103 mask <<= (count - 1); 4104 4105 ctrl = E1000_READ_REG(hw, CTRL); 4106 4107 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 4108 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4109 4110 while (mask) { 4111 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 4112 * then raising and lowering the Management Data Clock. A "0" is 4113 * shifted out to the PHY by setting the MDIO bit to "0" and then 4114 * raising and lowering the clock. 4115 */ 4116 if (data & mask) 4117 ctrl |= E1000_CTRL_MDIO; 4118 else 4119 ctrl &= ~E1000_CTRL_MDIO; 4120 4121 E1000_WRITE_REG(hw, CTRL, ctrl); 4122 E1000_WRITE_FLUSH(hw); 4123 4124 udelay(2); 4125 4126 e1000_raise_mdi_clk(hw, &ctrl); 4127 e1000_lower_mdi_clk(hw, &ctrl); 4128 4129 mask = mask >> 1; 4130 } 4131 } 4132 4133 /****************************************************************************** 4134 * Shifts data bits in from the PHY 4135 * 4136 * hw - Struct containing variables accessed by shared code 4137 * 4138 * Bits are shifted in in MSB to LSB order. 4139 ******************************************************************************/ 4140 static uint16_t 4141 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4142 { 4143 uint32_t ctrl; 4144 uint16_t data = 0; 4145 uint8_t i; 4146 4147 /* In order to read a register from the PHY, we need to shift in a total 4148 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4149 * to avoid contention on the MDIO pin when a read operation is performed. 4150 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4151 * by raising the input to the Management Data Clock (setting the MDC bit), 4152 * and then reading the value of the MDIO bit. 4153 */ 4154 ctrl = E1000_READ_REG(hw, CTRL); 4155 4156 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4157 ctrl &= ~E1000_CTRL_MDIO_DIR; 4158 ctrl &= ~E1000_CTRL_MDIO; 4159 4160 E1000_WRITE_REG(hw, CTRL, ctrl); 4161 E1000_WRITE_FLUSH(hw); 4162 4163 /* Raise and Lower the clock before reading in the data. This accounts for 4164 * the turnaround bits. The first clock occurred when we clocked out the 4165 * last bit of the Register Address. 4166 */ 4167 e1000_raise_mdi_clk(hw, &ctrl); 4168 e1000_lower_mdi_clk(hw, &ctrl); 4169 4170 for (data = 0, i = 0; i < 16; i++) { 4171 data = data << 1; 4172 e1000_raise_mdi_clk(hw, &ctrl); 4173 ctrl = E1000_READ_REG(hw, CTRL); 4174 /* Check to see if we shifted in a "1". */ 4175 if (ctrl & E1000_CTRL_MDIO) 4176 data |= 1; 4177 e1000_lower_mdi_clk(hw, &ctrl); 4178 } 4179 4180 e1000_raise_mdi_clk(hw, &ctrl); 4181 e1000_lower_mdi_clk(hw, &ctrl); 4182 4183 return data; 4184 } 4185 4186 /***************************************************************************** 4187 * Reads the value from a PHY register 4188 * 4189 * hw - Struct containing variables accessed by shared code 4190 * reg_addr - address of the PHY register to read 4191 ******************************************************************************/ 4192 static int 4193 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4194 { 4195 uint32_t i; 4196 uint32_t mdic = 0; 4197 const uint32_t phy_addr = 1; 4198 4199 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4200 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4201 return -E1000_ERR_PARAM; 4202 } 4203 4204 if (hw->mac_type > e1000_82543) { 4205 /* Set up Op-code, Phy Address, and register address in the MDI 4206 * Control register. The MAC will take care of interfacing with the 4207 * PHY to retrieve the desired data. 4208 */ 4209 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4210 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4211 (E1000_MDIC_OP_READ)); 4212 4213 E1000_WRITE_REG(hw, MDIC, mdic); 4214 4215 /* Poll the ready bit to see if the MDI read completed */ 4216 for (i = 0; i < 64; i++) { 4217 udelay(10); 4218 mdic = E1000_READ_REG(hw, MDIC); 4219 if (mdic & E1000_MDIC_READY) 4220 break; 4221 } 4222 if (!(mdic & E1000_MDIC_READY)) { 4223 DEBUGOUT("MDI Read did not complete\n"); 4224 return -E1000_ERR_PHY; 4225 } 4226 if (mdic & E1000_MDIC_ERROR) { 4227 DEBUGOUT("MDI Error\n"); 4228 return -E1000_ERR_PHY; 4229 } 4230 *phy_data = (uint16_t) mdic; 4231 } else { 4232 /* We must first send a preamble through the MDIO pin to signal the 4233 * beginning of an MII instruction. This is done by sending 32 4234 * consecutive "1" bits. 4235 */ 4236 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4237 4238 /* Now combine the next few fields that are required for a read 4239 * operation. We use this method instead of calling the 4240 * e1000_shift_out_mdi_bits routine five different times. The format of 4241 * a MII read instruction consists of a shift out of 14 bits and is 4242 * defined as follows: 4243 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4244 * followed by a shift in of 18 bits. This first two bits shifted in 4245 * are TurnAround bits used to avoid contention on the MDIO pin when a 4246 * READ operation is performed. These two bits are thrown away 4247 * followed by a shift in of 16 bits which contains the desired data. 4248 */ 4249 mdic = ((reg_addr) | (phy_addr << 5) | 4250 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4251 4252 e1000_shift_out_mdi_bits(hw, mdic, 14); 4253 4254 /* Now that we've shifted out the read command to the MII, we need to 4255 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4256 * register address. 4257 */ 4258 *phy_data = e1000_shift_in_mdi_bits(hw); 4259 } 4260 return 0; 4261 } 4262 4263 /****************************************************************************** 4264 * Writes a value to a PHY register 4265 * 4266 * hw - Struct containing variables accessed by shared code 4267 * reg_addr - address of the PHY register to write 4268 * data - data to write to the PHY 4269 ******************************************************************************/ 4270 static int 4271 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4272 { 4273 uint32_t i; 4274 uint32_t mdic = 0; 4275 const uint32_t phy_addr = 1; 4276 4277 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4278 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4279 return -E1000_ERR_PARAM; 4280 } 4281 4282 if (hw->mac_type > e1000_82543) { 4283 /* Set up Op-code, Phy Address, register address, and data intended 4284 * for the PHY register in the MDI Control register. The MAC will take 4285 * care of interfacing with the PHY to send the desired data. 4286 */ 4287 mdic = (((uint32_t) phy_data) | 4288 (reg_addr << E1000_MDIC_REG_SHIFT) | 4289 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4290 (E1000_MDIC_OP_WRITE)); 4291 4292 E1000_WRITE_REG(hw, MDIC, mdic); 4293 4294 /* Poll the ready bit to see if the MDI read completed */ 4295 for (i = 0; i < 64; i++) { 4296 udelay(10); 4297 mdic = E1000_READ_REG(hw, MDIC); 4298 if (mdic & E1000_MDIC_READY) 4299 break; 4300 } 4301 if (!(mdic & E1000_MDIC_READY)) { 4302 DEBUGOUT("MDI Write did not complete\n"); 4303 return -E1000_ERR_PHY; 4304 } 4305 } else { 4306 /* We'll need to use the SW defined pins to shift the write command 4307 * out to the PHY. We first send a preamble to the PHY to signal the 4308 * beginning of the MII instruction. This is done by sending 32 4309 * consecutive "1" bits. 4310 */ 4311 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4312 4313 /* Now combine the remaining required fields that will indicate a 4314 * write operation. We use this method instead of calling the 4315 * e1000_shift_out_mdi_bits routine for each field in the command. The 4316 * format of a MII write instruction is as follows: 4317 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4318 */ 4319 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4320 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4321 mdic <<= 16; 4322 mdic |= (uint32_t) phy_data; 4323 4324 e1000_shift_out_mdi_bits(hw, mdic, 32); 4325 } 4326 return 0; 4327 } 4328 4329 /****************************************************************************** 4330 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4331 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4332 * the caller to figure out how to deal with it. 4333 * 4334 * hw - Struct containing variables accessed by shared code 4335 * 4336 * returns: - E1000_BLK_PHY_RESET 4337 * E1000_SUCCESS 4338 * 4339 *****************************************************************************/ 4340 int32_t 4341 e1000_check_phy_reset_block(struct e1000_hw *hw) 4342 { 4343 uint32_t manc = 0; 4344 uint32_t fwsm = 0; 4345 4346 if (hw->mac_type == e1000_ich8lan) { 4347 fwsm = E1000_READ_REG(hw, FWSM); 4348 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4349 : E1000_BLK_PHY_RESET; 4350 } 4351 4352 if (hw->mac_type > e1000_82547_rev_2) 4353 manc = E1000_READ_REG(hw, MANC); 4354 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4355 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4356 } 4357 4358 /*************************************************************************** 4359 * Checks if the PHY configuration is done 4360 * 4361 * hw: Struct containing variables accessed by shared code 4362 * 4363 * returns: - E1000_ERR_RESET if fail to reset MAC 4364 * E1000_SUCCESS at any other case. 4365 * 4366 ***************************************************************************/ 4367 static int32_t 4368 e1000_get_phy_cfg_done(struct e1000_hw *hw) 4369 { 4370 int32_t timeout = PHY_CFG_TIMEOUT; 4371 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4372 4373 DEBUGFUNC(); 4374 4375 switch (hw->mac_type) { 4376 default: 4377 mdelay(10); 4378 break; 4379 4380 case e1000_80003es2lan: 4381 /* Separate *_CFG_DONE_* bit for each port */ 4382 if (e1000_is_second_port(hw)) 4383 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4384 /* Fall Through */ 4385 4386 case e1000_82571: 4387 case e1000_82572: 4388 case e1000_igb: 4389 while (timeout) { 4390 if (hw->mac_type == e1000_igb) { 4391 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 4392 break; 4393 } else { 4394 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4395 break; 4396 } 4397 mdelay(1); 4398 timeout--; 4399 } 4400 if (!timeout) { 4401 DEBUGOUT("MNG configuration cycle has not " 4402 "completed.\n"); 4403 return -E1000_ERR_RESET; 4404 } 4405 break; 4406 } 4407 4408 return E1000_SUCCESS; 4409 } 4410 4411 /****************************************************************************** 4412 * Returns the PHY to the power-on reset state 4413 * 4414 * hw - Struct containing variables accessed by shared code 4415 ******************************************************************************/ 4416 int32_t 4417 e1000_phy_hw_reset(struct e1000_hw *hw) 4418 { 4419 uint16_t swfw = E1000_SWFW_PHY0_SM; 4420 uint32_t ctrl, ctrl_ext; 4421 uint32_t led_ctrl; 4422 int32_t ret_val; 4423 4424 DEBUGFUNC(); 4425 4426 /* In the case of the phy reset being blocked, it's not an error, we 4427 * simply return success without performing the reset. */ 4428 ret_val = e1000_check_phy_reset_block(hw); 4429 if (ret_val) 4430 return E1000_SUCCESS; 4431 4432 DEBUGOUT("Resetting Phy...\n"); 4433 4434 if (hw->mac_type > e1000_82543) { 4435 if (e1000_is_second_port(hw)) 4436 swfw = E1000_SWFW_PHY1_SM; 4437 4438 if (e1000_swfw_sync_acquire(hw, swfw)) { 4439 DEBUGOUT("Unable to acquire swfw sync\n"); 4440 return -E1000_ERR_SWFW_SYNC; 4441 } 4442 4443 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4444 * bit. Then, take it out of reset. 4445 */ 4446 ctrl = E1000_READ_REG(hw, CTRL); 4447 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4448 E1000_WRITE_FLUSH(hw); 4449 4450 if (hw->mac_type < e1000_82571) 4451 udelay(10); 4452 else 4453 udelay(100); 4454 4455 E1000_WRITE_REG(hw, CTRL, ctrl); 4456 E1000_WRITE_FLUSH(hw); 4457 4458 if (hw->mac_type >= e1000_82571) 4459 mdelay(10); 4460 4461 } else { 4462 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4463 * bit to put the PHY into reset. Then, take it out of reset. 4464 */ 4465 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4466 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4467 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4468 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4469 E1000_WRITE_FLUSH(hw); 4470 mdelay(10); 4471 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4472 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4473 E1000_WRITE_FLUSH(hw); 4474 } 4475 udelay(150); 4476 4477 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4478 /* Configure activity LED after PHY reset */ 4479 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4480 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4481 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4482 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4483 } 4484 4485 e1000_swfw_sync_release(hw, swfw); 4486 4487 /* Wait for FW to finish PHY configuration. */ 4488 ret_val = e1000_get_phy_cfg_done(hw); 4489 if (ret_val != E1000_SUCCESS) 4490 return ret_val; 4491 4492 return ret_val; 4493 } 4494 4495 /****************************************************************************** 4496 * IGP phy init script - initializes the GbE PHY 4497 * 4498 * hw - Struct containing variables accessed by shared code 4499 *****************************************************************************/ 4500 static void 4501 e1000_phy_init_script(struct e1000_hw *hw) 4502 { 4503 uint32_t ret_val; 4504 uint16_t phy_saved_data; 4505 DEBUGFUNC(); 4506 4507 if (hw->phy_init_script) { 4508 mdelay(20); 4509 4510 /* Save off the current value of register 0x2F5B to be 4511 * restored at the end of this routine. */ 4512 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4513 4514 /* Disabled the PHY transmitter */ 4515 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4516 4517 mdelay(20); 4518 4519 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4520 4521 mdelay(5); 4522 4523 switch (hw->mac_type) { 4524 case e1000_82541: 4525 case e1000_82547: 4526 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4527 4528 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4529 4530 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4531 4532 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4533 4534 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4535 4536 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4537 4538 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4539 4540 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4541 4542 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4543 break; 4544 4545 case e1000_82541_rev_2: 4546 case e1000_82547_rev_2: 4547 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4548 break; 4549 default: 4550 break; 4551 } 4552 4553 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4554 4555 mdelay(20); 4556 4557 /* Now enable the transmitter */ 4558 if (!ret_val) 4559 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4560 4561 if (hw->mac_type == e1000_82547) { 4562 uint16_t fused, fine, coarse; 4563 4564 /* Move to analog registers page */ 4565 e1000_read_phy_reg(hw, 4566 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4567 4568 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4569 e1000_read_phy_reg(hw, 4570 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4571 4572 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4573 coarse = fused 4574 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4575 4576 if (coarse > 4577 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4578 coarse -= 4579 IGP01E1000_ANALOG_FUSE_COARSE_10; 4580 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4581 } else if (coarse 4582 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4583 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4584 4585 fused = (fused 4586 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4587 (fine 4588 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4589 (coarse 4590 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4591 4592 e1000_write_phy_reg(hw, 4593 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4594 e1000_write_phy_reg(hw, 4595 IGP01E1000_ANALOG_FUSE_BYPASS, 4596 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4597 } 4598 } 4599 } 4600 } 4601 4602 /****************************************************************************** 4603 * Resets the PHY 4604 * 4605 * hw - Struct containing variables accessed by shared code 4606 * 4607 * Sets bit 15 of the MII Control register 4608 ******************************************************************************/ 4609 int32_t 4610 e1000_phy_reset(struct e1000_hw *hw) 4611 { 4612 int32_t ret_val; 4613 uint16_t phy_data; 4614 4615 DEBUGFUNC(); 4616 4617 /* In the case of the phy reset being blocked, it's not an error, we 4618 * simply return success without performing the reset. */ 4619 ret_val = e1000_check_phy_reset_block(hw); 4620 if (ret_val) 4621 return E1000_SUCCESS; 4622 4623 switch (hw->phy_type) { 4624 case e1000_phy_igp: 4625 case e1000_phy_igp_2: 4626 case e1000_phy_igp_3: 4627 case e1000_phy_ife: 4628 case e1000_phy_igb: 4629 ret_val = e1000_phy_hw_reset(hw); 4630 if (ret_val) 4631 return ret_val; 4632 break; 4633 default: 4634 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4635 if (ret_val) 4636 return ret_val; 4637 4638 phy_data |= MII_CR_RESET; 4639 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4640 if (ret_val) 4641 return ret_val; 4642 4643 udelay(1); 4644 break; 4645 } 4646 4647 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4648 e1000_phy_init_script(hw); 4649 4650 return E1000_SUCCESS; 4651 } 4652 4653 static int e1000_set_phy_type (struct e1000_hw *hw) 4654 { 4655 DEBUGFUNC (); 4656 4657 if (hw->mac_type == e1000_undefined) 4658 return -E1000_ERR_PHY_TYPE; 4659 4660 switch (hw->phy_id) { 4661 case M88E1000_E_PHY_ID: 4662 case M88E1000_I_PHY_ID: 4663 case M88E1011_I_PHY_ID: 4664 case M88E1111_I_PHY_ID: 4665 hw->phy_type = e1000_phy_m88; 4666 break; 4667 case IGP01E1000_I_PHY_ID: 4668 if (hw->mac_type == e1000_82541 || 4669 hw->mac_type == e1000_82541_rev_2 || 4670 hw->mac_type == e1000_82547 || 4671 hw->mac_type == e1000_82547_rev_2) { 4672 hw->phy_type = e1000_phy_igp; 4673 break; 4674 } 4675 case IGP03E1000_E_PHY_ID: 4676 hw->phy_type = e1000_phy_igp_3; 4677 break; 4678 case IFE_E_PHY_ID: 4679 case IFE_PLUS_E_PHY_ID: 4680 case IFE_C_E_PHY_ID: 4681 hw->phy_type = e1000_phy_ife; 4682 break; 4683 case GG82563_E_PHY_ID: 4684 if (hw->mac_type == e1000_80003es2lan) { 4685 hw->phy_type = e1000_phy_gg82563; 4686 break; 4687 } 4688 case BME1000_E_PHY_ID: 4689 hw->phy_type = e1000_phy_bm; 4690 break; 4691 case I210_I_PHY_ID: 4692 hw->phy_type = e1000_phy_igb; 4693 break; 4694 /* Fall Through */ 4695 default: 4696 /* Should never have loaded on this device */ 4697 hw->phy_type = e1000_phy_undefined; 4698 return -E1000_ERR_PHY_TYPE; 4699 } 4700 4701 return E1000_SUCCESS; 4702 } 4703 4704 /****************************************************************************** 4705 * Probes the expected PHY address for known PHY IDs 4706 * 4707 * hw - Struct containing variables accessed by shared code 4708 ******************************************************************************/ 4709 static int32_t 4710 e1000_detect_gig_phy(struct e1000_hw *hw) 4711 { 4712 int32_t phy_init_status, ret_val; 4713 uint16_t phy_id_high, phy_id_low; 4714 bool match = false; 4715 4716 DEBUGFUNC(); 4717 4718 /* The 82571 firmware may still be configuring the PHY. In this 4719 * case, we cannot access the PHY until the configuration is done. So 4720 * we explicitly set the PHY values. */ 4721 if (hw->mac_type == e1000_82571 || 4722 hw->mac_type == e1000_82572) { 4723 hw->phy_id = IGP01E1000_I_PHY_ID; 4724 hw->phy_type = e1000_phy_igp_2; 4725 return E1000_SUCCESS; 4726 } 4727 4728 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4729 * work- around that forces PHY page 0 to be set or the reads fail. 4730 * The rest of the code in this routine uses e1000_read_phy_reg to 4731 * read the PHY ID. So for ESB-2 we need to have this set so our 4732 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4733 * the routines below will figure this out as well. */ 4734 if (hw->mac_type == e1000_80003es2lan) 4735 hw->phy_type = e1000_phy_gg82563; 4736 4737 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4738 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4739 if (ret_val) 4740 return ret_val; 4741 4742 hw->phy_id = (uint32_t) (phy_id_high << 16); 4743 udelay(20); 4744 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4745 if (ret_val) 4746 return ret_val; 4747 4748 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4749 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4750 4751 switch (hw->mac_type) { 4752 case e1000_82543: 4753 if (hw->phy_id == M88E1000_E_PHY_ID) 4754 match = true; 4755 break; 4756 case e1000_82544: 4757 if (hw->phy_id == M88E1000_I_PHY_ID) 4758 match = true; 4759 break; 4760 case e1000_82540: 4761 case e1000_82545: 4762 case e1000_82545_rev_3: 4763 case e1000_82546: 4764 case e1000_82546_rev_3: 4765 if (hw->phy_id == M88E1011_I_PHY_ID) 4766 match = true; 4767 break; 4768 case e1000_82541: 4769 case e1000_82541_rev_2: 4770 case e1000_82547: 4771 case e1000_82547_rev_2: 4772 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4773 match = true; 4774 4775 break; 4776 case e1000_82573: 4777 if (hw->phy_id == M88E1111_I_PHY_ID) 4778 match = true; 4779 break; 4780 case e1000_82574: 4781 if (hw->phy_id == BME1000_E_PHY_ID) 4782 match = true; 4783 break; 4784 case e1000_80003es2lan: 4785 if (hw->phy_id == GG82563_E_PHY_ID) 4786 match = true; 4787 break; 4788 case e1000_ich8lan: 4789 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4790 match = true; 4791 if (hw->phy_id == IFE_E_PHY_ID) 4792 match = true; 4793 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4794 match = true; 4795 if (hw->phy_id == IFE_C_E_PHY_ID) 4796 match = true; 4797 break; 4798 case e1000_igb: 4799 if (hw->phy_id == I210_I_PHY_ID) 4800 match = true; 4801 break; 4802 default: 4803 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4804 return -E1000_ERR_CONFIG; 4805 } 4806 4807 phy_init_status = e1000_set_phy_type(hw); 4808 4809 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4810 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4811 return 0; 4812 } 4813 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4814 return -E1000_ERR_PHY; 4815 } 4816 4817 /***************************************************************************** 4818 * Set media type and TBI compatibility. 4819 * 4820 * hw - Struct containing variables accessed by shared code 4821 * **************************************************************************/ 4822 void 4823 e1000_set_media_type(struct e1000_hw *hw) 4824 { 4825 uint32_t status; 4826 4827 DEBUGFUNC(); 4828 4829 if (hw->mac_type != e1000_82543) { 4830 /* tbi_compatibility is only valid on 82543 */ 4831 hw->tbi_compatibility_en = false; 4832 } 4833 4834 switch (hw->device_id) { 4835 case E1000_DEV_ID_82545GM_SERDES: 4836 case E1000_DEV_ID_82546GB_SERDES: 4837 case E1000_DEV_ID_82571EB_SERDES: 4838 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4839 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4840 case E1000_DEV_ID_82572EI_SERDES: 4841 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4842 hw->media_type = e1000_media_type_internal_serdes; 4843 break; 4844 default: 4845 switch (hw->mac_type) { 4846 case e1000_82542_rev2_0: 4847 case e1000_82542_rev2_1: 4848 hw->media_type = e1000_media_type_fiber; 4849 break; 4850 case e1000_ich8lan: 4851 case e1000_82573: 4852 case e1000_82574: 4853 case e1000_igb: 4854 /* The STATUS_TBIMODE bit is reserved or reused 4855 * for the this device. 4856 */ 4857 hw->media_type = e1000_media_type_copper; 4858 break; 4859 default: 4860 status = E1000_READ_REG(hw, STATUS); 4861 if (status & E1000_STATUS_TBIMODE) { 4862 hw->media_type = e1000_media_type_fiber; 4863 /* tbi_compatibility not valid on fiber */ 4864 hw->tbi_compatibility_en = false; 4865 } else { 4866 hw->media_type = e1000_media_type_copper; 4867 } 4868 break; 4869 } 4870 } 4871 } 4872 4873 /** 4874 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4875 * 4876 * e1000_sw_init initializes the Adapter private data structure. 4877 * Fields are initialized based on PCI device information and 4878 * OS network device settings (MTU size). 4879 **/ 4880 4881 static int 4882 e1000_sw_init(struct e1000_hw *hw) 4883 { 4884 int result; 4885 4886 /* PCI config space info */ 4887 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 4888 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 4889 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 4890 &hw->subsystem_vendor_id); 4891 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 4892 4893 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 4894 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 4895 4896 /* identify the MAC */ 4897 result = e1000_set_mac_type(hw); 4898 if (result) { 4899 E1000_ERR(hw, "Unknown MAC Type\n"); 4900 return result; 4901 } 4902 4903 switch (hw->mac_type) { 4904 default: 4905 break; 4906 case e1000_82541: 4907 case e1000_82547: 4908 case e1000_82541_rev_2: 4909 case e1000_82547_rev_2: 4910 hw->phy_init_script = 1; 4911 break; 4912 } 4913 4914 /* flow control settings */ 4915 hw->fc_high_water = E1000_FC_HIGH_THRESH; 4916 hw->fc_low_water = E1000_FC_LOW_THRESH; 4917 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 4918 hw->fc_send_xon = 1; 4919 4920 /* Media type - copper or fiber */ 4921 hw->tbi_compatibility_en = true; 4922 e1000_set_media_type(hw); 4923 4924 if (hw->mac_type >= e1000_82543) { 4925 uint32_t status = E1000_READ_REG(hw, STATUS); 4926 4927 if (status & E1000_STATUS_TBIMODE) { 4928 DEBUGOUT("fiber interface\n"); 4929 hw->media_type = e1000_media_type_fiber; 4930 } else { 4931 DEBUGOUT("copper interface\n"); 4932 hw->media_type = e1000_media_type_copper; 4933 } 4934 } else { 4935 hw->media_type = e1000_media_type_fiber; 4936 } 4937 4938 hw->wait_autoneg_complete = true; 4939 if (hw->mac_type < e1000_82543) 4940 hw->report_tx_early = 0; 4941 else 4942 hw->report_tx_early = 1; 4943 4944 return E1000_SUCCESS; 4945 } 4946 4947 void 4948 fill_rx(struct e1000_hw *hw) 4949 { 4950 struct e1000_rx_desc *rd; 4951 unsigned long flush_start, flush_end; 4952 4953 rx_last = rx_tail; 4954 rd = rx_base + rx_tail; 4955 rx_tail = (rx_tail + 1) % 8; 4956 memset(rd, 0, 16); 4957 rd->buffer_addr = cpu_to_le64((unsigned long)packet); 4958 4959 /* 4960 * Make sure there are no stale data in WB over this area, which 4961 * might get written into the memory while the e1000 also writes 4962 * into the same memory area. 4963 */ 4964 invalidate_dcache_range((unsigned long)packet, 4965 (unsigned long)packet + 4096); 4966 /* Dump the DMA descriptor into RAM. */ 4967 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 4968 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 4969 flush_dcache_range(flush_start, flush_end); 4970 4971 E1000_WRITE_REG(hw, RDT, rx_tail); 4972 } 4973 4974 /** 4975 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 4976 * @adapter: board private structure 4977 * 4978 * Configure the Tx unit of the MAC after a reset. 4979 **/ 4980 4981 static void 4982 e1000_configure_tx(struct e1000_hw *hw) 4983 { 4984 unsigned long tctl; 4985 unsigned long tipg, tarc; 4986 uint32_t ipgr1, ipgr2; 4987 4988 E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff); 4989 E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32); 4990 4991 E1000_WRITE_REG(hw, TDLEN, 128); 4992 4993 /* Setup the HW Tx Head and Tail descriptor pointers */ 4994 E1000_WRITE_REG(hw, TDH, 0); 4995 E1000_WRITE_REG(hw, TDT, 0); 4996 tx_tail = 0; 4997 4998 /* Set the default values for the Tx Inter Packet Gap timer */ 4999 if (hw->mac_type <= e1000_82547_rev_2 && 5000 (hw->media_type == e1000_media_type_fiber || 5001 hw->media_type == e1000_media_type_internal_serdes)) 5002 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 5003 else 5004 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 5005 5006 /* Set the default values for the Tx Inter Packet Gap timer */ 5007 switch (hw->mac_type) { 5008 case e1000_82542_rev2_0: 5009 case e1000_82542_rev2_1: 5010 tipg = DEFAULT_82542_TIPG_IPGT; 5011 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 5012 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 5013 break; 5014 case e1000_80003es2lan: 5015 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5016 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 5017 break; 5018 default: 5019 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5020 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 5021 break; 5022 } 5023 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 5024 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 5025 E1000_WRITE_REG(hw, TIPG, tipg); 5026 /* Program the Transmit Control Register */ 5027 tctl = E1000_READ_REG(hw, TCTL); 5028 tctl &= ~E1000_TCTL_CT; 5029 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 5030 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5031 5032 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5033 tarc = E1000_READ_REG(hw, TARC0); 5034 /* set the speed mode bit, we'll clear it if we're not at 5035 * gigabit link later */ 5036 /* git bit can be set to 1*/ 5037 } else if (hw->mac_type == e1000_80003es2lan) { 5038 tarc = E1000_READ_REG(hw, TARC0); 5039 tarc |= 1; 5040 E1000_WRITE_REG(hw, TARC0, tarc); 5041 tarc = E1000_READ_REG(hw, TARC1); 5042 tarc |= 1; 5043 E1000_WRITE_REG(hw, TARC1, tarc); 5044 } 5045 5046 5047 e1000_config_collision_dist(hw); 5048 /* Setup Transmit Descriptor Settings for eop descriptor */ 5049 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 5050 5051 /* Need to set up RS bit */ 5052 if (hw->mac_type < e1000_82543) 5053 hw->txd_cmd |= E1000_TXD_CMD_RPS; 5054 else 5055 hw->txd_cmd |= E1000_TXD_CMD_RS; 5056 5057 5058 if (hw->mac_type == e1000_igb) { 5059 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 5060 5061 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 5062 reg_txdctl |= 1 << 25; 5063 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 5064 mdelay(20); 5065 } 5066 5067 5068 5069 E1000_WRITE_REG(hw, TCTL, tctl); 5070 5071 5072 } 5073 5074 /** 5075 * e1000_setup_rctl - configure the receive control register 5076 * @adapter: Board private structure 5077 **/ 5078 static void 5079 e1000_setup_rctl(struct e1000_hw *hw) 5080 { 5081 uint32_t rctl; 5082 5083 rctl = E1000_READ_REG(hw, RCTL); 5084 5085 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 5086 5087 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5088 | E1000_RCTL_RDMTS_HALF; /* | 5089 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 5090 5091 if (hw->tbi_compatibility_on == 1) 5092 rctl |= E1000_RCTL_SBP; 5093 else 5094 rctl &= ~E1000_RCTL_SBP; 5095 5096 rctl &= ~(E1000_RCTL_SZ_4096); 5097 rctl |= E1000_RCTL_SZ_2048; 5098 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 5099 E1000_WRITE_REG(hw, RCTL, rctl); 5100 } 5101 5102 /** 5103 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 5104 * @adapter: board private structure 5105 * 5106 * Configure the Rx unit of the MAC after a reset. 5107 **/ 5108 static void 5109 e1000_configure_rx(struct e1000_hw *hw) 5110 { 5111 unsigned long rctl, ctrl_ext; 5112 rx_tail = 0; 5113 /* make sure receives are disabled while setting up the descriptors */ 5114 rctl = E1000_READ_REG(hw, RCTL); 5115 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 5116 if (hw->mac_type >= e1000_82540) { 5117 /* Set the interrupt throttling rate. Value is calculated 5118 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 5119 #define MAX_INTS_PER_SEC 8000 5120 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 5121 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 5122 } 5123 5124 if (hw->mac_type >= e1000_82571) { 5125 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5126 /* Reset delay timers after every interrupt */ 5127 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5128 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5129 E1000_WRITE_FLUSH(hw); 5130 } 5131 /* Setup the Base and Length of the Rx Descriptor Ring */ 5132 E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff); 5133 E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32); 5134 5135 E1000_WRITE_REG(hw, RDLEN, 128); 5136 5137 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 5138 E1000_WRITE_REG(hw, RDH, 0); 5139 E1000_WRITE_REG(hw, RDT, 0); 5140 /* Enable Receives */ 5141 5142 if (hw->mac_type == e1000_igb) { 5143 5144 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 5145 reg_rxdctl |= 1 << 25; 5146 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 5147 mdelay(20); 5148 } 5149 5150 E1000_WRITE_REG(hw, RCTL, rctl); 5151 5152 fill_rx(hw); 5153 } 5154 5155 /************************************************************************** 5156 POLL - Wait for a frame 5157 ***************************************************************************/ 5158 static int 5159 _e1000_poll(struct e1000_hw *hw) 5160 { 5161 struct e1000_rx_desc *rd; 5162 unsigned long inval_start, inval_end; 5163 uint32_t len; 5164 5165 /* return true if there's an ethernet packet ready to read */ 5166 rd = rx_base + rx_last; 5167 5168 /* Re-load the descriptor from RAM. */ 5169 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5170 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5171 invalidate_dcache_range(inval_start, inval_end); 5172 5173 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 5174 return 0; 5175 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ 5176 /* Packet received, make sure the data are re-loaded from RAM. */ 5177 len = le32_to_cpu(rd->length); 5178 invalidate_dcache_range((unsigned long)packet, 5179 (unsigned long)packet + 5180 roundup(len, ARCH_DMA_MINALIGN)); 5181 return len; 5182 } 5183 5184 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) 5185 { 5186 void *nv_packet = (void *)txpacket; 5187 struct e1000_tx_desc *txp; 5188 int i = 0; 5189 unsigned long flush_start, flush_end; 5190 5191 txp = tx_base + tx_tail; 5192 tx_tail = (tx_tail + 1) % 8; 5193 5194 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); 5195 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5196 txp->upper.data = 0; 5197 5198 /* Dump the packet into RAM so e1000 can pick them. */ 5199 flush_dcache_range((unsigned long)nv_packet, 5200 (unsigned long)nv_packet + 5201 roundup(length, ARCH_DMA_MINALIGN)); 5202 /* Dump the descriptor into RAM as well. */ 5203 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); 5204 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5205 flush_dcache_range(flush_start, flush_end); 5206 5207 E1000_WRITE_REG(hw, TDT, tx_tail); 5208 5209 E1000_WRITE_FLUSH(hw); 5210 while (1) { 5211 invalidate_dcache_range(flush_start, flush_end); 5212 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5213 break; 5214 if (i++ > TOUT_LOOP) { 5215 DEBUGOUT("e1000: tx timeout\n"); 5216 return 0; 5217 } 5218 udelay(10); /* give the nic a chance to write to the register */ 5219 } 5220 return 1; 5221 } 5222 5223 static void 5224 _e1000_disable(struct e1000_hw *hw) 5225 { 5226 /* Turn off the ethernet interface */ 5227 E1000_WRITE_REG(hw, RCTL, 0); 5228 E1000_WRITE_REG(hw, TCTL, 0); 5229 5230 /* Clear the transmit ring */ 5231 E1000_WRITE_REG(hw, TDH, 0); 5232 E1000_WRITE_REG(hw, TDT, 0); 5233 5234 /* Clear the receive ring */ 5235 E1000_WRITE_REG(hw, RDH, 0); 5236 E1000_WRITE_REG(hw, RDT, 0); 5237 5238 /* put the card in its initial state */ 5239 #if 0 5240 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 5241 #endif 5242 mdelay(10); 5243 } 5244 5245 /*reset function*/ 5246 static inline int 5247 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) 5248 { 5249 e1000_reset_hw(hw); 5250 if (hw->mac_type >= e1000_82544) 5251 E1000_WRITE_REG(hw, WUC, 0); 5252 5253 return e1000_init_hw(hw, enetaddr); 5254 } 5255 5256 static int 5257 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) 5258 { 5259 int ret_val = 0; 5260 5261 ret_val = e1000_reset(hw, enetaddr); 5262 if (ret_val < 0) { 5263 if ((ret_val == -E1000_ERR_NOLINK) || 5264 (ret_val == -E1000_ERR_TIMEOUT)) { 5265 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); 5266 } else { 5267 E1000_ERR(hw, "Hardware Initialization Failed\n"); 5268 } 5269 return ret_val; 5270 } 5271 e1000_configure_tx(hw); 5272 e1000_setup_rctl(hw); 5273 e1000_configure_rx(hw); 5274 return 0; 5275 } 5276 5277 /****************************************************************************** 5278 * Gets the current PCI bus type of hardware 5279 * 5280 * hw - Struct containing variables accessed by shared code 5281 *****************************************************************************/ 5282 void e1000_get_bus_type(struct e1000_hw *hw) 5283 { 5284 uint32_t status; 5285 5286 switch (hw->mac_type) { 5287 case e1000_82542_rev2_0: 5288 case e1000_82542_rev2_1: 5289 hw->bus_type = e1000_bus_type_pci; 5290 break; 5291 case e1000_82571: 5292 case e1000_82572: 5293 case e1000_82573: 5294 case e1000_82574: 5295 case e1000_80003es2lan: 5296 case e1000_ich8lan: 5297 case e1000_igb: 5298 hw->bus_type = e1000_bus_type_pci_express; 5299 break; 5300 default: 5301 status = E1000_READ_REG(hw, STATUS); 5302 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5303 e1000_bus_type_pcix : e1000_bus_type_pci; 5304 break; 5305 } 5306 } 5307 5308 #ifndef CONFIG_DM_ETH 5309 /* A list of all registered e1000 devices */ 5310 static LIST_HEAD(e1000_hw_list); 5311 #endif 5312 5313 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, 5314 unsigned char enetaddr[6]) 5315 { 5316 u32 val; 5317 5318 /* Assign the passed-in values */ 5319 hw->pdev = devno; 5320 hw->cardnum = cardnum; 5321 5322 /* Print a debug message with the IO base address */ 5323 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); 5324 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); 5325 5326 /* Try to enable I/O accesses and bus-mastering */ 5327 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5328 pci_write_config_dword(devno, PCI_COMMAND, val); 5329 5330 /* Make sure it worked */ 5331 pci_read_config_dword(devno, PCI_COMMAND, &val); 5332 if (!(val & PCI_COMMAND_MEMORY)) { 5333 E1000_ERR(hw, "Can't enable I/O memory\n"); 5334 return -ENOSPC; 5335 } 5336 if (!(val & PCI_COMMAND_MASTER)) { 5337 E1000_ERR(hw, "Can't enable bus-mastering\n"); 5338 return -EPERM; 5339 } 5340 5341 /* Are these variables needed? */ 5342 hw->fc = e1000_fc_default; 5343 hw->original_fc = e1000_fc_default; 5344 hw->autoneg_failed = 0; 5345 hw->autoneg = 1; 5346 hw->get_link_status = true; 5347 #ifndef CONFIG_E1000_NO_NVM 5348 hw->eeprom_semaphore_present = true; 5349 #endif 5350 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 5351 PCI_REGION_MEM); 5352 hw->mac_type = e1000_undefined; 5353 5354 /* MAC and Phy settings */ 5355 if (e1000_sw_init(hw) < 0) { 5356 E1000_ERR(hw, "Software init failed\n"); 5357 return -EIO; 5358 } 5359 if (e1000_check_phy_reset_block(hw)) 5360 E1000_ERR(hw, "PHY Reset is blocked!\n"); 5361 5362 /* Basic init was OK, reset the hardware and allow SPI access */ 5363 e1000_reset_hw(hw); 5364 5365 #ifndef CONFIG_E1000_NO_NVM 5366 /* Validate the EEPROM and get chipset information */ 5367 #if !defined(CONFIG_MVBC_1G) 5368 if (e1000_init_eeprom_params(hw)) { 5369 E1000_ERR(hw, "EEPROM is invalid!\n"); 5370 return -EINVAL; 5371 } 5372 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 5373 e1000_validate_eeprom_checksum(hw)) 5374 return -ENXIO; 5375 #endif 5376 e1000_read_mac_addr(hw, enetaddr); 5377 #endif 5378 e1000_get_bus_type(hw); 5379 5380 #ifndef CONFIG_E1000_NO_NVM 5381 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5382 enetaddr[0], enetaddr[1], enetaddr[2], 5383 enetaddr[3], enetaddr[4], enetaddr[5]); 5384 #else 5385 memset(enetaddr, 0, 6); 5386 printf("e1000: no NVM\n"); 5387 #endif 5388 5389 return 0; 5390 } 5391 5392 /* Put the name of a device in a string */ 5393 static void e1000_name(char *str, int cardnum) 5394 { 5395 sprintf(str, "e1000#%u", cardnum); 5396 } 5397 5398 #ifndef CONFIG_DM_ETH 5399 /************************************************************************** 5400 TRANSMIT - Transmit a frame 5401 ***************************************************************************/ 5402 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) 5403 { 5404 struct e1000_hw *hw = nic->priv; 5405 5406 return _e1000_transmit(hw, txpacket, length); 5407 } 5408 5409 /************************************************************************** 5410 DISABLE - Turn off ethernet interface 5411 ***************************************************************************/ 5412 static void 5413 e1000_disable(struct eth_device *nic) 5414 { 5415 struct e1000_hw *hw = nic->priv; 5416 5417 _e1000_disable(hw); 5418 } 5419 5420 /************************************************************************** 5421 INIT - set up ethernet interface(s) 5422 ***************************************************************************/ 5423 static int 5424 e1000_init(struct eth_device *nic, bd_t *bis) 5425 { 5426 struct e1000_hw *hw = nic->priv; 5427 5428 return _e1000_init(hw, nic->enetaddr); 5429 } 5430 5431 static int 5432 e1000_poll(struct eth_device *nic) 5433 { 5434 struct e1000_hw *hw = nic->priv; 5435 int len; 5436 5437 len = _e1000_poll(hw); 5438 if (len) { 5439 net_process_received_packet((uchar *)packet, len); 5440 fill_rx(hw); 5441 } 5442 5443 return len ? 1 : 0; 5444 } 5445 5446 /************************************************************************** 5447 PROBE - Look for an adapter, this routine's visible to the outside 5448 You should omit the last argument struct pci_device * for a non-PCI NIC 5449 ***************************************************************************/ 5450 int 5451 e1000_initialize(bd_t * bis) 5452 { 5453 unsigned int i; 5454 pci_dev_t devno; 5455 int ret; 5456 5457 DEBUGFUNC(); 5458 5459 /* Find and probe all the matching PCI devices */ 5460 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { 5461 /* 5462 * These will never get freed due to errors, this allows us to 5463 * perform SPI EEPROM programming from U-boot, for example. 5464 */ 5465 struct eth_device *nic = malloc(sizeof(*nic)); 5466 struct e1000_hw *hw = malloc(sizeof(*hw)); 5467 if (!nic || !hw) { 5468 printf("e1000#%u: Out of Memory!\n", i); 5469 free(nic); 5470 free(hw); 5471 continue; 5472 } 5473 5474 /* Make sure all of the fields are initially zeroed */ 5475 memset(nic, 0, sizeof(*nic)); 5476 memset(hw, 0, sizeof(*hw)); 5477 nic->priv = hw; 5478 5479 /* Generate a card name */ 5480 e1000_name(nic->name, i); 5481 hw->name = nic->name; 5482 5483 ret = e1000_init_one(hw, i, devno, nic->enetaddr); 5484 if (ret) 5485 continue; 5486 list_add_tail(&hw->list_node, &e1000_hw_list); 5487 5488 hw->nic = nic; 5489 5490 /* Set up the function pointers and register the device */ 5491 nic->init = e1000_init; 5492 nic->recv = e1000_poll; 5493 nic->send = e1000_transmit; 5494 nic->halt = e1000_disable; 5495 eth_register(nic); 5496 } 5497 5498 return i; 5499 } 5500 5501 struct e1000_hw *e1000_find_card(unsigned int cardnum) 5502 { 5503 struct e1000_hw *hw; 5504 5505 list_for_each_entry(hw, &e1000_hw_list, list_node) 5506 if (hw->cardnum == cardnum) 5507 return hw; 5508 5509 return NULL; 5510 } 5511 #endif /* !CONFIG_DM_ETH */ 5512 5513 #ifdef CONFIG_CMD_E1000 5514 static int do_e1000(cmd_tbl_t *cmdtp, int flag, 5515 int argc, char * const argv[]) 5516 { 5517 unsigned char *mac = NULL; 5518 #ifdef CONFIG_DM_ETH 5519 struct eth_pdata *plat; 5520 struct udevice *dev; 5521 char name[30]; 5522 int ret; 5523 #else 5524 struct e1000_hw *hw; 5525 #endif 5526 int cardnum; 5527 5528 if (argc < 3) { 5529 cmd_usage(cmdtp); 5530 return 1; 5531 } 5532 5533 /* Make sure we can find the requested e1000 card */ 5534 cardnum = simple_strtoul(argv[1], NULL, 10); 5535 #ifdef CONFIG_DM_ETH 5536 e1000_name(name, cardnum); 5537 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); 5538 if (!ret) { 5539 plat = dev_get_platdata(dev); 5540 mac = plat->enetaddr; 5541 } 5542 #else 5543 hw = e1000_find_card(cardnum); 5544 if (hw) 5545 mac = hw->nic->enetaddr; 5546 #endif 5547 if (!mac) { 5548 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5549 return 1; 5550 } 5551 5552 if (!strcmp(argv[2], "print-mac-address")) { 5553 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5554 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5555 return 0; 5556 } 5557 5558 #ifdef CONFIG_E1000_SPI 5559 /* Handle the "SPI" subcommand */ 5560 if (!strcmp(argv[2], "spi")) 5561 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5562 #endif 5563 5564 cmd_usage(cmdtp); 5565 return 1; 5566 } 5567 5568 U_BOOT_CMD( 5569 e1000, 7, 0, do_e1000, 5570 "Intel e1000 controller management", 5571 /* */"<card#> print-mac-address\n" 5572 #ifdef CONFIG_E1000_SPI 5573 "e1000 <card#> spi show [<offset> [<length>]]\n" 5574 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5575 "e1000 <card#> spi program <addr> <offset> <length>\n" 5576 "e1000 <card#> spi checksum [update]\n" 5577 #endif 5578 " - Manage the Intel E1000 PCI device" 5579 ); 5580 #endif /* not CONFIG_CMD_E1000 */ 5581 5582 #ifdef CONFIG_DM_ETH 5583 static int e1000_eth_start(struct udevice *dev) 5584 { 5585 struct eth_pdata *plat = dev_get_platdata(dev); 5586 struct e1000_hw *hw = dev_get_priv(dev); 5587 5588 return _e1000_init(hw, plat->enetaddr); 5589 } 5590 5591 static void e1000_eth_stop(struct udevice *dev) 5592 { 5593 struct e1000_hw *hw = dev_get_priv(dev); 5594 5595 _e1000_disable(hw); 5596 } 5597 5598 static int e1000_eth_send(struct udevice *dev, void *packet, int length) 5599 { 5600 struct e1000_hw *hw = dev_get_priv(dev); 5601 int ret; 5602 5603 ret = _e1000_transmit(hw, packet, length); 5604 5605 return ret ? 0 : -ETIMEDOUT; 5606 } 5607 5608 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) 5609 { 5610 struct e1000_hw *hw = dev_get_priv(dev); 5611 int len; 5612 5613 len = _e1000_poll(hw); 5614 if (len) 5615 *packetp = packet; 5616 5617 return len ? len : -EAGAIN; 5618 } 5619 5620 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) 5621 { 5622 struct e1000_hw *hw = dev_get_priv(dev); 5623 5624 fill_rx(hw); 5625 5626 return 0; 5627 } 5628 5629 static int e1000_eth_probe(struct udevice *dev) 5630 { 5631 struct eth_pdata *plat = dev_get_platdata(dev); 5632 struct e1000_hw *hw = dev_get_priv(dev); 5633 int ret; 5634 5635 hw->name = dev->name; 5636 ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), 5637 plat->enetaddr); 5638 if (ret < 0) { 5639 printf(pr_fmt("failed to initialize card: %d\n"), ret); 5640 return ret; 5641 } 5642 5643 return 0; 5644 } 5645 5646 static int e1000_eth_bind(struct udevice *dev) 5647 { 5648 char name[20]; 5649 5650 /* 5651 * A simple way to number the devices. When device tree is used this 5652 * is unnecessary, but when the device is just discovered on the PCI 5653 * bus we need a name. We could instead have the uclass figure out 5654 * which devices are different and number them. 5655 */ 5656 e1000_name(name, num_cards++); 5657 5658 return device_set_name(dev, name); 5659 } 5660 5661 static const struct eth_ops e1000_eth_ops = { 5662 .start = e1000_eth_start, 5663 .send = e1000_eth_send, 5664 .recv = e1000_eth_recv, 5665 .stop = e1000_eth_stop, 5666 .free_pkt = e1000_free_pkt, 5667 }; 5668 5669 static const struct udevice_id e1000_eth_ids[] = { 5670 { .compatible = "intel,e1000" }, 5671 { } 5672 }; 5673 5674 U_BOOT_DRIVER(eth_e1000) = { 5675 .name = "eth_e1000", 5676 .id = UCLASS_ETH, 5677 .of_match = e1000_eth_ids, 5678 .bind = e1000_eth_bind, 5679 .probe = e1000_eth_probe, 5680 .ops = &e1000_eth_ops, 5681 .priv_auto_alloc_size = sizeof(struct e1000_hw), 5682 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 5683 }; 5684 5685 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); 5686 #endif 5687