1 /************************************************************************** 2 Intel Pro 1000 for ppcboot/das-u-boot 3 Drivers are port from Intel's Linux driver e1000-4.3.15 4 and from Etherboot pro 1000 driver by mrakes at vivato dot net 5 tested on both gig copper and gig fiber boards 6 ***************************************************************************/ 7 /******************************************************************************* 8 9 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published by the Free 14 Software Foundation; either version 2 of the License, or (at your option) 15 any later version. 16 17 This program is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 more details. 21 22 You should have received a copy of the GNU General Public License along with 23 this program; if not, write to the Free Software Foundation, Inc., 59 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 26 The full GNU General Public License is included in this distribution in the 27 file called LICENSE. 28 29 Contact Information: 30 Linux NICS <linux.nics@intel.com> 31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 33 *******************************************************************************/ 34 /* 35 * Copyright (C) Archway Digital Solutions. 36 * 37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 38 * 2/9/2002 39 * 40 * Copyright (C) Linux Networx. 41 * Massive upgrade to work with the new intel gigabit NICs. 42 * <ebiederman at lnxi dot com> 43 */ 44 45 #include "e1000.h" 46 47 #define TOUT_LOOP 100000 48 49 #undef virt_to_bus 50 #define virt_to_bus(x) ((unsigned long)x) 51 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) 52 #define mdelay(n) udelay((n)*1000) 53 54 #define E1000_DEFAULT_PBA 0x00000030 55 56 /* NIC specific static variables go here */ 57 58 static char tx_pool[128 + 16]; 59 static char rx_pool[128 + 16]; 60 static char packet[2096]; 61 62 static struct e1000_tx_desc *tx_base; 63 static struct e1000_rx_desc *rx_base; 64 65 static int tx_tail; 66 static int rx_tail, rx_last; 67 68 static struct pci_device_id supported[] = { 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, 72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, 73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, 74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, 75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, 76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, 77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, 82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, 85 }; 86 87 /* Function forward declarations */ 88 static int e1000_setup_link(struct eth_device *nic); 89 static int e1000_setup_fiber_link(struct eth_device *nic); 90 static int e1000_setup_copper_link(struct eth_device *nic); 91 static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 92 static void e1000_config_collision_dist(struct e1000_hw *hw); 93 static int e1000_config_mac_to_phy(struct e1000_hw *hw); 94 static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 95 static int e1000_check_for_link(struct eth_device *nic); 96 static int e1000_wait_autoneg(struct e1000_hw *hw); 97 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 98 uint16_t * duplex); 99 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 100 uint16_t * phy_data); 101 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 102 uint16_t phy_data); 103 static void e1000_phy_hw_reset(struct e1000_hw *hw); 104 static int e1000_phy_reset(struct e1000_hw *hw); 105 static int e1000_detect_gig_phy(struct e1000_hw *hw); 106 107 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) 108 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) 109 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ 110 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) 111 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ 112 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) 113 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} 114 115 #ifndef CONFIG_AP1000 /* remove for warnings */ 116 /****************************************************************************** 117 * Raises the EEPROM's clock input. 118 * 119 * hw - Struct containing variables accessed by shared code 120 * eecd - EECD's current value 121 *****************************************************************************/ 122 static void 123 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 124 { 125 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 126 * wait 50 microseconds. 127 */ 128 *eecd = *eecd | E1000_EECD_SK; 129 E1000_WRITE_REG(hw, EECD, *eecd); 130 E1000_WRITE_FLUSH(hw); 131 udelay(50); 132 } 133 134 /****************************************************************************** 135 * Lowers the EEPROM's clock input. 136 * 137 * hw - Struct containing variables accessed by shared code 138 * eecd - EECD's current value 139 *****************************************************************************/ 140 static void 141 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 142 { 143 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 144 * wait 50 microseconds. 145 */ 146 *eecd = *eecd & ~E1000_EECD_SK; 147 E1000_WRITE_REG(hw, EECD, *eecd); 148 E1000_WRITE_FLUSH(hw); 149 udelay(50); 150 } 151 152 /****************************************************************************** 153 * Shift data bits out to the EEPROM. 154 * 155 * hw - Struct containing variables accessed by shared code 156 * data - data to send to the EEPROM 157 * count - number of bits to shift out 158 *****************************************************************************/ 159 static void 160 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 161 { 162 uint32_t eecd; 163 uint32_t mask; 164 165 /* We need to shift "count" bits out to the EEPROM. So, value in the 166 * "data" parameter will be shifted out to the EEPROM one bit at a time. 167 * In order to do this, "data" must be broken down into bits. 168 */ 169 mask = 0x01 << (count - 1); 170 eecd = E1000_READ_REG(hw, EECD); 171 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 172 do { 173 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 174 * and then raising and then lowering the clock (the SK bit controls 175 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 176 * by setting "DI" to "0" and then raising and then lowering the clock. 177 */ 178 eecd &= ~E1000_EECD_DI; 179 180 if (data & mask) 181 eecd |= E1000_EECD_DI; 182 183 E1000_WRITE_REG(hw, EECD, eecd); 184 E1000_WRITE_FLUSH(hw); 185 186 udelay(50); 187 188 e1000_raise_ee_clk(hw, &eecd); 189 e1000_lower_ee_clk(hw, &eecd); 190 191 mask = mask >> 1; 192 193 } while (mask); 194 195 /* We leave the "DI" bit set to "0" when we leave this routine. */ 196 eecd &= ~E1000_EECD_DI; 197 E1000_WRITE_REG(hw, EECD, eecd); 198 } 199 200 /****************************************************************************** 201 * Shift data bits in from the EEPROM 202 * 203 * hw - Struct containing variables accessed by shared code 204 *****************************************************************************/ 205 static uint16_t 206 e1000_shift_in_ee_bits(struct e1000_hw *hw) 207 { 208 uint32_t eecd; 209 uint32_t i; 210 uint16_t data; 211 212 /* In order to read a register from the EEPROM, we need to shift 16 bits 213 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 214 * the EEPROM (setting the SK bit), and then reading the value of the "DO" 215 * bit. During this "shifting in" process the "DI" bit should always be 216 * clear.. 217 */ 218 219 eecd = E1000_READ_REG(hw, EECD); 220 221 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 222 data = 0; 223 224 for (i = 0; i < 16; i++) { 225 data = data << 1; 226 e1000_raise_ee_clk(hw, &eecd); 227 228 eecd = E1000_READ_REG(hw, EECD); 229 230 eecd &= ~(E1000_EECD_DI); 231 if (eecd & E1000_EECD_DO) 232 data |= 1; 233 234 e1000_lower_ee_clk(hw, &eecd); 235 } 236 237 return data; 238 } 239 240 /****************************************************************************** 241 * Prepares EEPROM for access 242 * 243 * hw - Struct containing variables accessed by shared code 244 * 245 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 246 * function should be called before issuing a command to the EEPROM. 247 *****************************************************************************/ 248 static void 249 e1000_setup_eeprom(struct e1000_hw *hw) 250 { 251 uint32_t eecd; 252 253 eecd = E1000_READ_REG(hw, EECD); 254 255 /* Clear SK and DI */ 256 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); 257 E1000_WRITE_REG(hw, EECD, eecd); 258 259 /* Set CS */ 260 eecd |= E1000_EECD_CS; 261 E1000_WRITE_REG(hw, EECD, eecd); 262 } 263 264 /****************************************************************************** 265 * Returns EEPROM to a "standby" state 266 * 267 * hw - Struct containing variables accessed by shared code 268 *****************************************************************************/ 269 static void 270 e1000_standby_eeprom(struct e1000_hw *hw) 271 { 272 uint32_t eecd; 273 274 eecd = E1000_READ_REG(hw, EECD); 275 276 /* Deselct EEPROM */ 277 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 278 E1000_WRITE_REG(hw, EECD, eecd); 279 E1000_WRITE_FLUSH(hw); 280 udelay(50); 281 282 /* Clock high */ 283 eecd |= E1000_EECD_SK; 284 E1000_WRITE_REG(hw, EECD, eecd); 285 E1000_WRITE_FLUSH(hw); 286 udelay(50); 287 288 /* Select EEPROM */ 289 eecd |= E1000_EECD_CS; 290 E1000_WRITE_REG(hw, EECD, eecd); 291 E1000_WRITE_FLUSH(hw); 292 udelay(50); 293 294 /* Clock low */ 295 eecd &= ~E1000_EECD_SK; 296 E1000_WRITE_REG(hw, EECD, eecd); 297 E1000_WRITE_FLUSH(hw); 298 udelay(50); 299 } 300 301 /****************************************************************************** 302 * Reads a 16 bit word from the EEPROM. 303 * 304 * hw - Struct containing variables accessed by shared code 305 * offset - offset of word in the EEPROM to read 306 * data - word read from the EEPROM 307 *****************************************************************************/ 308 static int 309 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) 310 { 311 uint32_t eecd; 312 uint32_t i = 0; 313 int large_eeprom = FALSE; 314 315 /* Request EEPROM Access */ 316 if (hw->mac_type > e1000_82544) { 317 eecd = E1000_READ_REG(hw, EECD); 318 if (eecd & E1000_EECD_SIZE) 319 large_eeprom = TRUE; 320 eecd |= E1000_EECD_REQ; 321 E1000_WRITE_REG(hw, EECD, eecd); 322 eecd = E1000_READ_REG(hw, EECD); 323 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 324 i++; 325 udelay(10); 326 eecd = E1000_READ_REG(hw, EECD); 327 } 328 if (!(eecd & E1000_EECD_GNT)) { 329 eecd &= ~E1000_EECD_REQ; 330 E1000_WRITE_REG(hw, EECD, eecd); 331 DEBUGOUT("Could not acquire EEPROM grant\n"); 332 return -E1000_ERR_EEPROM; 333 } 334 } 335 336 /* Prepare the EEPROM for reading */ 337 e1000_setup_eeprom(hw); 338 339 /* Send the READ command (opcode + addr) */ 340 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); 341 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); 342 343 /* Read the data */ 344 *data = e1000_shift_in_ee_bits(hw); 345 346 /* End this read operation */ 347 e1000_standby_eeprom(hw); 348 349 /* Stop requesting EEPROM access */ 350 if (hw->mac_type > e1000_82544) { 351 eecd = E1000_READ_REG(hw, EECD); 352 eecd &= ~E1000_EECD_REQ; 353 E1000_WRITE_REG(hw, EECD, eecd); 354 } 355 356 return 0; 357 } 358 359 #if 0 360 static void 361 e1000_eeprom_cleanup(struct e1000_hw *hw) 362 { 363 uint32_t eecd; 364 365 eecd = E1000_READ_REG(hw, EECD); 366 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 367 E1000_WRITE_REG(hw, EECD, eecd); 368 e1000_raise_ee_clk(hw, &eecd); 369 e1000_lower_ee_clk(hw, &eecd); 370 } 371 372 static uint16_t 373 e1000_wait_eeprom_done(struct e1000_hw *hw) 374 { 375 uint32_t eecd; 376 uint32_t i; 377 378 e1000_standby_eeprom(hw); 379 for (i = 0; i < 200; i++) { 380 eecd = E1000_READ_REG(hw, EECD); 381 if (eecd & E1000_EECD_DO) 382 return (TRUE); 383 udelay(5); 384 } 385 return (FALSE); 386 } 387 388 static int 389 e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) 390 { 391 uint32_t eecd; 392 int large_eeprom = FALSE; 393 int i = 0; 394 395 /* Request EEPROM Access */ 396 if (hw->mac_type > e1000_82544) { 397 eecd = E1000_READ_REG(hw, EECD); 398 if (eecd & E1000_EECD_SIZE) 399 large_eeprom = TRUE; 400 eecd |= E1000_EECD_REQ; 401 E1000_WRITE_REG(hw, EECD, eecd); 402 eecd = E1000_READ_REG(hw, EECD); 403 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { 404 i++; 405 udelay(5); 406 eecd = E1000_READ_REG(hw, EECD); 407 } 408 if (!(eecd & E1000_EECD_GNT)) { 409 eecd &= ~E1000_EECD_REQ; 410 E1000_WRITE_REG(hw, EECD, eecd); 411 DEBUGOUT("Could not acquire EEPROM grant\n"); 412 return FALSE; 413 } 414 } 415 e1000_setup_eeprom(hw); 416 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); 417 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 418 e1000_standby_eeprom(hw); 419 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); 420 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); 421 e1000_shift_out_ee_bits(hw, Data, 16); 422 if (!e1000_wait_eeprom_done(hw)) { 423 return FALSE; 424 } 425 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); 426 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); 427 e1000_eeprom_cleanup(hw); 428 429 /* Stop requesting EEPROM access */ 430 if (hw->mac_type > e1000_82544) { 431 eecd = E1000_READ_REG(hw, EECD); 432 eecd &= ~E1000_EECD_REQ; 433 E1000_WRITE_REG(hw, EECD, eecd); 434 } 435 i = 0; 436 eecd = E1000_READ_REG(hw, EECD); 437 while (((eecd & E1000_EECD_GNT)) && (i < 500)) { 438 i++; 439 udelay(10); 440 eecd = E1000_READ_REG(hw, EECD); 441 } 442 if ((eecd & E1000_EECD_GNT)) { 443 DEBUGOUT("Could not release EEPROM grant\n"); 444 } 445 return TRUE; 446 } 447 #endif 448 449 /****************************************************************************** 450 * Verifies that the EEPROM has a valid checksum 451 * 452 * hw - Struct containing variables accessed by shared code 453 * 454 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 455 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 456 * valid. 457 *****************************************************************************/ 458 static int 459 e1000_validate_eeprom_checksum(struct eth_device *nic) 460 { 461 struct e1000_hw *hw = nic->priv; 462 uint16_t checksum = 0; 463 uint16_t i, eeprom_data; 464 465 DEBUGFUNC(); 466 467 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 468 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { 469 DEBUGOUT("EEPROM Read Error\n"); 470 return -E1000_ERR_EEPROM; 471 } 472 checksum += eeprom_data; 473 } 474 475 if (checksum == (uint16_t) EEPROM_SUM) { 476 return 0; 477 } else { 478 DEBUGOUT("EEPROM Checksum Invalid\n"); 479 return -E1000_ERR_EEPROM; 480 } 481 } 482 #endif /* #ifndef CONFIG_AP1000 */ 483 484 /****************************************************************************** 485 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 486 * second function of dual function devices 487 * 488 * nic - Struct containing variables accessed by shared code 489 *****************************************************************************/ 490 static int 491 e1000_read_mac_addr(struct eth_device *nic) 492 { 493 #ifndef CONFIG_AP1000 494 struct e1000_hw *hw = nic->priv; 495 uint16_t offset; 496 uint16_t eeprom_data; 497 int i; 498 499 DEBUGFUNC(); 500 501 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 502 offset = i >> 1; 503 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { 504 DEBUGOUT("EEPROM Read Error\n"); 505 return -E1000_ERR_EEPROM; 506 } 507 nic->enetaddr[i] = eeprom_data & 0xff; 508 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 509 } 510 if ((hw->mac_type == e1000_82546) && 511 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 512 /* Invert the last bit if this is the second device */ 513 nic->enetaddr[5] += 1; 514 } 515 #ifdef CONFIG_E1000_FALLBACK_MAC 516 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) 517 for ( i=0; i < NODE_ADDRESS_SIZE; i++ ) 518 nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff; 519 #endif 520 #else 521 /* 522 * The AP1000's e1000 has no eeprom; the MAC address is stored in the 523 * environment variables. Currently this does not support the addition 524 * of a PMC e1000 card, which is certainly a possibility, so this should 525 * be updated to properly use the env variable only for the onboard e1000 526 */ 527 528 int ii; 529 char *s, *e; 530 531 DEBUGFUNC(); 532 533 s = getenv ("ethaddr"); 534 if (s == NULL){ 535 return -E1000_ERR_EEPROM; 536 } 537 else{ 538 for(ii = 0; ii < 6; ii++) { 539 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; 540 if (s){ 541 s = (*e) ? e + 1 : e; 542 } 543 } 544 } 545 #endif 546 return 0; 547 } 548 549 /****************************************************************************** 550 * Initializes receive address filters. 551 * 552 * hw - Struct containing variables accessed by shared code 553 * 554 * Places the MAC address in receive address register 0 and clears the rest 555 * of the receive addresss registers. Clears the multicast table. Assumes 556 * the receiver is in reset when the routine is called. 557 *****************************************************************************/ 558 static void 559 e1000_init_rx_addrs(struct eth_device *nic) 560 { 561 struct e1000_hw *hw = nic->priv; 562 uint32_t i; 563 uint32_t addr_low; 564 uint32_t addr_high; 565 566 DEBUGFUNC(); 567 568 /* Setup the receive address. */ 569 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 570 addr_low = (nic->enetaddr[0] | 571 (nic->enetaddr[1] << 8) | 572 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); 573 574 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); 575 576 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 577 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 578 579 /* Zero out the other 15 receive addresses. */ 580 DEBUGOUT("Clearing RAR[1-15]\n"); 581 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 582 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 583 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 584 } 585 } 586 587 /****************************************************************************** 588 * Clears the VLAN filer table 589 * 590 * hw - Struct containing variables accessed by shared code 591 *****************************************************************************/ 592 static void 593 e1000_clear_vfta(struct e1000_hw *hw) 594 { 595 uint32_t offset; 596 597 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 598 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 599 } 600 601 /****************************************************************************** 602 * Set the mac type member in the hw struct. 603 * 604 * hw - Struct containing variables accessed by shared code 605 *****************************************************************************/ 606 static int 607 e1000_set_mac_type(struct e1000_hw *hw) 608 { 609 DEBUGFUNC(); 610 611 switch (hw->device_id) { 612 case E1000_DEV_ID_82542: 613 switch (hw->revision_id) { 614 case E1000_82542_2_0_REV_ID: 615 hw->mac_type = e1000_82542_rev2_0; 616 break; 617 case E1000_82542_2_1_REV_ID: 618 hw->mac_type = e1000_82542_rev2_1; 619 break; 620 default: 621 /* Invalid 82542 revision ID */ 622 return -E1000_ERR_MAC_TYPE; 623 } 624 break; 625 case E1000_DEV_ID_82543GC_FIBER: 626 case E1000_DEV_ID_82543GC_COPPER: 627 hw->mac_type = e1000_82543; 628 break; 629 case E1000_DEV_ID_82544EI_COPPER: 630 case E1000_DEV_ID_82544EI_FIBER: 631 case E1000_DEV_ID_82544GC_COPPER: 632 case E1000_DEV_ID_82544GC_LOM: 633 hw->mac_type = e1000_82544; 634 break; 635 case E1000_DEV_ID_82540EM: 636 case E1000_DEV_ID_82540EM_LOM: 637 hw->mac_type = e1000_82540; 638 break; 639 case E1000_DEV_ID_82545EM_COPPER: 640 case E1000_DEV_ID_82545GM_COPPER: 641 case E1000_DEV_ID_82545EM_FIBER: 642 hw->mac_type = e1000_82545; 643 break; 644 case E1000_DEV_ID_82546EB_COPPER: 645 case E1000_DEV_ID_82546EB_FIBER: 646 hw->mac_type = e1000_82546; 647 break; 648 case E1000_DEV_ID_82541ER: 649 case E1000_DEV_ID_82541GI_LF: 650 hw->mac_type = e1000_82541_rev_2; 651 break; 652 default: 653 /* Should never have loaded on this device */ 654 return -E1000_ERR_MAC_TYPE; 655 } 656 return E1000_SUCCESS; 657 } 658 659 /****************************************************************************** 660 * Reset the transmit and receive units; mask and clear all interrupts. 661 * 662 * hw - Struct containing variables accessed by shared code 663 *****************************************************************************/ 664 void 665 e1000_reset_hw(struct e1000_hw *hw) 666 { 667 uint32_t ctrl; 668 uint32_t ctrl_ext; 669 uint32_t icr; 670 uint32_t manc; 671 672 DEBUGFUNC(); 673 674 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 675 if (hw->mac_type == e1000_82542_rev2_0) { 676 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 677 pci_write_config_word(hw->pdev, PCI_COMMAND, 678 hw-> 679 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 680 } 681 682 /* Clear interrupt mask to stop board from generating interrupts */ 683 DEBUGOUT("Masking off all interrupts\n"); 684 E1000_WRITE_REG(hw, IMC, 0xffffffff); 685 686 /* Disable the Transmit and Receive units. Then delay to allow 687 * any pending transactions to complete before we hit the MAC with 688 * the global reset. 689 */ 690 E1000_WRITE_REG(hw, RCTL, 0); 691 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 692 E1000_WRITE_FLUSH(hw); 693 694 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 695 hw->tbi_compatibility_on = FALSE; 696 697 /* Delay to allow any outstanding PCI transactions to complete before 698 * resetting the device 699 */ 700 mdelay(10); 701 702 /* Issue a global reset to the MAC. This will reset the chip's 703 * transmit, receive, DMA, and link units. It will not effect 704 * the current PCI configuration. The global reset bit is self- 705 * clearing, and should clear within a microsecond. 706 */ 707 DEBUGOUT("Issuing a global reset to MAC\n"); 708 ctrl = E1000_READ_REG(hw, CTRL); 709 710 #if 0 711 if (hw->mac_type > e1000_82543) 712 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 713 else 714 #endif 715 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 716 717 /* Force a reload from the EEPROM if necessary */ 718 if (hw->mac_type < e1000_82540) { 719 /* Wait for reset to complete */ 720 udelay(10); 721 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 722 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 723 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 724 E1000_WRITE_FLUSH(hw); 725 /* Wait for EEPROM reload */ 726 mdelay(2); 727 } else { 728 /* Wait for EEPROM reload (it happens automatically) */ 729 mdelay(4); 730 /* Dissable HW ARPs on ASF enabled adapters */ 731 manc = E1000_READ_REG(hw, MANC); 732 manc &= ~(E1000_MANC_ARP_EN); 733 E1000_WRITE_REG(hw, MANC, manc); 734 } 735 736 /* Clear interrupt mask to stop board from generating interrupts */ 737 DEBUGOUT("Masking off all interrupts\n"); 738 E1000_WRITE_REG(hw, IMC, 0xffffffff); 739 740 /* Clear any pending interrupt events. */ 741 icr = E1000_READ_REG(hw, ICR); 742 743 /* If MWI was previously enabled, reenable it. */ 744 if (hw->mac_type == e1000_82542_rev2_0) { 745 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 746 } 747 } 748 749 /****************************************************************************** 750 * Performs basic configuration of the adapter. 751 * 752 * hw - Struct containing variables accessed by shared code 753 * 754 * Assumes that the controller has previously been reset and is in a 755 * post-reset uninitialized state. Initializes the receive address registers, 756 * multicast table, and VLAN filter table. Calls routines to setup link 757 * configuration and flow control settings. Clears all on-chip counters. Leaves 758 * the transmit and receive units disabled and uninitialized. 759 *****************************************************************************/ 760 static int 761 e1000_init_hw(struct eth_device *nic) 762 { 763 struct e1000_hw *hw = nic->priv; 764 uint32_t ctrl, status; 765 uint32_t i; 766 int32_t ret_val; 767 uint16_t pcix_cmd_word; 768 uint16_t pcix_stat_hi_word; 769 uint16_t cmd_mmrbc; 770 uint16_t stat_mmrbc; 771 e1000_bus_type bus_type = e1000_bus_type_unknown; 772 773 DEBUGFUNC(); 774 #if 0 775 /* Initialize Identification LED */ 776 ret_val = e1000_id_led_init(hw); 777 if (ret_val < 0) { 778 DEBUGOUT("Error Initializing Identification LED\n"); 779 return ret_val; 780 } 781 #endif 782 /* Set the Media Type and exit with error if it is not valid. */ 783 if (hw->mac_type != e1000_82543) { 784 /* tbi_compatibility is only valid on 82543 */ 785 hw->tbi_compatibility_en = FALSE; 786 } 787 788 if (hw->mac_type >= e1000_82543) { 789 status = E1000_READ_REG(hw, STATUS); 790 if (status & E1000_STATUS_TBIMODE) { 791 hw->media_type = e1000_media_type_fiber; 792 /* tbi_compatibility not valid on fiber */ 793 hw->tbi_compatibility_en = FALSE; 794 } else { 795 hw->media_type = e1000_media_type_copper; 796 } 797 } else { 798 /* This is an 82542 (fiber only) */ 799 hw->media_type = e1000_media_type_fiber; 800 } 801 802 /* Disabling VLAN filtering. */ 803 DEBUGOUT("Initializing the IEEE VLAN\n"); 804 E1000_WRITE_REG(hw, VET, 0); 805 806 e1000_clear_vfta(hw); 807 808 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 809 if (hw->mac_type == e1000_82542_rev2_0) { 810 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 811 pci_write_config_word(hw->pdev, PCI_COMMAND, 812 hw-> 813 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 814 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 815 E1000_WRITE_FLUSH(hw); 816 mdelay(5); 817 } 818 819 /* Setup the receive address. This involves initializing all of the Receive 820 * Address Registers (RARs 0 - 15). 821 */ 822 e1000_init_rx_addrs(nic); 823 824 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 825 if (hw->mac_type == e1000_82542_rev2_0) { 826 E1000_WRITE_REG(hw, RCTL, 0); 827 E1000_WRITE_FLUSH(hw); 828 mdelay(1); 829 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 830 } 831 832 /* Zero out the Multicast HASH table */ 833 DEBUGOUT("Zeroing the MTA\n"); 834 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 835 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 836 837 #if 0 838 /* Set the PCI priority bit correctly in the CTRL register. This 839 * determines if the adapter gives priority to receives, or if it 840 * gives equal priority to transmits and receives. 841 */ 842 if (hw->dma_fairness) { 843 ctrl = E1000_READ_REG(hw, CTRL); 844 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 845 } 846 #endif 847 if (hw->mac_type >= e1000_82543) { 848 status = E1000_READ_REG(hw, STATUS); 849 bus_type = (status & E1000_STATUS_PCIX_MODE) ? 850 e1000_bus_type_pcix : e1000_bus_type_pci; 851 } 852 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 853 if (bus_type == e1000_bus_type_pcix) { 854 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 855 &pcix_cmd_word); 856 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, 857 &pcix_stat_hi_word); 858 cmd_mmrbc = 859 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 860 PCIX_COMMAND_MMRBC_SHIFT; 861 stat_mmrbc = 862 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 863 PCIX_STATUS_HI_MMRBC_SHIFT; 864 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 865 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 866 if (cmd_mmrbc > stat_mmrbc) { 867 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 868 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 869 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, 870 pcix_cmd_word); 871 } 872 } 873 874 /* Call a subroutine to configure the link and setup flow control. */ 875 ret_val = e1000_setup_link(nic); 876 877 /* Set the transmit descriptor write-back policy */ 878 if (hw->mac_type > e1000_82544) { 879 ctrl = E1000_READ_REG(hw, TXDCTL); 880 ctrl = 881 (ctrl & ~E1000_TXDCTL_WTHRESH) | 882 E1000_TXDCTL_FULL_TX_DESC_WB; 883 E1000_WRITE_REG(hw, TXDCTL, ctrl); 884 } 885 #if 0 886 /* Clear all of the statistics registers (clear on read). It is 887 * important that we do this after we have tried to establish link 888 * because the symbol error count will increment wildly if there 889 * is no link. 890 */ 891 e1000_clear_hw_cntrs(hw); 892 #endif 893 894 return ret_val; 895 } 896 897 /****************************************************************************** 898 * Configures flow control and link settings. 899 * 900 * hw - Struct containing variables accessed by shared code 901 * 902 * Determines which flow control settings to use. Calls the apropriate media- 903 * specific link configuration function. Configures the flow control settings. 904 * Assuming the adapter has a valid link partner, a valid link should be 905 * established. Assumes the hardware has previously been reset and the 906 * transmitter and receiver are not enabled. 907 *****************************************************************************/ 908 static int 909 e1000_setup_link(struct eth_device *nic) 910 { 911 struct e1000_hw *hw = nic->priv; 912 uint32_t ctrl_ext; 913 int32_t ret_val; 914 uint16_t eeprom_data; 915 916 DEBUGFUNC(); 917 918 #ifndef CONFIG_AP1000 919 /* Read and store word 0x0F of the EEPROM. This word contains bits 920 * that determine the hardware's default PAUSE (flow control) mode, 921 * a bit that determines whether the HW defaults to enabling or 922 * disabling auto-negotiation, and the direction of the 923 * SW defined pins. If there is no SW over-ride of the flow 924 * control setting, then the variable hw->fc will 925 * be initialized based on a value in the EEPROM. 926 */ 927 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { 928 DEBUGOUT("EEPROM Read Error\n"); 929 return -E1000_ERR_EEPROM; 930 } 931 #else 932 /* we have to hardcode the proper value for our hardware. */ 933 /* this value is for the 82540EM pci card used for prototyping, and it works. */ 934 eeprom_data = 0xb220; 935 #endif 936 937 if (hw->fc == e1000_fc_default) { 938 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 939 hw->fc = e1000_fc_none; 940 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 941 EEPROM_WORD0F_ASM_DIR) 942 hw->fc = e1000_fc_tx_pause; 943 else 944 hw->fc = e1000_fc_full; 945 } 946 947 /* We want to save off the original Flow Control configuration just 948 * in case we get disconnected and then reconnected into a different 949 * hub or switch with different Flow Control capabilities. 950 */ 951 if (hw->mac_type == e1000_82542_rev2_0) 952 hw->fc &= (~e1000_fc_tx_pause); 953 954 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 955 hw->fc &= (~e1000_fc_rx_pause); 956 957 hw->original_fc = hw->fc; 958 959 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 960 961 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 962 * polarity value for the SW controlled pins, and setup the 963 * Extended Device Control reg with that info. 964 * This is needed because one of the SW controlled pins is used for 965 * signal detection. So this should be done before e1000_setup_pcs_link() 966 * or e1000_phy_setup() is called. 967 */ 968 if (hw->mac_type == e1000_82543) { 969 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 970 SWDPIO__EXT_SHIFT); 971 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 972 } 973 974 /* Call the necessary subroutine to configure the link. */ 975 ret_val = (hw->media_type == e1000_media_type_fiber) ? 976 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); 977 if (ret_val < 0) { 978 return ret_val; 979 } 980 981 /* Initialize the flow control address, type, and PAUSE timer 982 * registers to their default values. This is done even if flow 983 * control is disabled, because it does not hurt anything to 984 * initialize these registers. 985 */ 986 DEBUGOUT 987 ("Initializing the Flow Control address, type and timer regs\n"); 988 989 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 990 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 991 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 992 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 993 994 /* Set the flow control receive threshold registers. Normally, 995 * these registers will be set to a default threshold that may be 996 * adjusted later by the driver's runtime code. However, if the 997 * ability to transmit pause frames in not enabled, then these 998 * registers will be set to 0. 999 */ 1000 if (!(hw->fc & e1000_fc_tx_pause)) { 1001 E1000_WRITE_REG(hw, FCRTL, 0); 1002 E1000_WRITE_REG(hw, FCRTH, 0); 1003 } else { 1004 /* We need to set up the Receive Threshold high and low water marks 1005 * as well as (optionally) enabling the transmission of XON frames. 1006 */ 1007 if (hw->fc_send_xon) { 1008 E1000_WRITE_REG(hw, FCRTL, 1009 (hw->fc_low_water | E1000_FCRTL_XONE)); 1010 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1011 } else { 1012 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1013 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1014 } 1015 } 1016 return ret_val; 1017 } 1018 1019 /****************************************************************************** 1020 * Sets up link for a fiber based adapter 1021 * 1022 * hw - Struct containing variables accessed by shared code 1023 * 1024 * Manipulates Physical Coding Sublayer functions in order to configure 1025 * link. Assumes the hardware has been previously reset and the transmitter 1026 * and receiver are not enabled. 1027 *****************************************************************************/ 1028 static int 1029 e1000_setup_fiber_link(struct eth_device *nic) 1030 { 1031 struct e1000_hw *hw = nic->priv; 1032 uint32_t ctrl; 1033 uint32_t status; 1034 uint32_t txcw = 0; 1035 uint32_t i; 1036 uint32_t signal; 1037 int32_t ret_val; 1038 1039 DEBUGFUNC(); 1040 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1041 * set when the optics detect a signal. On older adapters, it will be 1042 * cleared when there is a signal 1043 */ 1044 ctrl = E1000_READ_REG(hw, CTRL); 1045 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1046 signal = E1000_CTRL_SWDPIN1; 1047 else 1048 signal = 0; 1049 1050 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, 1051 ctrl); 1052 /* Take the link out of reset */ 1053 ctrl &= ~(E1000_CTRL_LRST); 1054 1055 e1000_config_collision_dist(hw); 1056 1057 /* Check for a software override of the flow control settings, and setup 1058 * the device accordingly. If auto-negotiation is enabled, then software 1059 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1060 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1061 * auto-negotiation is disabled, then software will have to manually 1062 * configure the two flow control enable bits in the CTRL register. 1063 * 1064 * The possible values of the "fc" parameter are: 1065 * 0: Flow control is completely disabled 1066 * 1: Rx flow control is enabled (we can receive pause frames, but 1067 * not send pause frames). 1068 * 2: Tx flow control is enabled (we can send pause frames but we do 1069 * not support receiving pause frames). 1070 * 3: Both Rx and TX flow control (symmetric) are enabled. 1071 */ 1072 switch (hw->fc) { 1073 case e1000_fc_none: 1074 /* Flow control is completely disabled by a software over-ride. */ 1075 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1076 break; 1077 case e1000_fc_rx_pause: 1078 /* RX Flow control is enabled and TX Flow control is disabled by a 1079 * software over-ride. Since there really isn't a way to advertise 1080 * that we are capable of RX Pause ONLY, we will advertise that we 1081 * support both symmetric and asymmetric RX PAUSE. Later, we will 1082 * disable the adapter's ability to send PAUSE frames. 1083 */ 1084 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1085 break; 1086 case e1000_fc_tx_pause: 1087 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1088 * software over-ride. 1089 */ 1090 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1091 break; 1092 case e1000_fc_full: 1093 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1094 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1095 break; 1096 default: 1097 DEBUGOUT("Flow control param set incorrectly\n"); 1098 return -E1000_ERR_CONFIG; 1099 break; 1100 } 1101 1102 /* Since auto-negotiation is enabled, take the link out of reset (the link 1103 * will be in reset, because we previously reset the chip). This will 1104 * restart auto-negotiation. If auto-neogtiation is successful then the 1105 * link-up status bit will be set and the flow control enable bits (RFCE 1106 * and TFCE) will be set according to their negotiated value. 1107 */ 1108 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 1109 1110 E1000_WRITE_REG(hw, TXCW, txcw); 1111 E1000_WRITE_REG(hw, CTRL, ctrl); 1112 E1000_WRITE_FLUSH(hw); 1113 1114 hw->txcw = txcw; 1115 mdelay(1); 1116 1117 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1118 * indication in the Device Status Register. Time-out if a link isn't 1119 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1120 * less than 500 milliseconds even if the other end is doing it in SW). 1121 */ 1122 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1123 DEBUGOUT("Looking for Link\n"); 1124 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1125 mdelay(10); 1126 status = E1000_READ_REG(hw, STATUS); 1127 if (status & E1000_STATUS_LU) 1128 break; 1129 } 1130 if (i == (LINK_UP_TIMEOUT / 10)) { 1131 /* AutoNeg failed to achieve a link, so we'll call 1132 * e1000_check_for_link. This routine will force the link up if we 1133 * detect a signal. This will allow us to communicate with 1134 * non-autonegotiating link partners. 1135 */ 1136 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1137 hw->autoneg_failed = 1; 1138 ret_val = e1000_check_for_link(nic); 1139 if (ret_val < 0) { 1140 DEBUGOUT("Error while checking for link\n"); 1141 return ret_val; 1142 } 1143 hw->autoneg_failed = 0; 1144 } else { 1145 hw->autoneg_failed = 0; 1146 DEBUGOUT("Valid Link Found\n"); 1147 } 1148 } else { 1149 DEBUGOUT("No Signal Detected\n"); 1150 return -E1000_ERR_NOLINK; 1151 } 1152 return 0; 1153 } 1154 1155 /****************************************************************************** 1156 * Detects which PHY is present and the speed and duplex 1157 * 1158 * hw - Struct containing variables accessed by shared code 1159 ******************************************************************************/ 1160 static int 1161 e1000_setup_copper_link(struct eth_device *nic) 1162 { 1163 struct e1000_hw *hw = nic->priv; 1164 uint32_t ctrl; 1165 int32_t ret_val; 1166 uint16_t i; 1167 uint16_t phy_data; 1168 1169 DEBUGFUNC(); 1170 1171 ctrl = E1000_READ_REG(hw, CTRL); 1172 /* With 82543, we need to force speed and duplex on the MAC equal to what 1173 * the PHY speed and duplex configuration is. In addition, we need to 1174 * perform a hardware reset on the PHY to take it out of reset. 1175 */ 1176 if (hw->mac_type > e1000_82543) { 1177 ctrl |= E1000_CTRL_SLU; 1178 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1179 E1000_WRITE_REG(hw, CTRL, ctrl); 1180 } else { 1181 ctrl |= 1182 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1183 E1000_WRITE_REG(hw, CTRL, ctrl); 1184 e1000_phy_hw_reset(hw); 1185 } 1186 1187 /* Make sure we have a valid PHY */ 1188 ret_val = e1000_detect_gig_phy(hw); 1189 if (ret_val < 0) { 1190 DEBUGOUT("Error, did not detect valid phy.\n"); 1191 return ret_val; 1192 } 1193 DEBUGOUT("Phy ID = %x \n", hw->phy_id); 1194 1195 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1196 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1197 DEBUGOUT("PHY Read Error\n"); 1198 return -E1000_ERR_PHY; 1199 } 1200 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1201 1202 #if 0 1203 /* Options: 1204 * MDI/MDI-X = 0 (default) 1205 * 0 - Auto for all speeds 1206 * 1 - MDI mode 1207 * 2 - MDI-X mode 1208 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1209 */ 1210 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1211 switch (hw->mdix) { 1212 case 1: 1213 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1214 break; 1215 case 2: 1216 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1217 break; 1218 case 3: 1219 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1220 break; 1221 case 0: 1222 default: 1223 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1224 break; 1225 } 1226 #else 1227 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1228 #endif 1229 1230 #if 0 1231 /* Options: 1232 * disable_polarity_correction = 0 (default) 1233 * Automatic Correction for Reversed Cable Polarity 1234 * 0 - Disabled 1235 * 1 - Enabled 1236 */ 1237 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1238 if (hw->disable_polarity_correction == 1) 1239 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1240 #else 1241 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1242 #endif 1243 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1244 DEBUGOUT("PHY Write Error\n"); 1245 return -E1000_ERR_PHY; 1246 } 1247 1248 /* Force TX_CLK in the Extended PHY Specific Control Register 1249 * to 25MHz clock. 1250 */ 1251 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 1252 DEBUGOUT("PHY Read Error\n"); 1253 return -E1000_ERR_PHY; 1254 } 1255 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1256 /* Configure Master and Slave downshift values */ 1257 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1258 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1259 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1260 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1261 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { 1262 DEBUGOUT("PHY Write Error\n"); 1263 return -E1000_ERR_PHY; 1264 } 1265 1266 /* SW Reset the PHY so all changes take effect */ 1267 ret_val = e1000_phy_reset(hw); 1268 if (ret_val < 0) { 1269 DEBUGOUT("Error Resetting the PHY\n"); 1270 return ret_val; 1271 } 1272 1273 /* Options: 1274 * autoneg = 1 (default) 1275 * PHY will advertise value(s) parsed from 1276 * autoneg_advertised and fc 1277 * autoneg = 0 1278 * PHY will be set to 10H, 10F, 100H, or 100F 1279 * depending on value parsed from forced_speed_duplex. 1280 */ 1281 1282 /* Is autoneg enabled? This is enabled by default or by software override. 1283 * If so, call e1000_phy_setup_autoneg routine to parse the 1284 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the 1285 * user should have provided a speed/duplex override. If so, then call 1286 * e1000_phy_force_speed_duplex to parse and set this up. 1287 */ 1288 /* Perform some bounds checking on the hw->autoneg_advertised 1289 * parameter. If this variable is zero, then set it to the default. 1290 */ 1291 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1292 1293 /* If autoneg_advertised is zero, we assume it was not defaulted 1294 * by the calling code so we set to advertise full capability. 1295 */ 1296 if (hw->autoneg_advertised == 0) 1297 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1298 1299 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1300 ret_val = e1000_phy_setup_autoneg(hw); 1301 if (ret_val < 0) { 1302 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1303 return ret_val; 1304 } 1305 DEBUGOUT("Restarting Auto-Neg\n"); 1306 1307 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1308 * the Auto Neg Restart bit in the PHY control register. 1309 */ 1310 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 1311 DEBUGOUT("PHY Read Error\n"); 1312 return -E1000_ERR_PHY; 1313 } 1314 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1315 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 1316 DEBUGOUT("PHY Write Error\n"); 1317 return -E1000_ERR_PHY; 1318 } 1319 #if 0 1320 /* Does the user want to wait for Auto-Neg to complete here, or 1321 * check at a later time (for example, callback routine). 1322 */ 1323 if (hw->wait_autoneg_complete) { 1324 ret_val = e1000_wait_autoneg(hw); 1325 if (ret_val < 0) { 1326 DEBUGOUT 1327 ("Error while waiting for autoneg to complete\n"); 1328 return ret_val; 1329 } 1330 } 1331 #else 1332 /* If we do not wait for autonegtation to complete I 1333 * do not see a valid link status. 1334 */ 1335 ret_val = e1000_wait_autoneg(hw); 1336 if (ret_val < 0) { 1337 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1338 return ret_val; 1339 } 1340 #endif 1341 1342 /* Check link status. Wait up to 100 microseconds for link to become 1343 * valid. 1344 */ 1345 for (i = 0; i < 10; i++) { 1346 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1347 DEBUGOUT("PHY Read Error\n"); 1348 return -E1000_ERR_PHY; 1349 } 1350 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1351 DEBUGOUT("PHY Read Error\n"); 1352 return -E1000_ERR_PHY; 1353 } 1354 if (phy_data & MII_SR_LINK_STATUS) { 1355 /* We have link, so we need to finish the config process: 1356 * 1) Set up the MAC to the current PHY speed/duplex 1357 * if we are on 82543. If we 1358 * are on newer silicon, we only need to configure 1359 * collision distance in the Transmit Control Register. 1360 * 2) Set up flow control on the MAC to that established with 1361 * the link partner. 1362 */ 1363 if (hw->mac_type >= e1000_82544) { 1364 e1000_config_collision_dist(hw); 1365 } else { 1366 ret_val = e1000_config_mac_to_phy(hw); 1367 if (ret_val < 0) { 1368 DEBUGOUT 1369 ("Error configuring MAC to PHY settings\n"); 1370 return ret_val; 1371 } 1372 } 1373 ret_val = e1000_config_fc_after_link_up(hw); 1374 if (ret_val < 0) { 1375 DEBUGOUT("Error Configuring Flow Control\n"); 1376 return ret_val; 1377 } 1378 DEBUGOUT("Valid link established!!!\n"); 1379 return 0; 1380 } 1381 udelay(10); 1382 } 1383 1384 DEBUGOUT("Unable to establish link!!!\n"); 1385 return -E1000_ERR_NOLINK; 1386 } 1387 1388 /****************************************************************************** 1389 * Configures PHY autoneg and flow control advertisement settings 1390 * 1391 * hw - Struct containing variables accessed by shared code 1392 ******************************************************************************/ 1393 static int 1394 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1395 { 1396 uint16_t mii_autoneg_adv_reg; 1397 uint16_t mii_1000t_ctrl_reg; 1398 1399 DEBUGFUNC(); 1400 1401 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1402 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { 1403 DEBUGOUT("PHY Read Error\n"); 1404 return -E1000_ERR_PHY; 1405 } 1406 1407 /* Read the MII 1000Base-T Control Register (Address 9). */ 1408 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { 1409 DEBUGOUT("PHY Read Error\n"); 1410 return -E1000_ERR_PHY; 1411 } 1412 1413 /* Need to parse both autoneg_advertised and fc and set up 1414 * the appropriate PHY registers. First we will parse for 1415 * autoneg_advertised software override. Since we can advertise 1416 * a plethora of combinations, we need to check each bit 1417 * individually. 1418 */ 1419 1420 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1421 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1422 * the 1000Base-T Control Register (Address 9). 1423 */ 1424 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1425 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1426 1427 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 1428 1429 /* Do we want to advertise 10 Mb Half Duplex? */ 1430 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1431 DEBUGOUT("Advertise 10mb Half duplex\n"); 1432 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1433 } 1434 1435 /* Do we want to advertise 10 Mb Full Duplex? */ 1436 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1437 DEBUGOUT("Advertise 10mb Full duplex\n"); 1438 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1439 } 1440 1441 /* Do we want to advertise 100 Mb Half Duplex? */ 1442 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1443 DEBUGOUT("Advertise 100mb Half duplex\n"); 1444 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1445 } 1446 1447 /* Do we want to advertise 100 Mb Full Duplex? */ 1448 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1449 DEBUGOUT("Advertise 100mb Full duplex\n"); 1450 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1451 } 1452 1453 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1454 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1455 DEBUGOUT 1456 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1457 } 1458 1459 /* Do we want to advertise 1000 Mb Full Duplex? */ 1460 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1461 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1462 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1463 } 1464 1465 /* Check for a software override of the flow control settings, and 1466 * setup the PHY advertisement registers accordingly. If 1467 * auto-negotiation is enabled, then software will have to set the 1468 * "PAUSE" bits to the correct value in the Auto-Negotiation 1469 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1470 * 1471 * The possible values of the "fc" parameter are: 1472 * 0: Flow control is completely disabled 1473 * 1: Rx flow control is enabled (we can receive pause frames 1474 * but not send pause frames). 1475 * 2: Tx flow control is enabled (we can send pause frames 1476 * but we do not support receiving pause frames). 1477 * 3: Both Rx and TX flow control (symmetric) are enabled. 1478 * other: No software override. The flow control configuration 1479 * in the EEPROM is used. 1480 */ 1481 switch (hw->fc) { 1482 case e1000_fc_none: /* 0 */ 1483 /* Flow control (RX & TX) is completely disabled by a 1484 * software over-ride. 1485 */ 1486 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1487 break; 1488 case e1000_fc_rx_pause: /* 1 */ 1489 /* RX Flow control is enabled, and TX Flow control is 1490 * disabled, by a software over-ride. 1491 */ 1492 /* Since there really isn't a way to advertise that we are 1493 * capable of RX Pause ONLY, we will advertise that we 1494 * support both symmetric and asymmetric RX PAUSE. Later 1495 * (in e1000_config_fc_after_link_up) we will disable the 1496 *hw's ability to send PAUSE frames. 1497 */ 1498 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1499 break; 1500 case e1000_fc_tx_pause: /* 2 */ 1501 /* TX Flow control is enabled, and RX Flow control is 1502 * disabled, by a software over-ride. 1503 */ 1504 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1505 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1506 break; 1507 case e1000_fc_full: /* 3 */ 1508 /* Flow control (both RX and TX) is enabled by a software 1509 * over-ride. 1510 */ 1511 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1512 break; 1513 default: 1514 DEBUGOUT("Flow control param set incorrectly\n"); 1515 return -E1000_ERR_CONFIG; 1516 } 1517 1518 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { 1519 DEBUGOUT("PHY Write Error\n"); 1520 return -E1000_ERR_PHY; 1521 } 1522 1523 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1524 1525 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { 1526 DEBUGOUT("PHY Write Error\n"); 1527 return -E1000_ERR_PHY; 1528 } 1529 return 0; 1530 } 1531 1532 /****************************************************************************** 1533 * Sets the collision distance in the Transmit Control register 1534 * 1535 * hw - Struct containing variables accessed by shared code 1536 * 1537 * Link should have been established previously. Reads the speed and duplex 1538 * information from the Device Status register. 1539 ******************************************************************************/ 1540 static void 1541 e1000_config_collision_dist(struct e1000_hw *hw) 1542 { 1543 uint32_t tctl; 1544 1545 tctl = E1000_READ_REG(hw, TCTL); 1546 1547 tctl &= ~E1000_TCTL_COLD; 1548 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1549 1550 E1000_WRITE_REG(hw, TCTL, tctl); 1551 E1000_WRITE_FLUSH(hw); 1552 } 1553 1554 /****************************************************************************** 1555 * Sets MAC speed and duplex settings to reflect the those in the PHY 1556 * 1557 * hw - Struct containing variables accessed by shared code 1558 * mii_reg - data to write to the MII control register 1559 * 1560 * The contents of the PHY register containing the needed information need to 1561 * be passed in. 1562 ******************************************************************************/ 1563 static int 1564 e1000_config_mac_to_phy(struct e1000_hw *hw) 1565 { 1566 uint32_t ctrl; 1567 uint16_t phy_data; 1568 1569 DEBUGFUNC(); 1570 1571 /* Read the Device Control Register and set the bits to Force Speed 1572 * and Duplex. 1573 */ 1574 ctrl = E1000_READ_REG(hw, CTRL); 1575 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1576 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1577 1578 /* Set up duplex in the Device Control and Transmit Control 1579 * registers depending on negotiated values. 1580 */ 1581 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 1582 DEBUGOUT("PHY Read Error\n"); 1583 return -E1000_ERR_PHY; 1584 } 1585 if (phy_data & M88E1000_PSSR_DPLX) 1586 ctrl |= E1000_CTRL_FD; 1587 else 1588 ctrl &= ~E1000_CTRL_FD; 1589 1590 e1000_config_collision_dist(hw); 1591 1592 /* Set up speed in the Device Control register depending on 1593 * negotiated values. 1594 */ 1595 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1596 ctrl |= E1000_CTRL_SPD_1000; 1597 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1598 ctrl |= E1000_CTRL_SPD_100; 1599 /* Write the configured values back to the Device Control Reg. */ 1600 E1000_WRITE_REG(hw, CTRL, ctrl); 1601 return 0; 1602 } 1603 1604 /****************************************************************************** 1605 * Forces the MAC's flow control settings. 1606 * 1607 * hw - Struct containing variables accessed by shared code 1608 * 1609 * Sets the TFCE and RFCE bits in the device control register to reflect 1610 * the adapter settings. TFCE and RFCE need to be explicitly set by 1611 * software when a Copper PHY is used because autonegotiation is managed 1612 * by the PHY rather than the MAC. Software must also configure these 1613 * bits when link is forced on a fiber connection. 1614 *****************************************************************************/ 1615 static int 1616 e1000_force_mac_fc(struct e1000_hw *hw) 1617 { 1618 uint32_t ctrl; 1619 1620 DEBUGFUNC(); 1621 1622 /* Get the current configuration of the Device Control Register */ 1623 ctrl = E1000_READ_REG(hw, CTRL); 1624 1625 /* Because we didn't get link via the internal auto-negotiation 1626 * mechanism (we either forced link or we got link via PHY 1627 * auto-neg), we have to manually enable/disable transmit an 1628 * receive flow control. 1629 * 1630 * The "Case" statement below enables/disable flow control 1631 * according to the "hw->fc" parameter. 1632 * 1633 * The possible values of the "fc" parameter are: 1634 * 0: Flow control is completely disabled 1635 * 1: Rx flow control is enabled (we can receive pause 1636 * frames but not send pause frames). 1637 * 2: Tx flow control is enabled (we can send pause frames 1638 * frames but we do not receive pause frames). 1639 * 3: Both Rx and TX flow control (symmetric) is enabled. 1640 * other: No other values should be possible at this point. 1641 */ 1642 1643 switch (hw->fc) { 1644 case e1000_fc_none: 1645 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1646 break; 1647 case e1000_fc_rx_pause: 1648 ctrl &= (~E1000_CTRL_TFCE); 1649 ctrl |= E1000_CTRL_RFCE; 1650 break; 1651 case e1000_fc_tx_pause: 1652 ctrl &= (~E1000_CTRL_RFCE); 1653 ctrl |= E1000_CTRL_TFCE; 1654 break; 1655 case e1000_fc_full: 1656 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1657 break; 1658 default: 1659 DEBUGOUT("Flow control param set incorrectly\n"); 1660 return -E1000_ERR_CONFIG; 1661 } 1662 1663 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1664 if (hw->mac_type == e1000_82542_rev2_0) 1665 ctrl &= (~E1000_CTRL_TFCE); 1666 1667 E1000_WRITE_REG(hw, CTRL, ctrl); 1668 return 0; 1669 } 1670 1671 /****************************************************************************** 1672 * Configures flow control settings after link is established 1673 * 1674 * hw - Struct containing variables accessed by shared code 1675 * 1676 * Should be called immediately after a valid link has been established. 1677 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1678 * and autonegotiation is enabled, the MAC flow control settings will be set 1679 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1680 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1681 *****************************************************************************/ 1682 static int 1683 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1684 { 1685 int32_t ret_val; 1686 uint16_t mii_status_reg; 1687 uint16_t mii_nway_adv_reg; 1688 uint16_t mii_nway_lp_ability_reg; 1689 uint16_t speed; 1690 uint16_t duplex; 1691 1692 DEBUGFUNC(); 1693 1694 /* Check for the case where we have fiber media and auto-neg failed 1695 * so we had to force link. In this case, we need to force the 1696 * configuration of the MAC to match the "fc" parameter. 1697 */ 1698 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { 1699 ret_val = e1000_force_mac_fc(hw); 1700 if (ret_val < 0) { 1701 DEBUGOUT("Error forcing flow control settings\n"); 1702 return ret_val; 1703 } 1704 } 1705 1706 /* Check for the case where we have copper media and auto-neg is 1707 * enabled. In this case, we need to check and see if Auto-Neg 1708 * has completed, and if so, how the PHY and link partner has 1709 * flow control configured. 1710 */ 1711 if (hw->media_type == e1000_media_type_copper) { 1712 /* Read the MII Status Register and check to see if AutoNeg 1713 * has completed. We read this twice because this reg has 1714 * some "sticky" (latched) bits. 1715 */ 1716 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1717 DEBUGOUT("PHY Read Error \n"); 1718 return -E1000_ERR_PHY; 1719 } 1720 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1721 DEBUGOUT("PHY Read Error \n"); 1722 return -E1000_ERR_PHY; 1723 } 1724 1725 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 1726 /* The AutoNeg process has completed, so we now need to 1727 * read both the Auto Negotiation Advertisement Register 1728 * (Address 4) and the Auto_Negotiation Base Page Ability 1729 * Register (Address 5) to determine how flow control was 1730 * negotiated. 1731 */ 1732 if (e1000_read_phy_reg 1733 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 1734 DEBUGOUT("PHY Read Error\n"); 1735 return -E1000_ERR_PHY; 1736 } 1737 if (e1000_read_phy_reg 1738 (hw, PHY_LP_ABILITY, 1739 &mii_nway_lp_ability_reg) < 0) { 1740 DEBUGOUT("PHY Read Error\n"); 1741 return -E1000_ERR_PHY; 1742 } 1743 1744 /* Two bits in the Auto Negotiation Advertisement Register 1745 * (Address 4) and two bits in the Auto Negotiation Base 1746 * Page Ability Register (Address 5) determine flow control 1747 * for both the PHY and the link partner. The following 1748 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1749 * 1999, describes these PAUSE resolution bits and how flow 1750 * control is determined based upon these settings. 1751 * NOTE: DC = Don't Care 1752 * 1753 * LOCAL DEVICE | LINK PARTNER 1754 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1755 *-------|---------|-------|---------|-------------------- 1756 * 0 | 0 | DC | DC | e1000_fc_none 1757 * 0 | 1 | 0 | DC | e1000_fc_none 1758 * 0 | 1 | 1 | 0 | e1000_fc_none 1759 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1760 * 1 | 0 | 0 | DC | e1000_fc_none 1761 * 1 | DC | 1 | DC | e1000_fc_full 1762 * 1 | 1 | 0 | 0 | e1000_fc_none 1763 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1764 * 1765 */ 1766 /* Are both PAUSE bits set to 1? If so, this implies 1767 * Symmetric Flow Control is enabled at both ends. The 1768 * ASM_DIR bits are irrelevant per the spec. 1769 * 1770 * For Symmetric Flow Control: 1771 * 1772 * LOCAL DEVICE | LINK PARTNER 1773 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1774 *-------|---------|-------|---------|-------------------- 1775 * 1 | DC | 1 | DC | e1000_fc_full 1776 * 1777 */ 1778 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1779 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1780 /* Now we need to check if the user selected RX ONLY 1781 * of pause frames. In this case, we had to advertise 1782 * FULL flow control because we could not advertise RX 1783 * ONLY. Hence, we must now check to see if we need to 1784 * turn OFF the TRANSMISSION of PAUSE frames. 1785 */ 1786 if (hw->original_fc == e1000_fc_full) { 1787 hw->fc = e1000_fc_full; 1788 DEBUGOUT("Flow Control = FULL.\r\n"); 1789 } else { 1790 hw->fc = e1000_fc_rx_pause; 1791 DEBUGOUT 1792 ("Flow Control = RX PAUSE frames only.\r\n"); 1793 } 1794 } 1795 /* For receiving PAUSE frames ONLY. 1796 * 1797 * LOCAL DEVICE | LINK PARTNER 1798 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1799 *-------|---------|-------|---------|-------------------- 1800 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1801 * 1802 */ 1803 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1804 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1805 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1806 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1807 { 1808 hw->fc = e1000_fc_tx_pause; 1809 DEBUGOUT 1810 ("Flow Control = TX PAUSE frames only.\r\n"); 1811 } 1812 /* For transmitting PAUSE frames ONLY. 1813 * 1814 * LOCAL DEVICE | LINK PARTNER 1815 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1816 *-------|---------|-------|---------|-------------------- 1817 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1818 * 1819 */ 1820 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1821 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1822 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1823 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 1824 { 1825 hw->fc = e1000_fc_rx_pause; 1826 DEBUGOUT 1827 ("Flow Control = RX PAUSE frames only.\r\n"); 1828 } 1829 /* Per the IEEE spec, at this point flow control should be 1830 * disabled. However, we want to consider that we could 1831 * be connected to a legacy switch that doesn't advertise 1832 * desired flow control, but can be forced on the link 1833 * partner. So if we advertised no flow control, that is 1834 * what we will resolve to. If we advertised some kind of 1835 * receive capability (Rx Pause Only or Full Flow Control) 1836 * and the link partner advertised none, we will configure 1837 * ourselves to enable Rx Flow Control only. We can do 1838 * this safely for two reasons: If the link partner really 1839 * didn't want flow control enabled, and we enable Rx, no 1840 * harm done since we won't be receiving any PAUSE frames 1841 * anyway. If the intent on the link partner was to have 1842 * flow control enabled, then by us enabling RX only, we 1843 * can at least receive pause frames and process them. 1844 * This is a good idea because in most cases, since we are 1845 * predominantly a server NIC, more times than not we will 1846 * be asked to delay transmission of packets than asking 1847 * our link partner to pause transmission of frames. 1848 */ 1849 else if (hw->original_fc == e1000_fc_none || 1850 hw->original_fc == e1000_fc_tx_pause) { 1851 hw->fc = e1000_fc_none; 1852 DEBUGOUT("Flow Control = NONE.\r\n"); 1853 } else { 1854 hw->fc = e1000_fc_rx_pause; 1855 DEBUGOUT 1856 ("Flow Control = RX PAUSE frames only.\r\n"); 1857 } 1858 1859 /* Now we need to do one last check... If we auto- 1860 * negotiated to HALF DUPLEX, flow control should not be 1861 * enabled per IEEE 802.3 spec. 1862 */ 1863 e1000_get_speed_and_duplex(hw, &speed, &duplex); 1864 1865 if (duplex == HALF_DUPLEX) 1866 hw->fc = e1000_fc_none; 1867 1868 /* Now we call a subroutine to actually force the MAC 1869 * controller to use the correct flow control settings. 1870 */ 1871 ret_val = e1000_force_mac_fc(hw); 1872 if (ret_val < 0) { 1873 DEBUGOUT 1874 ("Error forcing flow control settings\n"); 1875 return ret_val; 1876 } 1877 } else { 1878 DEBUGOUT 1879 ("Copper PHY and Auto Neg has not completed.\r\n"); 1880 } 1881 } 1882 return 0; 1883 } 1884 1885 /****************************************************************************** 1886 * Checks to see if the link status of the hardware has changed. 1887 * 1888 * hw - Struct containing variables accessed by shared code 1889 * 1890 * Called by any function that needs to check the link status of the adapter. 1891 *****************************************************************************/ 1892 static int 1893 e1000_check_for_link(struct eth_device *nic) 1894 { 1895 struct e1000_hw *hw = nic->priv; 1896 uint32_t rxcw; 1897 uint32_t ctrl; 1898 uint32_t status; 1899 uint32_t rctl; 1900 uint32_t signal; 1901 int32_t ret_val; 1902 uint16_t phy_data; 1903 uint16_t lp_capability; 1904 1905 DEBUGFUNC(); 1906 1907 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1908 * set when the optics detect a signal. On older adapters, it will be 1909 * cleared when there is a signal 1910 */ 1911 ctrl = E1000_READ_REG(hw, CTRL); 1912 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 1913 signal = E1000_CTRL_SWDPIN1; 1914 else 1915 signal = 0; 1916 1917 status = E1000_READ_REG(hw, STATUS); 1918 rxcw = E1000_READ_REG(hw, RXCW); 1919 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 1920 1921 /* If we have a copper PHY then we only want to go out to the PHY 1922 * registers to see if Auto-Neg has completed and/or if our link 1923 * status has changed. The get_link_status flag will be set if we 1924 * receive a Link Status Change interrupt or we have Rx Sequence 1925 * Errors. 1926 */ 1927 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 1928 /* First we want to see if the MII Status Register reports 1929 * link. If so, then we want to get the current speed/duplex 1930 * of the PHY. 1931 * Read the register twice since the link bit is sticky. 1932 */ 1933 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1934 DEBUGOUT("PHY Read Error\n"); 1935 return -E1000_ERR_PHY; 1936 } 1937 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1938 DEBUGOUT("PHY Read Error\n"); 1939 return -E1000_ERR_PHY; 1940 } 1941 1942 if (phy_data & MII_SR_LINK_STATUS) { 1943 hw->get_link_status = FALSE; 1944 } else { 1945 /* No link detected */ 1946 return -E1000_ERR_NOLINK; 1947 } 1948 1949 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1950 * have Si on board that is 82544 or newer, Auto 1951 * Speed Detection takes care of MAC speed/duplex 1952 * configuration. So we only need to configure Collision 1953 * Distance in the MAC. Otherwise, we need to force 1954 * speed/duplex on the MAC to the current PHY speed/duplex 1955 * settings. 1956 */ 1957 if (hw->mac_type >= e1000_82544) 1958 e1000_config_collision_dist(hw); 1959 else { 1960 ret_val = e1000_config_mac_to_phy(hw); 1961 if (ret_val < 0) { 1962 DEBUGOUT 1963 ("Error configuring MAC to PHY settings\n"); 1964 return ret_val; 1965 } 1966 } 1967 1968 /* Configure Flow Control now that Auto-Neg has completed. First, we 1969 * need to restore the desired flow control settings because we may 1970 * have had to re-autoneg with a different link partner. 1971 */ 1972 ret_val = e1000_config_fc_after_link_up(hw); 1973 if (ret_val < 0) { 1974 DEBUGOUT("Error configuring flow control\n"); 1975 return ret_val; 1976 } 1977 1978 /* At this point we know that we are on copper and we have 1979 * auto-negotiated link. These are conditions for checking the link 1980 * parter capability register. We use the link partner capability to 1981 * determine if TBI Compatibility needs to be turned on or off. If 1982 * the link partner advertises any speed in addition to Gigabit, then 1983 * we assume that they are GMII-based, and TBI compatibility is not 1984 * needed. If no other speeds are advertised, we assume the link 1985 * partner is TBI-based, and we turn on TBI Compatibility. 1986 */ 1987 if (hw->tbi_compatibility_en) { 1988 if (e1000_read_phy_reg 1989 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 1990 DEBUGOUT("PHY Read Error\n"); 1991 return -E1000_ERR_PHY; 1992 } 1993 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 1994 NWAY_LPAR_10T_FD_CAPS | 1995 NWAY_LPAR_100TX_HD_CAPS | 1996 NWAY_LPAR_100TX_FD_CAPS | 1997 NWAY_LPAR_100T4_CAPS)) { 1998 /* If our link partner advertises anything in addition to 1999 * gigabit, we do not need to enable TBI compatibility. 2000 */ 2001 if (hw->tbi_compatibility_on) { 2002 /* If we previously were in the mode, turn it off. */ 2003 rctl = E1000_READ_REG(hw, RCTL); 2004 rctl &= ~E1000_RCTL_SBP; 2005 E1000_WRITE_REG(hw, RCTL, rctl); 2006 hw->tbi_compatibility_on = FALSE; 2007 } 2008 } else { 2009 /* If TBI compatibility is was previously off, turn it on. For 2010 * compatibility with a TBI link partner, we will store bad 2011 * packets. Some frames have an additional byte on the end and 2012 * will look like CRC errors to to the hardware. 2013 */ 2014 if (!hw->tbi_compatibility_on) { 2015 hw->tbi_compatibility_on = TRUE; 2016 rctl = E1000_READ_REG(hw, RCTL); 2017 rctl |= E1000_RCTL_SBP; 2018 E1000_WRITE_REG(hw, RCTL, rctl); 2019 } 2020 } 2021 } 2022 } 2023 /* If we don't have link (auto-negotiation failed or link partner cannot 2024 * auto-negotiate), the cable is plugged in (we have signal), and our 2025 * link partner is not trying to auto-negotiate with us (we are receiving 2026 * idles or data), we need to force link up. We also need to give 2027 * auto-negotiation time to complete, in case the cable was just plugged 2028 * in. The autoneg_failed flag does this. 2029 */ 2030 else if ((hw->media_type == e1000_media_type_fiber) && 2031 (!(status & E1000_STATUS_LU)) && 2032 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 2033 (!(rxcw & E1000_RXCW_C))) { 2034 if (hw->autoneg_failed == 0) { 2035 hw->autoneg_failed = 1; 2036 return 0; 2037 } 2038 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 2039 2040 /* Disable auto-negotiation in the TXCW register */ 2041 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2042 2043 /* Force link-up and also force full-duplex. */ 2044 ctrl = E1000_READ_REG(hw, CTRL); 2045 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2046 E1000_WRITE_REG(hw, CTRL, ctrl); 2047 2048 /* Configure Flow Control after forcing link up. */ 2049 ret_val = e1000_config_fc_after_link_up(hw); 2050 if (ret_val < 0) { 2051 DEBUGOUT("Error configuring flow control\n"); 2052 return ret_val; 2053 } 2054 } 2055 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 2056 * auto-negotiation in the TXCW register and disable forced link in the 2057 * Device Control register in an attempt to auto-negotiate with our link 2058 * partner. 2059 */ 2060 else if ((hw->media_type == e1000_media_type_fiber) && 2061 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2062 DEBUGOUT 2063 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 2064 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2065 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2066 } 2067 return 0; 2068 } 2069 2070 /****************************************************************************** 2071 * Detects the current speed and duplex settings of the hardware. 2072 * 2073 * hw - Struct containing variables accessed by shared code 2074 * speed - Speed of the connection 2075 * duplex - Duplex setting of the connection 2076 *****************************************************************************/ 2077 static void 2078 e1000_get_speed_and_duplex(struct e1000_hw *hw, 2079 uint16_t * speed, uint16_t * duplex) 2080 { 2081 uint32_t status; 2082 2083 DEBUGFUNC(); 2084 2085 if (hw->mac_type >= e1000_82543) { 2086 status = E1000_READ_REG(hw, STATUS); 2087 if (status & E1000_STATUS_SPEED_1000) { 2088 *speed = SPEED_1000; 2089 DEBUGOUT("1000 Mbs, "); 2090 } else if (status & E1000_STATUS_SPEED_100) { 2091 *speed = SPEED_100; 2092 DEBUGOUT("100 Mbs, "); 2093 } else { 2094 *speed = SPEED_10; 2095 DEBUGOUT("10 Mbs, "); 2096 } 2097 2098 if (status & E1000_STATUS_FD) { 2099 *duplex = FULL_DUPLEX; 2100 DEBUGOUT("Full Duplex\r\n"); 2101 } else { 2102 *duplex = HALF_DUPLEX; 2103 DEBUGOUT(" Half Duplex\r\n"); 2104 } 2105 } else { 2106 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 2107 *speed = SPEED_1000; 2108 *duplex = FULL_DUPLEX; 2109 } 2110 } 2111 2112 /****************************************************************************** 2113 * Blocks until autoneg completes or times out (~4.5 seconds) 2114 * 2115 * hw - Struct containing variables accessed by shared code 2116 ******************************************************************************/ 2117 static int 2118 e1000_wait_autoneg(struct e1000_hw *hw) 2119 { 2120 uint16_t i; 2121 uint16_t phy_data; 2122 2123 DEBUGFUNC(); 2124 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2125 2126 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2127 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2128 /* Read the MII Status Register and wait for Auto-Neg 2129 * Complete bit to be set. 2130 */ 2131 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2132 DEBUGOUT("PHY Read Error\n"); 2133 return -E1000_ERR_PHY; 2134 } 2135 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2136 DEBUGOUT("PHY Read Error\n"); 2137 return -E1000_ERR_PHY; 2138 } 2139 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2140 DEBUGOUT("Auto-Neg complete.\n"); 2141 return 0; 2142 } 2143 mdelay(100); 2144 } 2145 DEBUGOUT("Auto-Neg timedout.\n"); 2146 return -E1000_ERR_TIMEOUT; 2147 } 2148 2149 /****************************************************************************** 2150 * Raises the Management Data Clock 2151 * 2152 * hw - Struct containing variables accessed by shared code 2153 * ctrl - Device control register's current value 2154 ******************************************************************************/ 2155 static void 2156 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2157 { 2158 /* Raise the clock input to the Management Data Clock (by setting the MDC 2159 * bit), and then delay 2 microseconds. 2160 */ 2161 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2162 E1000_WRITE_FLUSH(hw); 2163 udelay(2); 2164 } 2165 2166 /****************************************************************************** 2167 * Lowers the Management Data Clock 2168 * 2169 * hw - Struct containing variables accessed by shared code 2170 * ctrl - Device control register's current value 2171 ******************************************************************************/ 2172 static void 2173 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 2174 { 2175 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2176 * bit), and then delay 2 microseconds. 2177 */ 2178 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2179 E1000_WRITE_FLUSH(hw); 2180 udelay(2); 2181 } 2182 2183 /****************************************************************************** 2184 * Shifts data bits out to the PHY 2185 * 2186 * hw - Struct containing variables accessed by shared code 2187 * data - Data to send out to the PHY 2188 * count - Number of bits to shift out 2189 * 2190 * Bits are shifted out in MSB to LSB order. 2191 ******************************************************************************/ 2192 static void 2193 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 2194 { 2195 uint32_t ctrl; 2196 uint32_t mask; 2197 2198 /* We need to shift "count" number of bits out to the PHY. So, the value 2199 * in the "data" parameter will be shifted out to the PHY one bit at a 2200 * time. In order to do this, "data" must be broken down into bits. 2201 */ 2202 mask = 0x01; 2203 mask <<= (count - 1); 2204 2205 ctrl = E1000_READ_REG(hw, CTRL); 2206 2207 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2208 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2209 2210 while (mask) { 2211 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2212 * then raising and lowering the Management Data Clock. A "0" is 2213 * shifted out to the PHY by setting the MDIO bit to "0" and then 2214 * raising and lowering the clock. 2215 */ 2216 if (data & mask) 2217 ctrl |= E1000_CTRL_MDIO; 2218 else 2219 ctrl &= ~E1000_CTRL_MDIO; 2220 2221 E1000_WRITE_REG(hw, CTRL, ctrl); 2222 E1000_WRITE_FLUSH(hw); 2223 2224 udelay(2); 2225 2226 e1000_raise_mdi_clk(hw, &ctrl); 2227 e1000_lower_mdi_clk(hw, &ctrl); 2228 2229 mask = mask >> 1; 2230 } 2231 } 2232 2233 /****************************************************************************** 2234 * Shifts data bits in from the PHY 2235 * 2236 * hw - Struct containing variables accessed by shared code 2237 * 2238 * Bits are shifted in in MSB to LSB order. 2239 ******************************************************************************/ 2240 static uint16_t 2241 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2242 { 2243 uint32_t ctrl; 2244 uint16_t data = 0; 2245 uint8_t i; 2246 2247 /* In order to read a register from the PHY, we need to shift in a total 2248 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2249 * to avoid contention on the MDIO pin when a read operation is performed. 2250 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2251 * by raising the input to the Management Data Clock (setting the MDC bit), 2252 * and then reading the value of the MDIO bit. 2253 */ 2254 ctrl = E1000_READ_REG(hw, CTRL); 2255 2256 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2257 ctrl &= ~E1000_CTRL_MDIO_DIR; 2258 ctrl &= ~E1000_CTRL_MDIO; 2259 2260 E1000_WRITE_REG(hw, CTRL, ctrl); 2261 E1000_WRITE_FLUSH(hw); 2262 2263 /* Raise and Lower the clock before reading in the data. This accounts for 2264 * the turnaround bits. The first clock occurred when we clocked out the 2265 * last bit of the Register Address. 2266 */ 2267 e1000_raise_mdi_clk(hw, &ctrl); 2268 e1000_lower_mdi_clk(hw, &ctrl); 2269 2270 for (data = 0, i = 0; i < 16; i++) { 2271 data = data << 1; 2272 e1000_raise_mdi_clk(hw, &ctrl); 2273 ctrl = E1000_READ_REG(hw, CTRL); 2274 /* Check to see if we shifted in a "1". */ 2275 if (ctrl & E1000_CTRL_MDIO) 2276 data |= 1; 2277 e1000_lower_mdi_clk(hw, &ctrl); 2278 } 2279 2280 e1000_raise_mdi_clk(hw, &ctrl); 2281 e1000_lower_mdi_clk(hw, &ctrl); 2282 2283 return data; 2284 } 2285 2286 /***************************************************************************** 2287 * Reads the value from a PHY register 2288 * 2289 * hw - Struct containing variables accessed by shared code 2290 * reg_addr - address of the PHY register to read 2291 ******************************************************************************/ 2292 static int 2293 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 2294 { 2295 uint32_t i; 2296 uint32_t mdic = 0; 2297 const uint32_t phy_addr = 1; 2298 2299 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2300 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2301 return -E1000_ERR_PARAM; 2302 } 2303 2304 if (hw->mac_type > e1000_82543) { 2305 /* Set up Op-code, Phy Address, and register address in the MDI 2306 * Control register. The MAC will take care of interfacing with the 2307 * PHY to retrieve the desired data. 2308 */ 2309 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2310 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2311 (E1000_MDIC_OP_READ)); 2312 2313 E1000_WRITE_REG(hw, MDIC, mdic); 2314 2315 /* Poll the ready bit to see if the MDI read completed */ 2316 for (i = 0; i < 64; i++) { 2317 udelay(10); 2318 mdic = E1000_READ_REG(hw, MDIC); 2319 if (mdic & E1000_MDIC_READY) 2320 break; 2321 } 2322 if (!(mdic & E1000_MDIC_READY)) { 2323 DEBUGOUT("MDI Read did not complete\n"); 2324 return -E1000_ERR_PHY; 2325 } 2326 if (mdic & E1000_MDIC_ERROR) { 2327 DEBUGOUT("MDI Error\n"); 2328 return -E1000_ERR_PHY; 2329 } 2330 *phy_data = (uint16_t) mdic; 2331 } else { 2332 /* We must first send a preamble through the MDIO pin to signal the 2333 * beginning of an MII instruction. This is done by sending 32 2334 * consecutive "1" bits. 2335 */ 2336 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2337 2338 /* Now combine the next few fields that are required for a read 2339 * operation. We use this method instead of calling the 2340 * e1000_shift_out_mdi_bits routine five different times. The format of 2341 * a MII read instruction consists of a shift out of 14 bits and is 2342 * defined as follows: 2343 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2344 * followed by a shift in of 18 bits. This first two bits shifted in 2345 * are TurnAround bits used to avoid contention on the MDIO pin when a 2346 * READ operation is performed. These two bits are thrown away 2347 * followed by a shift in of 16 bits which contains the desired data. 2348 */ 2349 mdic = ((reg_addr) | (phy_addr << 5) | 2350 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2351 2352 e1000_shift_out_mdi_bits(hw, mdic, 14); 2353 2354 /* Now that we've shifted out the read command to the MII, we need to 2355 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2356 * register address. 2357 */ 2358 *phy_data = e1000_shift_in_mdi_bits(hw); 2359 } 2360 return 0; 2361 } 2362 2363 /****************************************************************************** 2364 * Writes a value to a PHY register 2365 * 2366 * hw - Struct containing variables accessed by shared code 2367 * reg_addr - address of the PHY register to write 2368 * data - data to write to the PHY 2369 ******************************************************************************/ 2370 static int 2371 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 2372 { 2373 uint32_t i; 2374 uint32_t mdic = 0; 2375 const uint32_t phy_addr = 1; 2376 2377 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2378 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 2379 return -E1000_ERR_PARAM; 2380 } 2381 2382 if (hw->mac_type > e1000_82543) { 2383 /* Set up Op-code, Phy Address, register address, and data intended 2384 * for the PHY register in the MDI Control register. The MAC will take 2385 * care of interfacing with the PHY to send the desired data. 2386 */ 2387 mdic = (((uint32_t) phy_data) | 2388 (reg_addr << E1000_MDIC_REG_SHIFT) | 2389 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2390 (E1000_MDIC_OP_WRITE)); 2391 2392 E1000_WRITE_REG(hw, MDIC, mdic); 2393 2394 /* Poll the ready bit to see if the MDI read completed */ 2395 for (i = 0; i < 64; i++) { 2396 udelay(10); 2397 mdic = E1000_READ_REG(hw, MDIC); 2398 if (mdic & E1000_MDIC_READY) 2399 break; 2400 } 2401 if (!(mdic & E1000_MDIC_READY)) { 2402 DEBUGOUT("MDI Write did not complete\n"); 2403 return -E1000_ERR_PHY; 2404 } 2405 } else { 2406 /* We'll need to use the SW defined pins to shift the write command 2407 * out to the PHY. We first send a preamble to the PHY to signal the 2408 * beginning of the MII instruction. This is done by sending 32 2409 * consecutive "1" bits. 2410 */ 2411 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2412 2413 /* Now combine the remaining required fields that will indicate a 2414 * write operation. We use this method instead of calling the 2415 * e1000_shift_out_mdi_bits routine for each field in the command. The 2416 * format of a MII write instruction is as follows: 2417 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2418 */ 2419 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2420 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2421 mdic <<= 16; 2422 mdic |= (uint32_t) phy_data; 2423 2424 e1000_shift_out_mdi_bits(hw, mdic, 32); 2425 } 2426 return 0; 2427 } 2428 2429 /****************************************************************************** 2430 * Returns the PHY to the power-on reset state 2431 * 2432 * hw - Struct containing variables accessed by shared code 2433 ******************************************************************************/ 2434 static void 2435 e1000_phy_hw_reset(struct e1000_hw *hw) 2436 { 2437 uint32_t ctrl; 2438 uint32_t ctrl_ext; 2439 2440 DEBUGFUNC(); 2441 2442 DEBUGOUT("Resetting Phy...\n"); 2443 2444 if (hw->mac_type > e1000_82543) { 2445 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2446 * bit. Then, take it out of reset. 2447 */ 2448 ctrl = E1000_READ_REG(hw, CTRL); 2449 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 2450 E1000_WRITE_FLUSH(hw); 2451 mdelay(10); 2452 E1000_WRITE_REG(hw, CTRL, ctrl); 2453 E1000_WRITE_FLUSH(hw); 2454 } else { 2455 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2456 * bit to put the PHY into reset. Then, take it out of reset. 2457 */ 2458 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2459 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2460 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2461 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2462 E1000_WRITE_FLUSH(hw); 2463 mdelay(10); 2464 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2465 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2466 E1000_WRITE_FLUSH(hw); 2467 } 2468 udelay(150); 2469 } 2470 2471 /****************************************************************************** 2472 * Resets the PHY 2473 * 2474 * hw - Struct containing variables accessed by shared code 2475 * 2476 * Sets bit 15 of the MII Control regiser 2477 ******************************************************************************/ 2478 static int 2479 e1000_phy_reset(struct e1000_hw *hw) 2480 { 2481 uint16_t phy_data; 2482 2483 DEBUGFUNC(); 2484 2485 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 2486 DEBUGOUT("PHY Read Error\n"); 2487 return -E1000_ERR_PHY; 2488 } 2489 phy_data |= MII_CR_RESET; 2490 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 2491 DEBUGOUT("PHY Write Error\n"); 2492 return -E1000_ERR_PHY; 2493 } 2494 udelay(1); 2495 return 0; 2496 } 2497 2498 static int e1000_set_phy_type (struct e1000_hw *hw) 2499 { 2500 DEBUGFUNC (); 2501 2502 if (hw->mac_type == e1000_undefined) 2503 return -E1000_ERR_PHY_TYPE; 2504 2505 switch (hw->phy_id) { 2506 case M88E1000_E_PHY_ID: 2507 case M88E1000_I_PHY_ID: 2508 case M88E1011_I_PHY_ID: 2509 hw->phy_type = e1000_phy_m88; 2510 break; 2511 case IGP01E1000_I_PHY_ID: 2512 if (hw->mac_type == e1000_82541 || 2513 hw->mac_type == e1000_82541_rev_2) { 2514 hw->phy_type = e1000_phy_igp; 2515 break; 2516 } 2517 /* Fall Through */ 2518 default: 2519 /* Should never have loaded on this device */ 2520 hw->phy_type = e1000_phy_undefined; 2521 return -E1000_ERR_PHY_TYPE; 2522 } 2523 2524 return E1000_SUCCESS; 2525 } 2526 2527 /****************************************************************************** 2528 * Probes the expected PHY address for known PHY IDs 2529 * 2530 * hw - Struct containing variables accessed by shared code 2531 ******************************************************************************/ 2532 static int 2533 e1000_detect_gig_phy(struct e1000_hw *hw) 2534 { 2535 int32_t phy_init_status; 2536 uint16_t phy_id_high, phy_id_low; 2537 int match = FALSE; 2538 2539 DEBUGFUNC(); 2540 2541 /* Read the PHY ID Registers to identify which PHY is onboard. */ 2542 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { 2543 DEBUGOUT("PHY Read Error\n"); 2544 return -E1000_ERR_PHY; 2545 } 2546 hw->phy_id = (uint32_t) (phy_id_high << 16); 2547 udelay(2); 2548 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { 2549 DEBUGOUT("PHY Read Error\n"); 2550 return -E1000_ERR_PHY; 2551 } 2552 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 2553 2554 switch (hw->mac_type) { 2555 case e1000_82543: 2556 if (hw->phy_id == M88E1000_E_PHY_ID) 2557 match = TRUE; 2558 break; 2559 case e1000_82544: 2560 if (hw->phy_id == M88E1000_I_PHY_ID) 2561 match = TRUE; 2562 break; 2563 case e1000_82540: 2564 case e1000_82545: 2565 case e1000_82546: 2566 if (hw->phy_id == M88E1011_I_PHY_ID) 2567 match = TRUE; 2568 break; 2569 case e1000_82541_rev_2: 2570 if(hw->phy_id == IGP01E1000_I_PHY_ID) 2571 match = TRUE; 2572 2573 break; 2574 default: 2575 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 2576 return -E1000_ERR_CONFIG; 2577 } 2578 2579 phy_init_status = e1000_set_phy_type(hw); 2580 2581 if ((match) && (phy_init_status == E1000_SUCCESS)) { 2582 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 2583 return 0; 2584 } 2585 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 2586 return -E1000_ERR_PHY; 2587 } 2588 2589 /** 2590 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 2591 * 2592 * e1000_sw_init initializes the Adapter private data structure. 2593 * Fields are initialized based on PCI device information and 2594 * OS network device settings (MTU size). 2595 **/ 2596 2597 static int 2598 e1000_sw_init(struct eth_device *nic, int cardnum) 2599 { 2600 struct e1000_hw *hw = (typeof(hw)) nic->priv; 2601 int result; 2602 2603 /* PCI config space info */ 2604 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 2605 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 2606 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 2607 &hw->subsystem_vendor_id); 2608 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 2609 2610 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 2611 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 2612 2613 /* identify the MAC */ 2614 result = e1000_set_mac_type(hw); 2615 if (result) { 2616 E1000_ERR("Unknown MAC Type\n"); 2617 return result; 2618 } 2619 2620 /* lan a vs. lan b settings */ 2621 if (hw->mac_type == e1000_82546) 2622 /*this also works w/ multiple 82546 cards */ 2623 /*but not if they're intermingled /w other e1000s */ 2624 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; 2625 else 2626 hw->lan_loc = e1000_lan_a; 2627 2628 /* flow control settings */ 2629 hw->fc_high_water = E1000_FC_HIGH_THRESH; 2630 hw->fc_low_water = E1000_FC_LOW_THRESH; 2631 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 2632 hw->fc_send_xon = 1; 2633 2634 /* Media type - copper or fiber */ 2635 2636 if (hw->mac_type >= e1000_82543) { 2637 uint32_t status = E1000_READ_REG(hw, STATUS); 2638 2639 if (status & E1000_STATUS_TBIMODE) { 2640 DEBUGOUT("fiber interface\n"); 2641 hw->media_type = e1000_media_type_fiber; 2642 } else { 2643 DEBUGOUT("copper interface\n"); 2644 hw->media_type = e1000_media_type_copper; 2645 } 2646 } else { 2647 hw->media_type = e1000_media_type_fiber; 2648 } 2649 2650 if (hw->mac_type < e1000_82543) 2651 hw->report_tx_early = 0; 2652 else 2653 hw->report_tx_early = 1; 2654 2655 hw->tbi_compatibility_en = TRUE; 2656 #if 0 2657 hw->wait_autoneg_complete = FALSE; 2658 hw->adaptive_ifs = TRUE; 2659 2660 /* Copper options */ 2661 if (hw->media_type == e1000_media_type_copper) { 2662 hw->mdix = AUTO_ALL_MODES; 2663 hw->disable_polarity_correction = FALSE; 2664 } 2665 #endif 2666 return E1000_SUCCESS; 2667 } 2668 2669 void 2670 fill_rx(struct e1000_hw *hw) 2671 { 2672 struct e1000_rx_desc *rd; 2673 2674 rx_last = rx_tail; 2675 rd = rx_base + rx_tail; 2676 rx_tail = (rx_tail + 1) % 8; 2677 memset(rd, 0, 16); 2678 rd->buffer_addr = cpu_to_le64((u32) & packet); 2679 E1000_WRITE_REG(hw, RDT, rx_tail); 2680 } 2681 2682 /** 2683 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 2684 * @adapter: board private structure 2685 * 2686 * Configure the Tx unit of the MAC after a reset. 2687 **/ 2688 2689 static void 2690 e1000_configure_tx(struct e1000_hw *hw) 2691 { 2692 unsigned long ptr; 2693 unsigned long tctl; 2694 unsigned long tipg; 2695 2696 ptr = (u32) tx_pool; 2697 if (ptr & 0xf) 2698 ptr = (ptr + 0x10) & (~0xf); 2699 2700 tx_base = (typeof(tx_base)) ptr; 2701 2702 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); 2703 E1000_WRITE_REG(hw, TDBAH, 0); 2704 2705 E1000_WRITE_REG(hw, TDLEN, 128); 2706 2707 /* Setup the HW Tx Head and Tail descriptor pointers */ 2708 E1000_WRITE_REG(hw, TDH, 0); 2709 E1000_WRITE_REG(hw, TDT, 0); 2710 tx_tail = 0; 2711 2712 /* Set the default values for the Tx Inter Packet Gap timer */ 2713 switch (hw->mac_type) { 2714 case e1000_82542_rev2_0: 2715 case e1000_82542_rev2_1: 2716 tipg = DEFAULT_82542_TIPG_IPGT; 2717 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2718 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2719 break; 2720 default: 2721 if (hw->media_type == e1000_media_type_fiber) 2722 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2723 else 2724 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2725 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2726 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2727 } 2728 E1000_WRITE_REG(hw, TIPG, tipg); 2729 #if 0 2730 /* Set the Tx Interrupt Delay register */ 2731 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); 2732 if (hw->mac_type >= e1000_82540) 2733 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); 2734 #endif 2735 /* Program the Transmit Control Register */ 2736 tctl = E1000_READ_REG(hw, TCTL); 2737 tctl &= ~E1000_TCTL_CT; 2738 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 2739 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2740 E1000_WRITE_REG(hw, TCTL, tctl); 2741 2742 e1000_config_collision_dist(hw); 2743 #if 0 2744 /* Setup Transmit Descriptor Settings for this adapter */ 2745 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; 2746 2747 if (adapter->hw.report_tx_early == 1) 2748 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2749 else 2750 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 2751 #endif 2752 } 2753 2754 /** 2755 * e1000_setup_rctl - configure the receive control register 2756 * @adapter: Board private structure 2757 **/ 2758 static void 2759 e1000_setup_rctl(struct e1000_hw *hw) 2760 { 2761 uint32_t rctl; 2762 2763 rctl = E1000_READ_REG(hw, RCTL); 2764 2765 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2766 2767 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | 2768 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 2769 2770 if (hw->tbi_compatibility_on == 1) 2771 rctl |= E1000_RCTL_SBP; 2772 else 2773 rctl &= ~E1000_RCTL_SBP; 2774 2775 rctl &= ~(E1000_RCTL_SZ_4096); 2776 #if 0 2777 switch (adapter->rx_buffer_len) { 2778 case E1000_RXBUFFER_2048: 2779 default: 2780 #endif 2781 rctl |= E1000_RCTL_SZ_2048; 2782 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 2783 #if 0 2784 break; 2785 case E1000_RXBUFFER_4096: 2786 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2787 break; 2788 case E1000_RXBUFFER_8192: 2789 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2790 break; 2791 case E1000_RXBUFFER_16384: 2792 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; 2793 break; 2794 } 2795 #endif 2796 E1000_WRITE_REG(hw, RCTL, rctl); 2797 } 2798 2799 /** 2800 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 2801 * @adapter: board private structure 2802 * 2803 * Configure the Rx unit of the MAC after a reset. 2804 **/ 2805 static void 2806 e1000_configure_rx(struct e1000_hw *hw) 2807 { 2808 unsigned long ptr; 2809 unsigned long rctl; 2810 #if 0 2811 unsigned long rxcsum; 2812 #endif 2813 rx_tail = 0; 2814 /* make sure receives are disabled while setting up the descriptors */ 2815 rctl = E1000_READ_REG(hw, RCTL); 2816 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 2817 #if 0 2818 /* set the Receive Delay Timer Register */ 2819 2820 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); 2821 #endif 2822 if (hw->mac_type >= e1000_82540) { 2823 #if 0 2824 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 2825 #endif 2826 /* Set the interrupt throttling rate. Value is calculated 2827 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2828 #define MAX_INTS_PER_SEC 8000 2829 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 2830 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 2831 } 2832 2833 /* Setup the Base and Length of the Rx Descriptor Ring */ 2834 ptr = (u32) rx_pool; 2835 if (ptr & 0xf) 2836 ptr = (ptr + 0x10) & (~0xf); 2837 rx_base = (typeof(rx_base)) ptr; 2838 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); 2839 E1000_WRITE_REG(hw, RDBAH, 0); 2840 2841 E1000_WRITE_REG(hw, RDLEN, 128); 2842 2843 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2844 E1000_WRITE_REG(hw, RDH, 0); 2845 E1000_WRITE_REG(hw, RDT, 0); 2846 #if 0 2847 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2848 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { 2849 rxcsum = E1000_READ_REG(hw, RXCSUM); 2850 rxcsum |= E1000_RXCSUM_TUOFL; 2851 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 2852 } 2853 #endif 2854 /* Enable Receives */ 2855 2856 E1000_WRITE_REG(hw, RCTL, rctl); 2857 fill_rx(hw); 2858 } 2859 2860 /************************************************************************** 2861 POLL - Wait for a frame 2862 ***************************************************************************/ 2863 static int 2864 e1000_poll(struct eth_device *nic) 2865 { 2866 struct e1000_hw *hw = nic->priv; 2867 struct e1000_rx_desc *rd; 2868 /* return true if there's an ethernet packet ready to read */ 2869 rd = rx_base + rx_last; 2870 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) 2871 return 0; 2872 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ 2873 NetReceive((uchar *)packet, le32_to_cpu(rd->length)); 2874 fill_rx(hw); 2875 return 1; 2876 } 2877 2878 /************************************************************************** 2879 TRANSMIT - Transmit a frame 2880 ***************************************************************************/ 2881 static int 2882 e1000_transmit(struct eth_device *nic, volatile void *packet, int length) 2883 { 2884 struct e1000_hw *hw = nic->priv; 2885 struct e1000_tx_desc *txp; 2886 int i = 0; 2887 2888 txp = tx_base + tx_tail; 2889 tx_tail = (tx_tail + 1) % 8; 2890 2891 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); 2892 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | 2893 E1000_TXD_CMD_IFCS | length); 2894 txp->upper.data = 0; 2895 E1000_WRITE_REG(hw, TDT, tx_tail); 2896 2897 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { 2898 if (i++ > TOUT_LOOP) { 2899 DEBUGOUT("e1000: tx timeout\n"); 2900 return 0; 2901 } 2902 udelay(10); /* give the nic a chance to write to the register */ 2903 } 2904 return 1; 2905 } 2906 2907 /*reset function*/ 2908 static inline int 2909 e1000_reset(struct eth_device *nic) 2910 { 2911 struct e1000_hw *hw = nic->priv; 2912 2913 e1000_reset_hw(hw); 2914 if (hw->mac_type >= e1000_82544) { 2915 E1000_WRITE_REG(hw, WUC, 0); 2916 } 2917 return e1000_init_hw(nic); 2918 } 2919 2920 /************************************************************************** 2921 DISABLE - Turn off ethernet interface 2922 ***************************************************************************/ 2923 static void 2924 e1000_disable(struct eth_device *nic) 2925 { 2926 struct e1000_hw *hw = nic->priv; 2927 2928 /* Turn off the ethernet interface */ 2929 E1000_WRITE_REG(hw, RCTL, 0); 2930 E1000_WRITE_REG(hw, TCTL, 0); 2931 2932 /* Clear the transmit ring */ 2933 E1000_WRITE_REG(hw, TDH, 0); 2934 E1000_WRITE_REG(hw, TDT, 0); 2935 2936 /* Clear the receive ring */ 2937 E1000_WRITE_REG(hw, RDH, 0); 2938 E1000_WRITE_REG(hw, RDT, 0); 2939 2940 /* put the card in its initial state */ 2941 #if 0 2942 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); 2943 #endif 2944 mdelay(10); 2945 2946 } 2947 2948 /************************************************************************** 2949 INIT - set up ethernet interface(s) 2950 ***************************************************************************/ 2951 static int 2952 e1000_init(struct eth_device *nic, bd_t * bis) 2953 { 2954 struct e1000_hw *hw = nic->priv; 2955 int ret_val = 0; 2956 2957 ret_val = e1000_reset(nic); 2958 if (ret_val < 0) { 2959 if ((ret_val == -E1000_ERR_NOLINK) || 2960 (ret_val == -E1000_ERR_TIMEOUT)) { 2961 E1000_ERR("Valid Link not detected\n"); 2962 } else { 2963 E1000_ERR("Hardware Initialization Failed\n"); 2964 } 2965 return 0; 2966 } 2967 e1000_configure_tx(hw); 2968 e1000_setup_rctl(hw); 2969 e1000_configure_rx(hw); 2970 return 1; 2971 } 2972 2973 /************************************************************************** 2974 PROBE - Look for an adapter, this routine's visible to the outside 2975 You should omit the last argument struct pci_device * for a non-PCI NIC 2976 ***************************************************************************/ 2977 int 2978 e1000_initialize(bd_t * bis) 2979 { 2980 pci_dev_t devno; 2981 int card_number = 0; 2982 struct eth_device *nic = NULL; 2983 struct e1000_hw *hw = NULL; 2984 u32 iobase; 2985 int idx = 0; 2986 u32 PciCommandWord; 2987 2988 while (1) { /* Find PCI device(s) */ 2989 if ((devno = pci_find_devices(supported, idx++)) < 0) { 2990 break; 2991 } 2992 2993 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); 2994 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ 2995 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); 2996 2997 pci_write_config_dword(devno, PCI_COMMAND, 2998 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 2999 /* Check if I/O accesses and Bus Mastering are enabled. */ 3000 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); 3001 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { 3002 printf("Error: Can not enable MEM access.\n"); 3003 continue; 3004 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { 3005 printf("Error: Can not enable Bus Mastering.\n"); 3006 continue; 3007 } 3008 3009 nic = (struct eth_device *) malloc(sizeof (*nic)); 3010 hw = (struct e1000_hw *) malloc(sizeof (*hw)); 3011 hw->pdev = devno; 3012 nic->priv = hw; 3013 nic->iobase = bus_to_phys(devno, iobase); 3014 3015 sprintf(nic->name, "e1000#%d", card_number); 3016 3017 /* Are these variables needed? */ 3018 #if 0 3019 hw->fc = e1000_fc_none; 3020 hw->original_fc = e1000_fc_none; 3021 #else 3022 hw->fc = e1000_fc_default; 3023 hw->original_fc = e1000_fc_default; 3024 #endif 3025 hw->autoneg_failed = 0; 3026 hw->get_link_status = TRUE; 3027 hw->hw_addr = (typeof(hw->hw_addr)) iobase; 3028 hw->mac_type = e1000_undefined; 3029 3030 /* MAC and Phy settings */ 3031 if (e1000_sw_init(nic, card_number) < 0) { 3032 free(hw); 3033 free(nic); 3034 return 0; 3035 } 3036 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) 3037 if (e1000_validate_eeprom_checksum(nic) < 0) { 3038 printf("The EEPROM Checksum Is Not Valid\n"); 3039 free(hw); 3040 free(nic); 3041 return 0; 3042 } 3043 #endif 3044 e1000_read_mac_addr(nic); 3045 3046 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); 3047 3048 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", 3049 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], 3050 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); 3051 3052 nic->init = e1000_init; 3053 nic->recv = e1000_poll; 3054 nic->send = e1000_transmit; 3055 nic->halt = e1000_disable; 3056 3057 eth_register(nic); 3058 3059 card_number++; 3060 } 3061 return 1; 3062 } 3063