1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * Designware ethernet IP driver for u-boot 26 */ 27 28 #include <common.h> 29 #include <miiphy.h> 30 #include <malloc.h> 31 #include <linux/err.h> 32 #include <asm/io.h> 33 #include "designware.h" 34 35 static void tx_descs_init(struct eth_device *dev) 36 { 37 struct dw_eth_dev *priv = dev->priv; 38 struct eth_dma_regs *dma_p = priv->dma_regs_p; 39 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 40 char *txbuffs = &priv->txbuffs[0]; 41 struct dmamacdescr *desc_p; 42 u32 idx; 43 44 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 45 desc_p = &desc_table_p[idx]; 46 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 47 desc_p->dmamac_next = &desc_table_p[idx + 1]; 48 49 #if defined(CONFIG_DW_ALTDESCRIPTOR) 50 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 51 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ 52 DESC_TXSTS_TXCHECKINSCTRL | \ 53 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 54 55 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 56 desc_p->dmamac_cntl = 0; 57 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 58 #else 59 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 60 desc_p->txrx_status = 0; 61 #endif 62 } 63 64 /* Correcting the last pointer of the chain */ 65 desc_p->dmamac_next = &desc_table_p[0]; 66 67 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 68 } 69 70 static void rx_descs_init(struct eth_device *dev) 71 { 72 struct dw_eth_dev *priv = dev->priv; 73 struct eth_dma_regs *dma_p = priv->dma_regs_p; 74 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 75 char *rxbuffs = &priv->rxbuffs[0]; 76 struct dmamacdescr *desc_p; 77 u32 idx; 78 79 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 80 desc_p = &desc_table_p[idx]; 81 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 82 desc_p->dmamac_next = &desc_table_p[idx + 1]; 83 84 desc_p->dmamac_cntl = 85 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ 86 DESC_RXCTRL_RXCHAIN; 87 88 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 89 } 90 91 /* Correcting the last pointer of the chain */ 92 desc_p->dmamac_next = &desc_table_p[0]; 93 94 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 95 } 96 97 static void descs_init(struct eth_device *dev) 98 { 99 tx_descs_init(dev); 100 rx_descs_init(dev); 101 } 102 103 static int mac_reset(struct eth_device *dev) 104 { 105 struct dw_eth_dev *priv = dev->priv; 106 struct eth_mac_regs *mac_p = priv->mac_regs_p; 107 struct eth_dma_regs *dma_p = priv->dma_regs_p; 108 109 int timeout = CONFIG_MACRESET_TIMEOUT; 110 111 writel(DMAMAC_SRST, &dma_p->busmode); 112 writel(MII_PORTSELECT, &mac_p->conf); 113 114 do { 115 if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) 116 return 0; 117 udelay(1000); 118 } while (timeout--); 119 120 return -1; 121 } 122 123 static int dw_write_hwaddr(struct eth_device *dev) 124 { 125 struct dw_eth_dev *priv = dev->priv; 126 struct eth_mac_regs *mac_p = priv->mac_regs_p; 127 u32 macid_lo, macid_hi; 128 u8 *mac_id = &dev->enetaddr[0]; 129 130 macid_lo = mac_id[0] + (mac_id[1] << 8) + \ 131 (mac_id[2] << 16) + (mac_id[3] << 24); 132 macid_hi = mac_id[4] + (mac_id[5] << 8); 133 134 writel(macid_hi, &mac_p->macaddr0hi); 135 writel(macid_lo, &mac_p->macaddr0lo); 136 137 return 0; 138 } 139 140 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 141 { 142 struct dw_eth_dev *priv = dev->priv; 143 struct eth_mac_regs *mac_p = priv->mac_regs_p; 144 struct eth_dma_regs *dma_p = priv->dma_regs_p; 145 u32 conf; 146 147 /* Reset ethernet hardware */ 148 if (mac_reset(dev) < 0) 149 return -1; 150 151 /* Resore the HW MAC address as it has been lost during MAC reset */ 152 dw_write_hwaddr(dev); 153 154 writel(FIXEDBURST | PRIORXTX_41 | BURST_16, 155 &dma_p->busmode); 156 157 writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); 158 writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); 159 160 conf = FRAMEBURSTENABLE | DISABLERXOWN; 161 162 if (priv->speed != SPEED_1000M) 163 conf |= MII_PORTSELECT; 164 165 if (priv->duplex == FULL_DUPLEX) 166 conf |= FULLDPLXMODE; 167 168 writel(conf, &mac_p->conf); 169 170 descs_init(dev); 171 172 /* 173 * Start/Enable xfer at dma as well as mac level 174 */ 175 writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); 176 writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); 177 178 writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); 179 writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); 180 181 return 0; 182 } 183 184 static int dw_eth_send(struct eth_device *dev, volatile void *packet, 185 int length) 186 { 187 struct dw_eth_dev *priv = dev->priv; 188 struct eth_dma_regs *dma_p = priv->dma_regs_p; 189 u32 desc_num = priv->tx_currdescnum; 190 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 191 192 /* Check if the descriptor is owned by CPU */ 193 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 194 printf("CPU not owner of tx frame\n"); 195 return -1; 196 } 197 198 memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); 199 200 #if defined(CONFIG_DW_ALTDESCRIPTOR) 201 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 202 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ 203 DESC_TXCTRL_SIZE1MASK; 204 205 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 206 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 207 #else 208 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ 209 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ 210 DESC_TXCTRL_TXFIRST; 211 212 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 213 #endif 214 215 /* Test the wrap-around condition. */ 216 if (++desc_num >= CONFIG_TX_DESCR_NUM) 217 desc_num = 0; 218 219 priv->tx_currdescnum = desc_num; 220 221 /* Start the transmission */ 222 writel(POLL_DATA, &dma_p->txpolldemand); 223 224 return 0; 225 } 226 227 static int dw_eth_recv(struct eth_device *dev) 228 { 229 struct dw_eth_dev *priv = dev->priv; 230 u32 desc_num = priv->rx_currdescnum; 231 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 232 233 u32 status = desc_p->txrx_status; 234 int length = 0; 235 236 /* Check if the owner is the CPU */ 237 if (!(status & DESC_RXSTS_OWNBYDMA)) { 238 239 length = (status & DESC_RXSTS_FRMLENMSK) >> \ 240 DESC_RXSTS_FRMLENSHFT; 241 242 NetReceive(desc_p->dmamac_addr, length); 243 244 /* 245 * Make the current descriptor valid again and go to 246 * the next one 247 */ 248 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 249 250 /* Test the wrap-around condition. */ 251 if (++desc_num >= CONFIG_RX_DESCR_NUM) 252 desc_num = 0; 253 } 254 255 priv->rx_currdescnum = desc_num; 256 257 return length; 258 } 259 260 static void dw_eth_halt(struct eth_device *dev) 261 { 262 struct dw_eth_dev *priv = dev->priv; 263 264 mac_reset(dev); 265 priv->tx_currdescnum = priv->rx_currdescnum = 0; 266 } 267 268 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) 269 { 270 struct dw_eth_dev *priv = dev->priv; 271 struct eth_mac_regs *mac_p = priv->mac_regs_p; 272 u32 miiaddr; 273 int timeout = CONFIG_MDIO_TIMEOUT; 274 275 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 276 ((reg << MIIREGSHIFT) & MII_REGMSK); 277 278 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 279 280 do { 281 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 282 *val = readl(&mac_p->miidata); 283 return 0; 284 } 285 udelay(1000); 286 } while (timeout--); 287 288 return -1; 289 } 290 291 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) 292 { 293 struct dw_eth_dev *priv = dev->priv; 294 struct eth_mac_regs *mac_p = priv->mac_regs_p; 295 u32 miiaddr; 296 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; 297 u16 value; 298 299 writel(val, &mac_p->miidata); 300 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 301 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 302 303 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 304 305 do { 306 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 307 ret = 0; 308 break; 309 } 310 udelay(1000); 311 } while (timeout--); 312 313 /* Needed as a fix for ST-Phy */ 314 eth_mdio_read(dev, addr, reg, &value); 315 316 return ret; 317 } 318 319 #if defined(CONFIG_DW_SEARCH_PHY) 320 static int find_phy(struct eth_device *dev) 321 { 322 int phy_addr = 0; 323 u16 ctrl, oldctrl; 324 325 do { 326 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 327 oldctrl = ctrl & BMCR_ANENABLE; 328 329 ctrl ^= BMCR_ANENABLE; 330 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 331 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 332 ctrl &= BMCR_ANENABLE; 333 334 if (ctrl == oldctrl) { 335 phy_addr++; 336 } else { 337 ctrl ^= BMCR_ANENABLE; 338 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 339 340 return phy_addr; 341 } 342 } while (phy_addr < 32); 343 344 return -1; 345 } 346 #endif 347 348 static int dw_reset_phy(struct eth_device *dev) 349 { 350 struct dw_eth_dev *priv = dev->priv; 351 u16 ctrl; 352 int timeout = CONFIG_PHYRESET_TIMEOUT; 353 u32 phy_addr = priv->address; 354 355 eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); 356 do { 357 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 358 if (!(ctrl & BMCR_RESET)) 359 break; 360 udelay(1000); 361 } while (timeout--); 362 363 if (timeout < 0) 364 return -1; 365 366 #ifdef CONFIG_PHY_RESET_DELAY 367 udelay(CONFIG_PHY_RESET_DELAY); 368 #endif 369 return 0; 370 } 371 372 static int configure_phy(struct eth_device *dev) 373 { 374 struct dw_eth_dev *priv = dev->priv; 375 int phy_addr; 376 u16 bmcr; 377 #if defined(CONFIG_DW_AUTONEG) 378 u16 bmsr; 379 u32 timeout; 380 u16 anlpar, btsr; 381 #else 382 u16 ctrl; 383 #endif 384 385 #if defined(CONFIG_DW_SEARCH_PHY) 386 phy_addr = find_phy(dev); 387 if (phy_addr > 0) 388 priv->address = phy_addr; 389 else 390 return -1; 391 #else 392 phy_addr = priv->address; 393 #endif 394 if (dw_reset_phy(dev) < 0) 395 return -1; 396 397 #if defined(CONFIG_DW_AUTONEG) 398 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \ 399 BMCR_FULLDPLX | BMCR_SPEED1000; 400 #else 401 bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; 402 403 #if defined(CONFIG_DW_SPEED10M) 404 bmcr &= ~BMCR_SPEED100; 405 #endif 406 #if defined(CONFIG_DW_DUPLEXHALF) 407 bmcr &= ~BMCR_FULLDPLX; 408 #endif 409 #endif 410 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) 411 return -1; 412 413 /* Read the phy status register and populate priv structure */ 414 #if defined(CONFIG_DW_AUTONEG) 415 timeout = CONFIG_AUTONEG_TIMEOUT; 416 do { 417 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); 418 if (bmsr & BMSR_ANEGCOMPLETE) 419 break; 420 udelay(1000); 421 } while (timeout--); 422 423 eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); 424 eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); 425 426 if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 427 priv->speed = SPEED_1000M; 428 if (btsr & PHY_1000BTSR_1000FD) 429 priv->duplex = FULL_DUPLEX; 430 else 431 priv->duplex = HALF_DUPLEX; 432 } else { 433 if (anlpar & LPA_100) 434 priv->speed = SPEED_100M; 435 else 436 priv->speed = SPEED_10M; 437 438 if (anlpar & (LPA_10FULL | LPA_100FULL)) 439 priv->duplex = FULL_DUPLEX; 440 else 441 priv->duplex = HALF_DUPLEX; 442 } 443 #else 444 if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) 445 return -1; 446 447 if (ctrl & BMCR_FULLDPLX) 448 priv->duplex = FULL_DUPLEX; 449 else 450 priv->duplex = HALF_DUPLEX; 451 452 if (ctrl & BMCR_SPEED1000) 453 priv->speed = SPEED_1000M; 454 else if (ctrl & BMCR_SPEED100) 455 priv->speed = SPEED_100M; 456 else 457 priv->speed = SPEED_10M; 458 #endif 459 return 0; 460 } 461 462 #if defined(CONFIG_MII) 463 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) 464 { 465 struct eth_device *dev; 466 467 dev = eth_get_dev_by_name(devname); 468 if (dev) 469 eth_mdio_read(dev, addr, reg, val); 470 471 return 0; 472 } 473 474 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) 475 { 476 struct eth_device *dev; 477 478 dev = eth_get_dev_by_name(devname); 479 if (dev) 480 eth_mdio_write(dev, addr, reg, val); 481 482 return 0; 483 } 484 #endif 485 486 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) 487 { 488 struct eth_device *dev; 489 struct dw_eth_dev *priv; 490 491 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 492 if (!dev) 493 return -ENOMEM; 494 495 /* 496 * Since the priv structure contains the descriptors which need a strict 497 * buswidth alignment, memalign is used to allocate memory 498 */ 499 priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); 500 if (!priv) { 501 free(dev); 502 return -ENOMEM; 503 } 504 505 memset(dev, 0, sizeof(struct eth_device)); 506 memset(priv, 0, sizeof(struct dw_eth_dev)); 507 508 sprintf(dev->name, "mii%d", id); 509 dev->iobase = (int)base_addr; 510 dev->priv = priv; 511 512 eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); 513 514 priv->dev = dev; 515 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 516 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 517 DW_DMA_BASE_OFFSET); 518 priv->address = phy_addr; 519 520 if (mac_reset(dev) < 0) 521 return -1; 522 523 if (configure_phy(dev) < 0) { 524 printf("Phy could not be configured\n"); 525 return -1; 526 } 527 528 dev->init = dw_eth_init; 529 dev->send = dw_eth_send; 530 dev->recv = dw_eth_recv; 531 dev->halt = dw_eth_halt; 532 dev->write_hwaddr = dw_write_hwaddr; 533 534 eth_register(dev); 535 536 #if defined(CONFIG_MII) 537 miiphy_register(dev->name, dw_mii_read, dw_mii_write); 538 #endif 539 return 1; 540 } 541