1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for u-boot 10 */ 11 12 #include <common.h> 13 #include <miiphy.h> 14 #include <malloc.h> 15 #include <linux/compiler.h> 16 #include <linux/err.h> 17 #include <asm/io.h> 18 #include "designware.h" 19 20 static int configure_phy(struct eth_device *dev); 21 22 static void tx_descs_init(struct eth_device *dev) 23 { 24 struct dw_eth_dev *priv = dev->priv; 25 struct eth_dma_regs *dma_p = priv->dma_regs_p; 26 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 27 char *txbuffs = &priv->txbuffs[0]; 28 struct dmamacdescr *desc_p; 29 u32 idx; 30 31 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 32 desc_p = &desc_table_p[idx]; 33 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 34 desc_p->dmamac_next = &desc_table_p[idx + 1]; 35 36 #if defined(CONFIG_DW_ALTDESCRIPTOR) 37 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 38 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ 39 DESC_TXSTS_TXCHECKINSCTRL | \ 40 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 41 42 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 43 desc_p->dmamac_cntl = 0; 44 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 45 #else 46 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 47 desc_p->txrx_status = 0; 48 #endif 49 } 50 51 /* Correcting the last pointer of the chain */ 52 desc_p->dmamac_next = &desc_table_p[0]; 53 54 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 55 priv->tx_currdescnum = 0; 56 } 57 58 static void rx_descs_init(struct eth_device *dev) 59 { 60 struct dw_eth_dev *priv = dev->priv; 61 struct eth_dma_regs *dma_p = priv->dma_regs_p; 62 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 63 char *rxbuffs = &priv->rxbuffs[0]; 64 struct dmamacdescr *desc_p; 65 u32 idx; 66 67 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 68 desc_p = &desc_table_p[idx]; 69 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 70 desc_p->dmamac_next = &desc_table_p[idx + 1]; 71 72 desc_p->dmamac_cntl = 73 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ 74 DESC_RXCTRL_RXCHAIN; 75 76 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 77 } 78 79 /* Correcting the last pointer of the chain */ 80 desc_p->dmamac_next = &desc_table_p[0]; 81 82 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 83 priv->rx_currdescnum = 0; 84 } 85 86 static void descs_init(struct eth_device *dev) 87 { 88 tx_descs_init(dev); 89 rx_descs_init(dev); 90 } 91 92 static int mac_reset(struct eth_device *dev) 93 { 94 struct dw_eth_dev *priv = dev->priv; 95 struct eth_mac_regs *mac_p = priv->mac_regs_p; 96 struct eth_dma_regs *dma_p = priv->dma_regs_p; 97 98 ulong start; 99 int timeout = CONFIG_MACRESET_TIMEOUT; 100 101 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 102 103 if (priv->interface != PHY_INTERFACE_MODE_RGMII) 104 writel(MII_PORTSELECT, &mac_p->conf); 105 106 start = get_timer(0); 107 while (get_timer(start) < timeout) { 108 if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) 109 return 0; 110 111 /* Try again after 10usec */ 112 udelay(10); 113 }; 114 115 return -1; 116 } 117 118 static int dw_write_hwaddr(struct eth_device *dev) 119 { 120 struct dw_eth_dev *priv = dev->priv; 121 struct eth_mac_regs *mac_p = priv->mac_regs_p; 122 u32 macid_lo, macid_hi; 123 u8 *mac_id = &dev->enetaddr[0]; 124 125 macid_lo = mac_id[0] + (mac_id[1] << 8) + \ 126 (mac_id[2] << 16) + (mac_id[3] << 24); 127 macid_hi = mac_id[4] + (mac_id[5] << 8); 128 129 writel(macid_hi, &mac_p->macaddr0hi); 130 writel(macid_lo, &mac_p->macaddr0lo); 131 132 return 0; 133 } 134 135 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 136 { 137 struct dw_eth_dev *priv = dev->priv; 138 struct eth_mac_regs *mac_p = priv->mac_regs_p; 139 struct eth_dma_regs *dma_p = priv->dma_regs_p; 140 u32 conf; 141 142 if (priv->phy_configured != 1) 143 configure_phy(dev); 144 145 /* Print link status only once */ 146 if (!priv->link_printed) { 147 printf("ENET Speed is %d Mbps - %s duplex connection\n", 148 priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); 149 priv->link_printed = 1; 150 } 151 152 /* Reset ethernet hardware */ 153 if (mac_reset(dev) < 0) 154 return -1; 155 156 /* Resore the HW MAC address as it has been lost during MAC reset */ 157 dw_write_hwaddr(dev); 158 159 writel(FIXEDBURST | PRIORXTX_41 | BURST_16, 160 &dma_p->busmode); 161 162 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | 163 TXSECONDFRAME, &dma_p->opmode); 164 165 conf = FRAMEBURSTENABLE | DISABLERXOWN; 166 167 if (priv->speed != 1000) 168 conf |= MII_PORTSELECT; 169 170 if ((priv->interface != PHY_INTERFACE_MODE_MII) && 171 (priv->interface != PHY_INTERFACE_MODE_GMII)) { 172 173 if (priv->speed == 100) 174 conf |= FES_100; 175 } 176 177 if (priv->duplex == FULL) 178 conf |= FULLDPLXMODE; 179 180 writel(conf, &mac_p->conf); 181 182 descs_init(dev); 183 184 /* 185 * Start/Enable xfer at dma as well as mac level 186 */ 187 writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); 188 writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); 189 190 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 191 192 return 0; 193 } 194 195 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 196 { 197 struct dw_eth_dev *priv = dev->priv; 198 struct eth_dma_regs *dma_p = priv->dma_regs_p; 199 u32 desc_num = priv->tx_currdescnum; 200 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 201 202 /* Check if the descriptor is owned by CPU */ 203 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 204 printf("CPU not owner of tx frame\n"); 205 return -1; 206 } 207 208 memcpy((void *)desc_p->dmamac_addr, packet, length); 209 210 #if defined(CONFIG_DW_ALTDESCRIPTOR) 211 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 212 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ 213 DESC_TXCTRL_SIZE1MASK; 214 215 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 216 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 217 #else 218 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ 219 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ 220 DESC_TXCTRL_TXFIRST; 221 222 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 223 #endif 224 225 /* Test the wrap-around condition. */ 226 if (++desc_num >= CONFIG_TX_DESCR_NUM) 227 desc_num = 0; 228 229 priv->tx_currdescnum = desc_num; 230 231 /* Start the transmission */ 232 writel(POLL_DATA, &dma_p->txpolldemand); 233 234 return 0; 235 } 236 237 static int dw_eth_recv(struct eth_device *dev) 238 { 239 struct dw_eth_dev *priv = dev->priv; 240 u32 desc_num = priv->rx_currdescnum; 241 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 242 243 u32 status = desc_p->txrx_status; 244 int length = 0; 245 246 /* Check if the owner is the CPU */ 247 if (!(status & DESC_RXSTS_OWNBYDMA)) { 248 249 length = (status & DESC_RXSTS_FRMLENMSK) >> \ 250 DESC_RXSTS_FRMLENSHFT; 251 252 NetReceive(desc_p->dmamac_addr, length); 253 254 /* 255 * Make the current descriptor valid again and go to 256 * the next one 257 */ 258 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 259 260 /* Test the wrap-around condition. */ 261 if (++desc_num >= CONFIG_RX_DESCR_NUM) 262 desc_num = 0; 263 } 264 265 priv->rx_currdescnum = desc_num; 266 267 return length; 268 } 269 270 static void dw_eth_halt(struct eth_device *dev) 271 { 272 struct dw_eth_dev *priv = dev->priv; 273 274 mac_reset(dev); 275 priv->tx_currdescnum = priv->rx_currdescnum = 0; 276 } 277 278 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) 279 { 280 struct dw_eth_dev *priv = dev->priv; 281 struct eth_mac_regs *mac_p = priv->mac_regs_p; 282 ulong start; 283 u32 miiaddr; 284 int timeout = CONFIG_MDIO_TIMEOUT; 285 286 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 287 ((reg << MIIREGSHIFT) & MII_REGMSK); 288 289 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 290 291 start = get_timer(0); 292 while (get_timer(start) < timeout) { 293 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 294 *val = readl(&mac_p->miidata); 295 return 0; 296 } 297 298 /* Try again after 10usec */ 299 udelay(10); 300 }; 301 302 return -1; 303 } 304 305 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) 306 { 307 struct dw_eth_dev *priv = dev->priv; 308 struct eth_mac_regs *mac_p = priv->mac_regs_p; 309 ulong start; 310 u32 miiaddr; 311 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; 312 u16 value; 313 314 writel(val, &mac_p->miidata); 315 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 316 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 317 318 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 319 320 start = get_timer(0); 321 while (get_timer(start) < timeout) { 322 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 323 ret = 0; 324 break; 325 } 326 327 /* Try again after 10usec */ 328 udelay(10); 329 }; 330 331 /* Needed as a fix for ST-Phy */ 332 eth_mdio_read(dev, addr, reg, &value); 333 334 return ret; 335 } 336 337 #if defined(CONFIG_DW_SEARCH_PHY) 338 static int find_phy(struct eth_device *dev) 339 { 340 int phy_addr = 0; 341 u16 ctrl, oldctrl; 342 343 do { 344 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 345 oldctrl = ctrl & BMCR_ANENABLE; 346 347 ctrl ^= BMCR_ANENABLE; 348 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 349 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 350 ctrl &= BMCR_ANENABLE; 351 352 if (ctrl == oldctrl) { 353 phy_addr++; 354 } else { 355 ctrl ^= BMCR_ANENABLE; 356 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 357 358 return phy_addr; 359 } 360 } while (phy_addr < 32); 361 362 return -1; 363 } 364 #endif 365 366 static int dw_reset_phy(struct eth_device *dev) 367 { 368 struct dw_eth_dev *priv = dev->priv; 369 u16 ctrl; 370 ulong start; 371 int timeout = CONFIG_PHYRESET_TIMEOUT; 372 u32 phy_addr = priv->address; 373 374 eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); 375 376 start = get_timer(0); 377 while (get_timer(start) < timeout) { 378 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 379 if (!(ctrl & BMCR_RESET)) 380 break; 381 382 /* Try again after 10usec */ 383 udelay(10); 384 }; 385 386 if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) 387 return -1; 388 389 #ifdef CONFIG_PHY_RESET_DELAY 390 udelay(CONFIG_PHY_RESET_DELAY); 391 #endif 392 return 0; 393 } 394 395 /* 396 * Add weak default function for board specific PHY configuration 397 */ 398 int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, 399 int (*mii_write)(struct eth_device *, u8, u8, u16), 400 int dw_reset_phy(struct eth_device *)) 401 { 402 return 0; 403 } 404 405 static int configure_phy(struct eth_device *dev) 406 { 407 struct dw_eth_dev *priv = dev->priv; 408 int phy_addr; 409 u16 bmcr; 410 #if defined(CONFIG_DW_AUTONEG) 411 u16 bmsr; 412 u32 timeout; 413 ulong start; 414 #endif 415 416 #if defined(CONFIG_DW_SEARCH_PHY) 417 phy_addr = find_phy(dev); 418 if (phy_addr >= 0) 419 priv->address = phy_addr; 420 else 421 return -1; 422 #else 423 phy_addr = priv->address; 424 #endif 425 426 /* 427 * Some boards need board specific PHY initialization. This is 428 * after the main driver init code but before the auto negotiation 429 * is run. 430 */ 431 if (designware_board_phy_init(dev, phy_addr, 432 eth_mdio_write, dw_reset_phy) < 0) 433 return -1; 434 435 if (dw_reset_phy(dev) < 0) 436 return -1; 437 438 #if defined(CONFIG_DW_AUTONEG) 439 /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ 440 eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); 441 442 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 443 #else 444 bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; 445 446 #if defined(CONFIG_DW_SPEED10M) 447 bmcr &= ~BMCR_SPEED100; 448 #endif 449 #if defined(CONFIG_DW_DUPLEXHALF) 450 bmcr &= ~BMCR_FULLDPLX; 451 #endif 452 #endif 453 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) 454 return -1; 455 456 /* Read the phy status register and populate priv structure */ 457 #if defined(CONFIG_DW_AUTONEG) 458 timeout = CONFIG_AUTONEG_TIMEOUT; 459 start = get_timer(0); 460 puts("Waiting for PHY auto negotiation to complete"); 461 while (get_timer(start) < timeout) { 462 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); 463 if (bmsr & BMSR_ANEGCOMPLETE) { 464 priv->phy_configured = 1; 465 break; 466 } 467 468 /* Print dot all 1s to show progress */ 469 if ((get_timer(start) % 1000) == 0) 470 putc('.'); 471 472 /* Try again after 1msec */ 473 udelay(1000); 474 }; 475 476 if (!(bmsr & BMSR_ANEGCOMPLETE)) 477 puts(" TIMEOUT!\n"); 478 else 479 puts(" done\n"); 480 #else 481 priv->phy_configured = 1; 482 #endif 483 484 priv->speed = miiphy_speed(dev->name, phy_addr); 485 priv->duplex = miiphy_duplex(dev->name, phy_addr); 486 487 return 0; 488 } 489 490 #if defined(CONFIG_MII) 491 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) 492 { 493 struct eth_device *dev; 494 495 dev = eth_get_dev_by_name(devname); 496 if (dev) 497 eth_mdio_read(dev, addr, reg, val); 498 499 return 0; 500 } 501 502 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) 503 { 504 struct eth_device *dev; 505 506 dev = eth_get_dev_by_name(devname); 507 if (dev) 508 eth_mdio_write(dev, addr, reg, val); 509 510 return 0; 511 } 512 #endif 513 514 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) 515 { 516 struct eth_device *dev; 517 struct dw_eth_dev *priv; 518 519 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 520 if (!dev) 521 return -ENOMEM; 522 523 /* 524 * Since the priv structure contains the descriptors which need a strict 525 * buswidth alignment, memalign is used to allocate memory 526 */ 527 priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); 528 if (!priv) { 529 free(dev); 530 return -ENOMEM; 531 } 532 533 memset(dev, 0, sizeof(struct eth_device)); 534 memset(priv, 0, sizeof(struct dw_eth_dev)); 535 536 sprintf(dev->name, "mii%d", id); 537 dev->iobase = (int)base_addr; 538 dev->priv = priv; 539 540 eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); 541 542 priv->dev = dev; 543 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 544 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 545 DW_DMA_BASE_OFFSET); 546 priv->address = phy_addr; 547 priv->phy_configured = 0; 548 priv->interface = interface; 549 550 dev->init = dw_eth_init; 551 dev->send = dw_eth_send; 552 dev->recv = dw_eth_recv; 553 dev->halt = dw_eth_halt; 554 dev->write_hwaddr = dw_write_hwaddr; 555 556 eth_register(dev); 557 558 #if defined(CONFIG_MII) 559 miiphy_register(dev->name, dw_mii_read, dw_mii_write); 560 #endif 561 return 1; 562 } 563