1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * Designware ethernet IP driver for u-boot 26 */ 27 28 #include <common.h> 29 #include <miiphy.h> 30 #include <malloc.h> 31 #include <linux/err.h> 32 #include <asm/io.h> 33 #include "designware.h" 34 35 static int configure_phy(struct eth_device *dev); 36 37 static void tx_descs_init(struct eth_device *dev) 38 { 39 struct dw_eth_dev *priv = dev->priv; 40 struct eth_dma_regs *dma_p = priv->dma_regs_p; 41 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 42 char *txbuffs = &priv->txbuffs[0]; 43 struct dmamacdescr *desc_p; 44 u32 idx; 45 46 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 47 desc_p = &desc_table_p[idx]; 48 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; 49 desc_p->dmamac_next = &desc_table_p[idx + 1]; 50 51 #if defined(CONFIG_DW_ALTDESCRIPTOR) 52 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 53 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ 54 DESC_TXSTS_TXCHECKINSCTRL | \ 55 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 56 57 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 58 desc_p->dmamac_cntl = 0; 59 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 60 #else 61 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 62 desc_p->txrx_status = 0; 63 #endif 64 } 65 66 /* Correcting the last pointer of the chain */ 67 desc_p->dmamac_next = &desc_table_p[0]; 68 69 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 70 } 71 72 static void rx_descs_init(struct eth_device *dev) 73 { 74 struct dw_eth_dev *priv = dev->priv; 75 struct eth_dma_regs *dma_p = priv->dma_regs_p; 76 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 77 char *rxbuffs = &priv->rxbuffs[0]; 78 struct dmamacdescr *desc_p; 79 u32 idx; 80 81 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 82 desc_p = &desc_table_p[idx]; 83 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 84 desc_p->dmamac_next = &desc_table_p[idx + 1]; 85 86 desc_p->dmamac_cntl = 87 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ 88 DESC_RXCTRL_RXCHAIN; 89 90 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 91 } 92 93 /* Correcting the last pointer of the chain */ 94 desc_p->dmamac_next = &desc_table_p[0]; 95 96 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 97 } 98 99 static void descs_init(struct eth_device *dev) 100 { 101 tx_descs_init(dev); 102 rx_descs_init(dev); 103 } 104 105 static int mac_reset(struct eth_device *dev) 106 { 107 struct dw_eth_dev *priv = dev->priv; 108 struct eth_mac_regs *mac_p = priv->mac_regs_p; 109 struct eth_dma_regs *dma_p = priv->dma_regs_p; 110 111 int timeout = CONFIG_MACRESET_TIMEOUT; 112 113 writel(DMAMAC_SRST, &dma_p->busmode); 114 writel(MII_PORTSELECT, &mac_p->conf); 115 116 do { 117 if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) 118 return 0; 119 udelay(1000); 120 } while (timeout--); 121 122 return -1; 123 } 124 125 static int dw_write_hwaddr(struct eth_device *dev) 126 { 127 struct dw_eth_dev *priv = dev->priv; 128 struct eth_mac_regs *mac_p = priv->mac_regs_p; 129 u32 macid_lo, macid_hi; 130 u8 *mac_id = &dev->enetaddr[0]; 131 132 macid_lo = mac_id[0] + (mac_id[1] << 8) + \ 133 (mac_id[2] << 16) + (mac_id[3] << 24); 134 macid_hi = mac_id[4] + (mac_id[5] << 8); 135 136 writel(macid_hi, &mac_p->macaddr0hi); 137 writel(macid_lo, &mac_p->macaddr0lo); 138 139 return 0; 140 } 141 142 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 143 { 144 struct dw_eth_dev *priv = dev->priv; 145 struct eth_mac_regs *mac_p = priv->mac_regs_p; 146 struct eth_dma_regs *dma_p = priv->dma_regs_p; 147 u32 conf; 148 149 if (priv->phy_configured != 1) 150 configure_phy(dev); 151 152 /* Reset ethernet hardware */ 153 if (mac_reset(dev) < 0) 154 return -1; 155 156 /* Resore the HW MAC address as it has been lost during MAC reset */ 157 dw_write_hwaddr(dev); 158 159 writel(FIXEDBURST | PRIORXTX_41 | BURST_16, 160 &dma_p->busmode); 161 162 writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); 163 writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); 164 165 conf = FRAMEBURSTENABLE | DISABLERXOWN; 166 167 if (priv->speed != SPEED_1000M) 168 conf |= MII_PORTSELECT; 169 170 if (priv->duplex == FULL_DUPLEX) 171 conf |= FULLDPLXMODE; 172 173 writel(conf, &mac_p->conf); 174 175 descs_init(dev); 176 177 /* 178 * Start/Enable xfer at dma as well as mac level 179 */ 180 writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); 181 writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); 182 183 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 184 185 return 0; 186 } 187 188 static int dw_eth_send(struct eth_device *dev, volatile void *packet, 189 int length) 190 { 191 struct dw_eth_dev *priv = dev->priv; 192 struct eth_dma_regs *dma_p = priv->dma_regs_p; 193 u32 desc_num = priv->tx_currdescnum; 194 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 195 196 /* Check if the descriptor is owned by CPU */ 197 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 198 printf("CPU not owner of tx frame\n"); 199 return -1; 200 } 201 202 memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); 203 204 #if defined(CONFIG_DW_ALTDESCRIPTOR) 205 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 206 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ 207 DESC_TXCTRL_SIZE1MASK; 208 209 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 210 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 211 #else 212 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ 213 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ 214 DESC_TXCTRL_TXFIRST; 215 216 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 217 #endif 218 219 /* Test the wrap-around condition. */ 220 if (++desc_num >= CONFIG_TX_DESCR_NUM) 221 desc_num = 0; 222 223 priv->tx_currdescnum = desc_num; 224 225 /* Start the transmission */ 226 writel(POLL_DATA, &dma_p->txpolldemand); 227 228 return 0; 229 } 230 231 static int dw_eth_recv(struct eth_device *dev) 232 { 233 struct dw_eth_dev *priv = dev->priv; 234 u32 desc_num = priv->rx_currdescnum; 235 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 236 237 u32 status = desc_p->txrx_status; 238 int length = 0; 239 240 /* Check if the owner is the CPU */ 241 if (!(status & DESC_RXSTS_OWNBYDMA)) { 242 243 length = (status & DESC_RXSTS_FRMLENMSK) >> \ 244 DESC_RXSTS_FRMLENSHFT; 245 246 NetReceive(desc_p->dmamac_addr, length); 247 248 /* 249 * Make the current descriptor valid again and go to 250 * the next one 251 */ 252 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 253 254 /* Test the wrap-around condition. */ 255 if (++desc_num >= CONFIG_RX_DESCR_NUM) 256 desc_num = 0; 257 } 258 259 priv->rx_currdescnum = desc_num; 260 261 return length; 262 } 263 264 static void dw_eth_halt(struct eth_device *dev) 265 { 266 struct dw_eth_dev *priv = dev->priv; 267 268 mac_reset(dev); 269 priv->tx_currdescnum = priv->rx_currdescnum = 0; 270 } 271 272 static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) 273 { 274 struct dw_eth_dev *priv = dev->priv; 275 struct eth_mac_regs *mac_p = priv->mac_regs_p; 276 u32 miiaddr; 277 int timeout = CONFIG_MDIO_TIMEOUT; 278 279 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 280 ((reg << MIIREGSHIFT) & MII_REGMSK); 281 282 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 283 284 do { 285 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 286 *val = readl(&mac_p->miidata); 287 return 0; 288 } 289 udelay(1000); 290 } while (timeout--); 291 292 return -1; 293 } 294 295 static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) 296 { 297 struct dw_eth_dev *priv = dev->priv; 298 struct eth_mac_regs *mac_p = priv->mac_regs_p; 299 u32 miiaddr; 300 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; 301 u16 value; 302 303 writel(val, &mac_p->miidata); 304 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ 305 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 306 307 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 308 309 do { 310 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 311 ret = 0; 312 break; 313 } 314 udelay(1000); 315 } while (timeout--); 316 317 /* Needed as a fix for ST-Phy */ 318 eth_mdio_read(dev, addr, reg, &value); 319 320 return ret; 321 } 322 323 #if defined(CONFIG_DW_SEARCH_PHY) 324 static int find_phy(struct eth_device *dev) 325 { 326 int phy_addr = 0; 327 u16 ctrl, oldctrl; 328 329 do { 330 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 331 oldctrl = ctrl & BMCR_ANENABLE; 332 333 ctrl ^= BMCR_ANENABLE; 334 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 335 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 336 ctrl &= BMCR_ANENABLE; 337 338 if (ctrl == oldctrl) { 339 phy_addr++; 340 } else { 341 ctrl ^= BMCR_ANENABLE; 342 eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); 343 344 return phy_addr; 345 } 346 } while (phy_addr < 32); 347 348 return -1; 349 } 350 #endif 351 352 static int dw_reset_phy(struct eth_device *dev) 353 { 354 struct dw_eth_dev *priv = dev->priv; 355 u16 ctrl; 356 int timeout = CONFIG_PHYRESET_TIMEOUT; 357 u32 phy_addr = priv->address; 358 359 eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); 360 do { 361 eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); 362 if (!(ctrl & BMCR_RESET)) 363 break; 364 udelay(1000); 365 } while (timeout--); 366 367 if (timeout < 0) 368 return -1; 369 370 #ifdef CONFIG_PHY_RESET_DELAY 371 udelay(CONFIG_PHY_RESET_DELAY); 372 #endif 373 return 0; 374 } 375 376 static int configure_phy(struct eth_device *dev) 377 { 378 struct dw_eth_dev *priv = dev->priv; 379 int phy_addr; 380 u16 bmcr; 381 #if defined(CONFIG_DW_AUTONEG) 382 u16 bmsr; 383 u32 timeout; 384 u16 anlpar, btsr; 385 #else 386 u16 ctrl; 387 #endif 388 389 #if defined(CONFIG_DW_SEARCH_PHY) 390 phy_addr = find_phy(dev); 391 if (phy_addr >= 0) 392 priv->address = phy_addr; 393 else 394 return -1; 395 #else 396 phy_addr = priv->address; 397 #endif 398 if (dw_reset_phy(dev) < 0) 399 return -1; 400 401 #if defined(CONFIG_DW_AUTONEG) 402 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \ 403 BMCR_FULLDPLX | BMCR_SPEED1000; 404 #else 405 bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; 406 407 #if defined(CONFIG_DW_SPEED10M) 408 bmcr &= ~BMCR_SPEED100; 409 #endif 410 #if defined(CONFIG_DW_DUPLEXHALF) 411 bmcr &= ~BMCR_FULLDPLX; 412 #endif 413 #endif 414 if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) 415 return -1; 416 417 /* Read the phy status register and populate priv structure */ 418 #if defined(CONFIG_DW_AUTONEG) 419 timeout = CONFIG_AUTONEG_TIMEOUT; 420 do { 421 eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); 422 if (bmsr & BMSR_ANEGCOMPLETE) 423 break; 424 udelay(1000); 425 } while (timeout--); 426 427 eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); 428 eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); 429 430 if (bmsr & BMSR_ANEGCOMPLETE) { 431 if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 432 priv->speed = SPEED_1000M; 433 if (btsr & PHY_1000BTSR_1000FD) 434 priv->duplex = FULL_DUPLEX; 435 else 436 priv->duplex = HALF_DUPLEX; 437 } else { 438 if (anlpar & LPA_100) 439 priv->speed = SPEED_100M; 440 else 441 priv->speed = SPEED_10M; 442 443 if (anlpar & (LPA_10FULL | LPA_100FULL)) 444 priv->duplex = FULL_DUPLEX; 445 else 446 priv->duplex = HALF_DUPLEX; 447 } 448 } else 449 return -1; 450 #else 451 if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) 452 return -1; 453 454 if (ctrl & BMCR_FULLDPLX) 455 priv->duplex = FULL_DUPLEX; 456 else 457 priv->duplex = HALF_DUPLEX; 458 459 if (ctrl & BMCR_SPEED1000) 460 priv->speed = SPEED_1000M; 461 else if (ctrl & BMCR_SPEED100) 462 priv->speed = SPEED_100M; 463 else 464 priv->speed = SPEED_10M; 465 #endif 466 priv->phy_configured = 1; 467 468 return 0; 469 } 470 471 #if defined(CONFIG_MII) 472 static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) 473 { 474 struct eth_device *dev; 475 476 dev = eth_get_dev_by_name(devname); 477 if (dev) 478 eth_mdio_read(dev, addr, reg, val); 479 480 return 0; 481 } 482 483 static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) 484 { 485 struct eth_device *dev; 486 487 dev = eth_get_dev_by_name(devname); 488 if (dev) 489 eth_mdio_write(dev, addr, reg, val); 490 491 return 0; 492 } 493 #endif 494 495 int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) 496 { 497 struct eth_device *dev; 498 struct dw_eth_dev *priv; 499 500 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 501 if (!dev) 502 return -ENOMEM; 503 504 /* 505 * Since the priv structure contains the descriptors which need a strict 506 * buswidth alignment, memalign is used to allocate memory 507 */ 508 priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); 509 if (!priv) { 510 free(dev); 511 return -ENOMEM; 512 } 513 514 memset(dev, 0, sizeof(struct eth_device)); 515 memset(priv, 0, sizeof(struct dw_eth_dev)); 516 517 sprintf(dev->name, "mii%d", id); 518 dev->iobase = (int)base_addr; 519 dev->priv = priv; 520 521 eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); 522 523 priv->dev = dev; 524 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 525 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 526 DW_DMA_BASE_OFFSET); 527 priv->address = phy_addr; 528 priv->phy_configured = 0; 529 530 if (mac_reset(dev) < 0) 531 return -1; 532 533 configure_phy(dev); 534 535 dev->init = dw_eth_init; 536 dev->send = dw_eth_send; 537 dev->recv = dw_eth_recv; 538 dev->halt = dw_eth_halt; 539 dev->write_hwaddr = dw_write_hwaddr; 540 541 eth_register(dev); 542 543 #if defined(CONFIG_MII) 544 miiphy_register(dev->name, dw_mii_read, dw_mii_write); 545 #endif 546 return 1; 547 } 548