1 /* 2 * (C) Copyright 2010 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * Designware ethernet IP driver for U-Boot 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <miiphy.h> 16 #include <malloc.h> 17 #include <pci.h> 18 #include <linux/compiler.h> 19 #include <linux/err.h> 20 #include <asm/io.h> 21 #include "designware.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 26 { 27 #ifdef CONFIG_DM_ETH 28 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 29 struct eth_mac_regs *mac_p = priv->mac_regs_p; 30 #else 31 struct eth_mac_regs *mac_p = bus->priv; 32 #endif 33 ulong start; 34 u16 miiaddr; 35 int timeout = CONFIG_MDIO_TIMEOUT; 36 37 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 38 ((reg << MIIREGSHIFT) & MII_REGMSK); 39 40 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 41 42 start = get_timer(0); 43 while (get_timer(start) < timeout) { 44 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) 45 return readl(&mac_p->miidata); 46 udelay(10); 47 }; 48 49 return -ETIMEDOUT; 50 } 51 52 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 53 u16 val) 54 { 55 #ifdef CONFIG_DM_ETH 56 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); 57 struct eth_mac_regs *mac_p = priv->mac_regs_p; 58 #else 59 struct eth_mac_regs *mac_p = bus->priv; 60 #endif 61 ulong start; 62 u16 miiaddr; 63 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; 64 65 writel(val, &mac_p->miidata); 66 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | 67 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; 68 69 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); 70 71 start = get_timer(0); 72 while (get_timer(start) < timeout) { 73 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { 74 ret = 0; 75 break; 76 } 77 udelay(10); 78 }; 79 80 return ret; 81 } 82 83 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 84 static int dw_mdio_reset(struct mii_dev *bus) 85 { 86 struct udevice *dev = bus->priv; 87 struct dw_eth_dev *priv = dev_get_priv(dev); 88 struct dw_eth_pdata *pdata = dev_get_platdata(dev); 89 int ret; 90 91 if (!dm_gpio_is_valid(&priv->reset_gpio)) 92 return 0; 93 94 /* reset the phy */ 95 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 96 if (ret) 97 return ret; 98 99 udelay(pdata->reset_delays[0]); 100 101 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 102 if (ret) 103 return ret; 104 105 udelay(pdata->reset_delays[1]); 106 107 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 108 if (ret) 109 return ret; 110 111 udelay(pdata->reset_delays[2]); 112 113 return 0; 114 } 115 #endif 116 117 static int dw_mdio_init(const char *name, void *priv) 118 { 119 struct mii_dev *bus = mdio_alloc(); 120 121 if (!bus) { 122 printf("Failed to allocate MDIO bus\n"); 123 return -ENOMEM; 124 } 125 126 bus->read = dw_mdio_read; 127 bus->write = dw_mdio_write; 128 snprintf(bus->name, sizeof(bus->name), "%s", name); 129 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) 130 bus->reset = dw_mdio_reset; 131 #endif 132 133 bus->priv = priv; 134 135 return mdio_register(bus); 136 } 137 138 static void tx_descs_init(struct dw_eth_dev *priv) 139 { 140 struct eth_dma_regs *dma_p = priv->dma_regs_p; 141 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; 142 char *txbuffs = &priv->txbuffs[0]; 143 struct dmamacdescr *desc_p; 144 u32 idx; 145 146 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 147 desc_p = &desc_table_p[idx]; 148 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; 149 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 150 151 #if defined(CONFIG_DW_ALTDESCRIPTOR) 152 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | 153 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | 154 DESC_TXSTS_TXCHECKINSCTRL | 155 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); 156 157 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; 158 desc_p->dmamac_cntl = 0; 159 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); 160 #else 161 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; 162 desc_p->txrx_status = 0; 163 #endif 164 } 165 166 /* Correcting the last pointer of the chain */ 167 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 168 169 /* Flush all Tx buffer descriptors at once */ 170 flush_dcache_range((ulong)priv->tx_mac_descrtable, 171 (ulong)priv->tx_mac_descrtable + 172 sizeof(priv->tx_mac_descrtable)); 173 174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); 175 priv->tx_currdescnum = 0; 176 } 177 178 static void rx_descs_init(struct dw_eth_dev *priv) 179 { 180 struct eth_dma_regs *dma_p = priv->dma_regs_p; 181 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; 182 char *rxbuffs = &priv->rxbuffs[0]; 183 struct dmamacdescr *desc_p; 184 u32 idx; 185 186 /* Before passing buffers to GMAC we need to make sure zeros 187 * written there right after "priv" structure allocation were 188 * flushed into RAM. 189 * Otherwise there's a chance to get some of them flushed in RAM when 190 * GMAC is already pushing data to RAM via DMA. This way incoming from 191 * GMAC data will be corrupted. */ 192 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); 193 194 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 195 desc_p = &desc_table_p[idx]; 196 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; 197 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; 198 199 desc_p->dmamac_cntl = 200 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | 201 DESC_RXCTRL_RXCHAIN; 202 203 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; 204 } 205 206 /* Correcting the last pointer of the chain */ 207 desc_p->dmamac_next = (ulong)&desc_table_p[0]; 208 209 /* Flush all Rx buffer descriptors at once */ 210 flush_dcache_range((ulong)priv->rx_mac_descrtable, 211 (ulong)priv->rx_mac_descrtable + 212 sizeof(priv->rx_mac_descrtable)); 213 214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); 215 priv->rx_currdescnum = 0; 216 } 217 218 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) 219 { 220 struct eth_mac_regs *mac_p = priv->mac_regs_p; 221 u32 macid_lo, macid_hi; 222 223 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 224 (mac_id[3] << 24); 225 macid_hi = mac_id[4] + (mac_id[5] << 8); 226 227 writel(macid_hi, &mac_p->macaddr0hi); 228 writel(macid_lo, &mac_p->macaddr0lo); 229 230 return 0; 231 } 232 233 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, 234 struct phy_device *phydev) 235 { 236 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; 237 238 if (!phydev->link) { 239 printf("%s: No link.\n", phydev->dev->name); 240 return 0; 241 } 242 243 if (phydev->speed != 1000) 244 conf |= MII_PORTSELECT; 245 else 246 conf &= ~MII_PORTSELECT; 247 248 if (phydev->speed == 100) 249 conf |= FES_100; 250 251 if (phydev->duplex) 252 conf |= FULLDPLXMODE; 253 254 writel(conf, &mac_p->conf); 255 256 printf("Speed: %d, %s duplex%s\n", phydev->speed, 257 (phydev->duplex) ? "full" : "half", 258 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 259 260 return 0; 261 } 262 263 static void _dw_eth_halt(struct dw_eth_dev *priv) 264 { 265 struct eth_mac_regs *mac_p = priv->mac_regs_p; 266 struct eth_dma_regs *dma_p = priv->dma_regs_p; 267 268 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); 269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); 270 271 phy_shutdown(priv->phydev); 272 } 273 274 static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) 275 { 276 struct eth_mac_regs *mac_p = priv->mac_regs_p; 277 struct eth_dma_regs *dma_p = priv->dma_regs_p; 278 unsigned int start; 279 int ret; 280 281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); 282 283 start = get_timer(0); 284 while (readl(&dma_p->busmode) & DMAMAC_SRST) { 285 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { 286 printf("DMA reset timeout\n"); 287 return -ETIMEDOUT; 288 } 289 290 mdelay(100); 291 }; 292 293 /* 294 * Soft reset above clears HW address registers. 295 * So we have to set it here once again. 296 */ 297 _dw_write_hwaddr(priv, enetaddr); 298 299 rx_descs_init(priv); 300 tx_descs_init(priv); 301 302 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); 303 304 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE 305 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, 306 &dma_p->opmode); 307 #else 308 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, 309 &dma_p->opmode); 310 #endif 311 312 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); 313 314 #ifdef CONFIG_DW_AXI_BURST_LEN 315 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); 316 #endif 317 318 /* Start up the PHY */ 319 ret = phy_startup(priv->phydev); 320 if (ret) { 321 printf("Could not initialize PHY %s\n", 322 priv->phydev->dev->name); 323 return ret; 324 } 325 326 ret = dw_adjust_link(priv, mac_p, priv->phydev); 327 if (ret) 328 return ret; 329 330 if (!priv->phydev->link) 331 return -EIO; 332 333 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); 334 335 return 0; 336 } 337 338 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) 339 { 340 struct eth_dma_regs *dma_p = priv->dma_regs_p; 341 u32 desc_num = priv->tx_currdescnum; 342 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; 343 ulong desc_start = (ulong)desc_p; 344 ulong desc_end = desc_start + 345 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 346 ulong data_start = desc_p->dmamac_addr; 347 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 348 /* 349 * Strictly we only need to invalidate the "txrx_status" field 350 * for the following check, but on some platforms we cannot 351 * invalidate only 4 bytes, so we flush the entire descriptor, 352 * which is 16 bytes in total. This is safe because the 353 * individual descriptors in the array are each aligned to 354 * ARCH_DMA_MINALIGN and padded appropriately. 355 */ 356 invalidate_dcache_range(desc_start, desc_end); 357 358 /* Check if the descriptor is owned by CPU */ 359 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { 360 printf("CPU not owner of tx frame\n"); 361 return -EPERM; 362 } 363 364 memcpy((void *)data_start, packet, length); 365 366 /* Flush data to be sent */ 367 flush_dcache_range(data_start, data_end); 368 369 #if defined(CONFIG_DW_ALTDESCRIPTOR) 370 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; 371 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & 372 DESC_TXCTRL_SIZE1MASK; 373 374 desc_p->txrx_status &= ~(DESC_TXSTS_MSK); 375 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; 376 #else 377 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & 378 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | 379 DESC_TXCTRL_TXFIRST; 380 381 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; 382 #endif 383 384 /* Flush modified buffer descriptor */ 385 flush_dcache_range(desc_start, desc_end); 386 387 /* Test the wrap-around condition. */ 388 if (++desc_num >= CONFIG_TX_DESCR_NUM) 389 desc_num = 0; 390 391 priv->tx_currdescnum = desc_num; 392 393 /* Start the transmission */ 394 writel(POLL_DATA, &dma_p->txpolldemand); 395 396 return 0; 397 } 398 399 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) 400 { 401 u32 status, desc_num = priv->rx_currdescnum; 402 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 403 int length = -EAGAIN; 404 ulong desc_start = (ulong)desc_p; 405 ulong desc_end = desc_start + 406 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 407 ulong data_start = desc_p->dmamac_addr; 408 ulong data_end; 409 410 /* Invalidate entire buffer descriptor */ 411 invalidate_dcache_range(desc_start, desc_end); 412 413 status = desc_p->txrx_status; 414 415 /* Check if the owner is the CPU */ 416 if (!(status & DESC_RXSTS_OWNBYDMA)) { 417 418 length = (status & DESC_RXSTS_FRMLENMSK) >> 419 DESC_RXSTS_FRMLENSHFT; 420 421 /* Invalidate received data */ 422 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 423 invalidate_dcache_range(data_start, data_end); 424 *packetp = (uchar *)(ulong)desc_p->dmamac_addr; 425 } 426 427 return length; 428 } 429 430 static int _dw_free_pkt(struct dw_eth_dev *priv) 431 { 432 u32 desc_num = priv->rx_currdescnum; 433 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; 434 ulong desc_start = (ulong)desc_p; 435 ulong desc_end = desc_start + 436 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 437 438 /* 439 * Make the current descriptor valid again and go to 440 * the next one 441 */ 442 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; 443 444 /* Flush only status field - others weren't changed */ 445 flush_dcache_range(desc_start, desc_end); 446 447 /* Test the wrap-around condition. */ 448 if (++desc_num >= CONFIG_RX_DESCR_NUM) 449 desc_num = 0; 450 priv->rx_currdescnum = desc_num; 451 452 return 0; 453 } 454 455 static int dw_phy_init(struct dw_eth_dev *priv, void *dev) 456 { 457 struct phy_device *phydev; 458 int mask = 0xffffffff, ret; 459 460 #ifdef CONFIG_PHY_ADDR 461 mask = 1 << CONFIG_PHY_ADDR; 462 #endif 463 464 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 465 if (!phydev) 466 return -ENODEV; 467 468 phy_connect_dev(phydev, dev); 469 470 phydev->supported &= PHY_GBIT_FEATURES; 471 if (priv->max_speed) { 472 ret = phy_set_supported(phydev, priv->max_speed); 473 if (ret) 474 return ret; 475 } 476 phydev->advertising = phydev->supported; 477 478 priv->phydev = phydev; 479 phy_config(phydev); 480 481 return 0; 482 } 483 484 #ifndef CONFIG_DM_ETH 485 static int dw_eth_init(struct eth_device *dev, bd_t *bis) 486 { 487 return _dw_eth_init(dev->priv, dev->enetaddr); 488 } 489 490 static int dw_eth_send(struct eth_device *dev, void *packet, int length) 491 { 492 return _dw_eth_send(dev->priv, packet, length); 493 } 494 495 static int dw_eth_recv(struct eth_device *dev) 496 { 497 uchar *packet; 498 int length; 499 500 length = _dw_eth_recv(dev->priv, &packet); 501 if (length == -EAGAIN) 502 return 0; 503 net_process_received_packet(packet, length); 504 505 _dw_free_pkt(dev->priv); 506 507 return 0; 508 } 509 510 static void dw_eth_halt(struct eth_device *dev) 511 { 512 return _dw_eth_halt(dev->priv); 513 } 514 515 static int dw_write_hwaddr(struct eth_device *dev) 516 { 517 return _dw_write_hwaddr(dev->priv, dev->enetaddr); 518 } 519 520 int designware_initialize(ulong base_addr, u32 interface) 521 { 522 struct eth_device *dev; 523 struct dw_eth_dev *priv; 524 525 dev = (struct eth_device *) malloc(sizeof(struct eth_device)); 526 if (!dev) 527 return -ENOMEM; 528 529 /* 530 * Since the priv structure contains the descriptors which need a strict 531 * buswidth alignment, memalign is used to allocate memory 532 */ 533 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, 534 sizeof(struct dw_eth_dev)); 535 if (!priv) { 536 free(dev); 537 return -ENOMEM; 538 } 539 540 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { 541 printf("designware: buffers are outside DMA memory\n"); 542 return -EINVAL; 543 } 544 545 memset(dev, 0, sizeof(struct eth_device)); 546 memset(priv, 0, sizeof(struct dw_eth_dev)); 547 548 sprintf(dev->name, "dwmac.%lx", base_addr); 549 dev->iobase = (int)base_addr; 550 dev->priv = priv; 551 552 priv->dev = dev; 553 priv->mac_regs_p = (struct eth_mac_regs *)base_addr; 554 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + 555 DW_DMA_BASE_OFFSET); 556 557 dev->init = dw_eth_init; 558 dev->send = dw_eth_send; 559 dev->recv = dw_eth_recv; 560 dev->halt = dw_eth_halt; 561 dev->write_hwaddr = dw_write_hwaddr; 562 563 eth_register(dev); 564 565 priv->interface = interface; 566 567 dw_mdio_init(dev->name, priv->mac_regs_p); 568 priv->bus = miiphy_get_dev_by_name(dev->name); 569 570 return dw_phy_init(priv, dev); 571 } 572 #endif 573 574 #ifdef CONFIG_DM_ETH 575 static int designware_eth_start(struct udevice *dev) 576 { 577 struct eth_pdata *pdata = dev_get_platdata(dev); 578 579 return _dw_eth_init(dev->priv, pdata->enetaddr); 580 } 581 582 static int designware_eth_send(struct udevice *dev, void *packet, int length) 583 { 584 struct dw_eth_dev *priv = dev_get_priv(dev); 585 586 return _dw_eth_send(priv, packet, length); 587 } 588 589 static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) 590 { 591 struct dw_eth_dev *priv = dev_get_priv(dev); 592 593 return _dw_eth_recv(priv, packetp); 594 } 595 596 static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 597 int length) 598 { 599 struct dw_eth_dev *priv = dev_get_priv(dev); 600 601 return _dw_free_pkt(priv); 602 } 603 604 static void designware_eth_stop(struct udevice *dev) 605 { 606 struct dw_eth_dev *priv = dev_get_priv(dev); 607 608 return _dw_eth_halt(priv); 609 } 610 611 static int designware_eth_write_hwaddr(struct udevice *dev) 612 { 613 struct eth_pdata *pdata = dev_get_platdata(dev); 614 struct dw_eth_dev *priv = dev_get_priv(dev); 615 616 return _dw_write_hwaddr(priv, pdata->enetaddr); 617 } 618 619 static int designware_eth_bind(struct udevice *dev) 620 { 621 #ifdef CONFIG_DM_PCI 622 static int num_cards; 623 char name[20]; 624 625 /* Create a unique device name for PCI type devices */ 626 if (device_is_on_pci_bus(dev)) { 627 sprintf(name, "eth_designware#%u", num_cards++); 628 device_set_name(dev, name); 629 } 630 #endif 631 632 return 0; 633 } 634 635 int designware_eth_probe(struct udevice *dev) 636 { 637 struct eth_pdata *pdata = dev_get_platdata(dev); 638 struct dw_eth_dev *priv = dev_get_priv(dev); 639 u32 iobase = pdata->iobase; 640 ulong ioaddr; 641 int ret; 642 643 #ifdef CONFIG_DM_PCI 644 /* 645 * If we are on PCI bus, either directly attached to a PCI root port, 646 * or via a PCI bridge, fill in platdata before we probe the hardware. 647 */ 648 if (device_is_on_pci_bus(dev)) { 649 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); 650 iobase &= PCI_BASE_ADDRESS_MEM_MASK; 651 iobase = dm_pci_mem_to_phys(dev, iobase); 652 653 pdata->iobase = iobase; 654 pdata->phy_interface = PHY_INTERFACE_MODE_RMII; 655 } 656 #endif 657 658 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); 659 ioaddr = iobase; 660 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; 661 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); 662 priv->interface = pdata->phy_interface; 663 priv->max_speed = pdata->max_speed; 664 665 dw_mdio_init(dev->name, dev); 666 priv->bus = miiphy_get_dev_by_name(dev->name); 667 668 ret = dw_phy_init(priv, dev); 669 debug("%s, ret=%d\n", __func__, ret); 670 671 return ret; 672 } 673 674 static int designware_eth_remove(struct udevice *dev) 675 { 676 struct dw_eth_dev *priv = dev_get_priv(dev); 677 678 free(priv->phydev); 679 mdio_unregister(priv->bus); 680 mdio_free(priv->bus); 681 682 return 0; 683 } 684 685 const struct eth_ops designware_eth_ops = { 686 .start = designware_eth_start, 687 .send = designware_eth_send, 688 .recv = designware_eth_recv, 689 .free_pkt = designware_eth_free_pkt, 690 .stop = designware_eth_stop, 691 .write_hwaddr = designware_eth_write_hwaddr, 692 }; 693 694 int designware_eth_ofdata_to_platdata(struct udevice *dev) 695 { 696 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 697 #ifdef CONFIG_DM_GPIO 698 struct dw_eth_dev *priv = dev_get_priv(dev); 699 #endif 700 struct eth_pdata *pdata = &dw_pdata->eth_pdata; 701 const char *phy_mode; 702 const fdt32_t *cell; 703 #ifdef CONFIG_DM_GPIO 704 int reset_flags = GPIOD_IS_OUT; 705 #endif 706 int ret = 0; 707 708 pdata->iobase = dev_get_addr(dev); 709 pdata->phy_interface = -1; 710 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 711 if (phy_mode) 712 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 713 if (pdata->phy_interface == -1) { 714 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 715 return -EINVAL; 716 } 717 718 pdata->max_speed = 0; 719 cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL); 720 if (cell) 721 pdata->max_speed = fdt32_to_cpu(*cell); 722 723 #ifdef CONFIG_DM_GPIO 724 if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, 725 "snps,reset-active-low")) 726 reset_flags |= GPIOD_ACTIVE_LOW; 727 728 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 729 &priv->reset_gpio, reset_flags); 730 if (ret == 0) { 731 ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, 732 "snps,reset-delays-us", dw_pdata->reset_delays, 3); 733 } else if (ret == -ENOENT) { 734 ret = 0; 735 } 736 #endif 737 738 return ret; 739 } 740 741 static const struct udevice_id designware_eth_ids[] = { 742 { .compatible = "allwinner,sun7i-a20-gmac" }, 743 { .compatible = "altr,socfpga-stmmac" }, 744 { .compatible = "amlogic,meson6-dwmac" }, 745 { } 746 }; 747 748 U_BOOT_DRIVER(eth_designware) = { 749 .name = "eth_designware", 750 .id = UCLASS_ETH, 751 .of_match = designware_eth_ids, 752 .ofdata_to_platdata = designware_eth_ofdata_to_platdata, 753 .bind = designware_eth_bind, 754 .probe = designware_eth_probe, 755 .remove = designware_eth_remove, 756 .ops = &designware_eth_ops, 757 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 758 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), 759 .flags = DM_FLAG_ALLOC_PRIV_DMA, 760 }; 761 762 static struct pci_device_id supported[] = { 763 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, 764 { } 765 }; 766 767 U_BOOT_PCI_DEVICE(eth_designware, supported); 768 #endif 769