1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on: mach-davinci/emac_defs.h 5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #ifndef _DAVINCI_EMAC_H_ 23 #define _DAVINCI_EMAC_H_ 24 /* Ethernet Min/Max packet size */ 25 #define EMAC_MIN_ETHERNET_PKT_SIZE 60 26 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518 27 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ 28 #define EMAC_PKT_ALIGN 18 29 30 /* Number of RX packet buffers 31 * NOTE: Only 1 buffer supported as of now 32 */ 33 #define EMAC_MAX_RX_BUFFERS 10 34 35 36 /*********************************************** 37 ******** Internally used macros *************** 38 ***********************************************/ 39 40 #define EMAC_CH_TX 1 41 #define EMAC_CH_RX 0 42 43 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and 44 * reserve space for 64 descriptors max 45 */ 46 #define EMAC_RX_DESC_BASE 0x0 47 #define EMAC_TX_DESC_BASE 0x1000 48 49 /* EMAC Teardown value */ 50 #define EMAC_TEARDOWN_VALUE 0xfffffffc 51 52 /* MII Status Register */ 53 #define MII_STATUS_REG 1 54 55 /* Number of statistics registers */ 56 #define EMAC_NUM_STATS 36 57 58 59 /* EMAC Descriptor */ 60 typedef volatile struct _emac_desc 61 { 62 u_int32_t next; /* Pointer to next descriptor 63 in chain */ 64 u_int8_t *buffer; /* Pointer to data buffer */ 65 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ 66 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ 67 } emac_desc; 68 69 /* CPPI bit positions */ 70 #define EMAC_CPPI_SOP_BIT (0x80000000) 71 #define EMAC_CPPI_EOP_BIT (0x40000000) 72 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) 73 #define EMAC_CPPI_EOQ_BIT (0x10000000) 74 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) 75 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000) 76 77 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) 78 79 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) 80 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) 81 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) 82 #define EMAC_MACCONTROL_GIGFORCE (1 << 17) 83 #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) 84 85 #define EMAC_MAC_ADDR_MATCH (1 << 19) 86 #define EMAC_MAC_ADDR_IS_VALID (1 << 20) 87 88 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) 89 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) 90 91 92 #define MDIO_CONTROL_IDLE (0x80000000) 93 #define MDIO_CONTROL_ENABLE (0x40000000) 94 #define MDIO_CONTROL_FAULT_ENABLE (0x40000) 95 #define MDIO_CONTROL_FAULT (0x80000) 96 #define MDIO_USERACCESS0_GO (0x80000000) 97 #define MDIO_USERACCESS0_WRITE_READ (0x0) 98 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) 99 #define MDIO_USERACCESS0_ACK (0x20000000) 100 101 /* Ethernet MAC Registers Structure */ 102 typedef struct { 103 dv_reg TXIDVER; 104 dv_reg TXCONTROL; 105 dv_reg TXTEARDOWN; 106 u_int8_t RSVD0[4]; 107 dv_reg RXIDVER; 108 dv_reg RXCONTROL; 109 dv_reg RXTEARDOWN; 110 u_int8_t RSVD1[100]; 111 dv_reg TXINTSTATRAW; 112 dv_reg TXINTSTATMASKED; 113 dv_reg TXINTMASKSET; 114 dv_reg TXINTMASKCLEAR; 115 dv_reg MACINVECTOR; 116 u_int8_t RSVD2[12]; 117 dv_reg RXINTSTATRAW; 118 dv_reg RXINTSTATMASKED; 119 dv_reg RXINTMASKSET; 120 dv_reg RXINTMASKCLEAR; 121 dv_reg MACINTSTATRAW; 122 dv_reg MACINTSTATMASKED; 123 dv_reg MACINTMASKSET; 124 dv_reg MACINTMASKCLEAR; 125 u_int8_t RSVD3[64]; 126 dv_reg RXMBPENABLE; 127 dv_reg RXUNICASTSET; 128 dv_reg RXUNICASTCLEAR; 129 dv_reg RXMAXLEN; 130 dv_reg RXBUFFEROFFSET; 131 dv_reg RXFILTERLOWTHRESH; 132 u_int8_t RSVD4[8]; 133 dv_reg RX0FLOWTHRESH; 134 dv_reg RX1FLOWTHRESH; 135 dv_reg RX2FLOWTHRESH; 136 dv_reg RX3FLOWTHRESH; 137 dv_reg RX4FLOWTHRESH; 138 dv_reg RX5FLOWTHRESH; 139 dv_reg RX6FLOWTHRESH; 140 dv_reg RX7FLOWTHRESH; 141 dv_reg RX0FREEBUFFER; 142 dv_reg RX1FREEBUFFER; 143 dv_reg RX2FREEBUFFER; 144 dv_reg RX3FREEBUFFER; 145 dv_reg RX4FREEBUFFER; 146 dv_reg RX5FREEBUFFER; 147 dv_reg RX6FREEBUFFER; 148 dv_reg RX7FREEBUFFER; 149 dv_reg MACCONTROL; 150 dv_reg MACSTATUS; 151 dv_reg EMCONTROL; 152 dv_reg FIFOCONTROL; 153 dv_reg MACCONFIG; 154 dv_reg SOFTRESET; 155 u_int8_t RSVD5[88]; 156 dv_reg MACSRCADDRLO; 157 dv_reg MACSRCADDRHI; 158 dv_reg MACHASH1; 159 dv_reg MACHASH2; 160 dv_reg BOFFTEST; 161 dv_reg TPACETEST; 162 dv_reg RXPAUSE; 163 dv_reg TXPAUSE; 164 u_int8_t RSVD6[16]; 165 dv_reg RXGOODFRAMES; 166 dv_reg RXBCASTFRAMES; 167 dv_reg RXMCASTFRAMES; 168 dv_reg RXPAUSEFRAMES; 169 dv_reg RXCRCERRORS; 170 dv_reg RXALIGNCODEERRORS; 171 dv_reg RXOVERSIZED; 172 dv_reg RXJABBER; 173 dv_reg RXUNDERSIZED; 174 dv_reg RXFRAGMENTS; 175 dv_reg RXFILTERED; 176 dv_reg RXQOSFILTERED; 177 dv_reg RXOCTETS; 178 dv_reg TXGOODFRAMES; 179 dv_reg TXBCASTFRAMES; 180 dv_reg TXMCASTFRAMES; 181 dv_reg TXPAUSEFRAMES; 182 dv_reg TXDEFERRED; 183 dv_reg TXCOLLISION; 184 dv_reg TXSINGLECOLL; 185 dv_reg TXMULTICOLL; 186 dv_reg TXEXCESSIVECOLL; 187 dv_reg TXLATECOLL; 188 dv_reg TXUNDERRUN; 189 dv_reg TXCARRIERSENSE; 190 dv_reg TXOCTETS; 191 dv_reg FRAME64; 192 dv_reg FRAME65T127; 193 dv_reg FRAME128T255; 194 dv_reg FRAME256T511; 195 dv_reg FRAME512T1023; 196 dv_reg FRAME1024TUP; 197 dv_reg NETOCTETS; 198 dv_reg RXSOFOVERRUNS; 199 dv_reg RXMOFOVERRUNS; 200 dv_reg RXDMAOVERRUNS; 201 u_int8_t RSVD7[624]; 202 dv_reg MACADDRLO; 203 dv_reg MACADDRHI; 204 dv_reg MACINDEX; 205 u_int8_t RSVD8[244]; 206 dv_reg TX0HDP; 207 dv_reg TX1HDP; 208 dv_reg TX2HDP; 209 dv_reg TX3HDP; 210 dv_reg TX4HDP; 211 dv_reg TX5HDP; 212 dv_reg TX6HDP; 213 dv_reg TX7HDP; 214 dv_reg RX0HDP; 215 dv_reg RX1HDP; 216 dv_reg RX2HDP; 217 dv_reg RX3HDP; 218 dv_reg RX4HDP; 219 dv_reg RX5HDP; 220 dv_reg RX6HDP; 221 dv_reg RX7HDP; 222 dv_reg TX0CP; 223 dv_reg TX1CP; 224 dv_reg TX2CP; 225 dv_reg TX3CP; 226 dv_reg TX4CP; 227 dv_reg TX5CP; 228 dv_reg TX6CP; 229 dv_reg TX7CP; 230 dv_reg RX0CP; 231 dv_reg RX1CP; 232 dv_reg RX2CP; 233 dv_reg RX3CP; 234 dv_reg RX4CP; 235 dv_reg RX5CP; 236 dv_reg RX6CP; 237 dv_reg RX7CP; 238 } emac_regs; 239 240 /* EMAC Wrapper Registers Structure */ 241 typedef struct { 242 #ifdef DAVINCI_EMAC_VERSION2 243 dv_reg idver; 244 dv_reg softrst; 245 dv_reg emctrl; 246 dv_reg c0rxthreshen; 247 dv_reg c0rxen; 248 dv_reg c0txen; 249 dv_reg c0miscen; 250 dv_reg c1rxthreshen; 251 dv_reg c1rxen; 252 dv_reg c1txen; 253 dv_reg c1miscen; 254 dv_reg c2rxthreshen; 255 dv_reg c2rxen; 256 dv_reg c2txen; 257 dv_reg c2miscen; 258 dv_reg c0rxthreshstat; 259 dv_reg c0rxstat; 260 dv_reg c0txstat; 261 dv_reg c0miscstat; 262 dv_reg c1rxthreshstat; 263 dv_reg c1rxstat; 264 dv_reg c1txstat; 265 dv_reg c1miscstat; 266 dv_reg c2rxthreshstat; 267 dv_reg c2rxstat; 268 dv_reg c2txstat; 269 dv_reg c2miscstat; 270 dv_reg c0rximax; 271 dv_reg c0tximax; 272 dv_reg c1rximax; 273 dv_reg c1tximax; 274 dv_reg c2rximax; 275 dv_reg c2tximax; 276 #else 277 u_int8_t RSVD0[4100]; 278 dv_reg EWCTL; 279 dv_reg EWINTTCNT; 280 #endif 281 } ewrap_regs; 282 283 /* EMAC MDIO Registers Structure */ 284 typedef struct { 285 dv_reg VERSION; 286 dv_reg CONTROL; 287 dv_reg ALIVE; 288 dv_reg LINK; 289 dv_reg LINKINTRAW; 290 dv_reg LINKINTMASKED; 291 u_int8_t RSVD0[8]; 292 dv_reg USERINTRAW; 293 dv_reg USERINTMASKED; 294 dv_reg USERINTMASKSET; 295 dv_reg USERINTMASKCLEAR; 296 u_int8_t RSVD1[80]; 297 dv_reg USERACCESS0; 298 dv_reg USERPHYSEL0; 299 dv_reg USERACCESS1; 300 dv_reg USERPHYSEL1; 301 } mdio_regs; 302 303 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); 304 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); 305 306 typedef struct { 307 char name[64]; 308 int (*init)(int phy_addr); 309 int (*is_phy_connected)(int phy_addr); 310 int (*get_link_speed)(int phy_addr); 311 int (*auto_negotiate)(int phy_addr); 312 } phy_t; 313 314 #endif /* _DAVINCI_EMAC_H_ */ 315