1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 * 21 * Modifications: 22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 23 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 24 */ 25 #include <common.h> 26 #include <command.h> 27 #include <net.h> 28 #include <miiphy.h> 29 #include <malloc.h> 30 #include <linux/compiler.h> 31 #include <asm/arch/emac_defs.h> 32 #include <asm/io.h> 33 #include "davinci_emac.h" 34 35 unsigned int emac_dbg = 0; 36 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 37 38 #ifdef EMAC_HW_RAM_ADDR 39 static inline unsigned long BD_TO_HW(unsigned long x) 40 { 41 if (x == 0) 42 return 0; 43 44 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; 45 } 46 47 static inline unsigned long HW_TO_BD(unsigned long x) 48 { 49 if (x == 0) 50 return 0; 51 52 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; 53 } 54 #else 55 #define BD_TO_HW(x) (x) 56 #define HW_TO_BD(x) (x) 57 #endif 58 59 #ifdef DAVINCI_EMAC_GIG_ENABLE 60 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) 61 #else 62 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ 63 #endif 64 65 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) 66 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ 67 EMAC_MDIO_CLOCK_FREQ) - 1) 68 #endif 69 70 static void davinci_eth_mdio_enable(void); 71 72 static int gen_init_phy(int phy_addr); 73 static int gen_is_phy_connected(int phy_addr); 74 static int gen_get_link_speed(int phy_addr); 75 static int gen_auto_negotiate(int phy_addr); 76 77 void eth_mdio_enable(void) 78 { 79 davinci_eth_mdio_enable(); 80 } 81 82 /* EMAC Addresses */ 83 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 84 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 85 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 86 87 /* EMAC descriptors */ 88 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 89 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 90 static volatile emac_desc *emac_rx_active_head = 0; 91 static volatile emac_desc *emac_rx_active_tail = 0; 92 static int emac_rx_queue_active = 0; 93 94 /* Receive packet buffers */ 95 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] 96 __aligned(ARCH_DMA_MINALIGN); 97 98 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 99 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 100 #endif 101 102 /* PHY address for a discovered PHY (0xff - not found) */ 103 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 104 105 /* number of PHY found active */ 106 static u_int8_t num_phy; 107 108 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 109 110 static inline void davinci_flush_rx_descs(void) 111 { 112 /* flush the whole RX descs area */ 113 flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 114 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 115 } 116 117 static inline void davinci_invalidate_rx_descs(void) 118 { 119 /* invalidate the whole RX descs area */ 120 invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 121 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 122 } 123 124 static inline void davinci_flush_desc(emac_desc *desc) 125 { 126 flush_dcache_range((unsigned long)desc, 127 (unsigned long)desc + sizeof(*desc)); 128 } 129 130 static int davinci_eth_set_mac_addr(struct eth_device *dev) 131 { 132 unsigned long mac_hi; 133 unsigned long mac_lo; 134 135 /* 136 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 137 * receive) 138 * Using channel 0 only - other channels are disabled 139 * */ 140 writel(0, &adap_emac->MACINDEX); 141 mac_hi = (dev->enetaddr[3] << 24) | 142 (dev->enetaddr[2] << 16) | 143 (dev->enetaddr[1] << 8) | 144 (dev->enetaddr[0]); 145 mac_lo = (dev->enetaddr[5] << 8) | 146 (dev->enetaddr[4]); 147 148 writel(mac_hi, &adap_emac->MACADDRHI); 149 #if defined(DAVINCI_EMAC_VERSION2) 150 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 151 &adap_emac->MACADDRLO); 152 #else 153 writel(mac_lo, &adap_emac->MACADDRLO); 154 #endif 155 156 writel(0, &adap_emac->MACHASH1); 157 writel(0, &adap_emac->MACHASH2); 158 159 /* Set source MAC address - REQUIRED */ 160 writel(mac_hi, &adap_emac->MACSRCADDRHI); 161 writel(mac_lo, &adap_emac->MACSRCADDRLO); 162 163 164 return 0; 165 } 166 167 static void davinci_eth_mdio_enable(void) 168 { 169 u_int32_t clkdiv; 170 171 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 172 173 writel((clkdiv & 0xff) | 174 MDIO_CONTROL_ENABLE | 175 MDIO_CONTROL_FAULT | 176 MDIO_CONTROL_FAULT_ENABLE, 177 &adap_mdio->CONTROL); 178 179 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 180 ; 181 } 182 183 /* 184 * Tries to find an active connected PHY. Returns 1 if address if found. 185 * If no active PHY (or more than one PHY) found returns 0. 186 * Sets active_phy_addr variable. 187 */ 188 static int davinci_eth_phy_detect(void) 189 { 190 u_int32_t phy_act_state; 191 int i; 192 int j; 193 unsigned int count = 0; 194 195 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) 196 active_phy_addr[i] = 0xff; 197 198 udelay(1000); 199 phy_act_state = readl(&adap_mdio->ALIVE); 200 201 if (phy_act_state == 0) 202 return 0; /* No active PHYs */ 203 204 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 205 206 for (i = 0, j = 0; i < 32; i++) 207 if (phy_act_state & (1 << i)) { 208 count++; 209 if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { 210 active_phy_addr[j++] = i; 211 } else { 212 printf("%s: to many PHYs detected.\n", 213 __func__); 214 count = 0; 215 break; 216 } 217 } 218 219 num_phy = count; 220 221 return count; 222 } 223 224 225 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 226 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 227 { 228 int tmp; 229 230 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 231 ; 232 233 writel(MDIO_USERACCESS0_GO | 234 MDIO_USERACCESS0_WRITE_READ | 235 ((reg_num & 0x1f) << 21) | 236 ((phy_addr & 0x1f) << 16), 237 &adap_mdio->USERACCESS0); 238 239 /* Wait for command to complete */ 240 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 241 ; 242 243 if (tmp & MDIO_USERACCESS0_ACK) { 244 *data = tmp & 0xffff; 245 return(1); 246 } 247 248 *data = -1; 249 return(0); 250 } 251 252 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 253 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 254 { 255 256 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 257 ; 258 259 writel(MDIO_USERACCESS0_GO | 260 MDIO_USERACCESS0_WRITE_WRITE | 261 ((reg_num & 0x1f) << 21) | 262 ((phy_addr & 0x1f) << 16) | 263 (data & 0xffff), 264 &adap_mdio->USERACCESS0); 265 266 /* Wait for command to complete */ 267 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 268 ; 269 270 return(1); 271 } 272 273 /* PHY functions for a generic PHY */ 274 static int gen_init_phy(int phy_addr) 275 { 276 int ret = 1; 277 278 if (gen_get_link_speed(phy_addr)) { 279 /* Try another time */ 280 ret = gen_get_link_speed(phy_addr); 281 } 282 283 return(ret); 284 } 285 286 static int gen_is_phy_connected(int phy_addr) 287 { 288 u_int16_t dummy; 289 290 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); 291 } 292 293 static int get_active_phy(void) 294 { 295 int i; 296 297 for (i = 0; i < num_phy; i++) 298 if (phy[i].get_link_speed(active_phy_addr[i])) 299 return i; 300 301 return -1; /* Return error if no link */ 302 } 303 304 static int gen_get_link_speed(int phy_addr) 305 { 306 u_int16_t tmp; 307 308 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 309 (tmp & 0x04)) { 310 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 311 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 312 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 313 314 /* Speed doesn't matter, there is no setting for it in EMAC. */ 315 if (tmp & (LPA_100FULL | LPA_10FULL)) { 316 /* set EMAC for Full Duplex */ 317 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 318 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 319 &adap_emac->MACCONTROL); 320 } else { 321 /*set EMAC for Half Duplex */ 322 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 323 &adap_emac->MACCONTROL); 324 } 325 326 if (tmp & (LPA_100FULL | LPA_100HALF)) 327 writel(readl(&adap_emac->MACCONTROL) | 328 EMAC_MACCONTROL_RMIISPEED_100, 329 &adap_emac->MACCONTROL); 330 else 331 writel(readl(&adap_emac->MACCONTROL) & 332 ~EMAC_MACCONTROL_RMIISPEED_100, 333 &adap_emac->MACCONTROL); 334 #endif 335 return(1); 336 } 337 338 return(0); 339 } 340 341 static int gen_auto_negotiate(int phy_addr) 342 { 343 u_int16_t tmp; 344 u_int16_t val; 345 unsigned long cntr = 0; 346 347 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 348 return 0; 349 350 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | 351 BMCR_SPEED100; 352 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 353 354 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) 355 return 0; 356 357 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | 358 ADVERTISE_10HALF); 359 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); 360 361 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 362 return(0); 363 364 /* Restart Auto_negotiation */ 365 tmp |= BMCR_ANRESTART; 366 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 367 368 /*check AutoNegotiate complete */ 369 do { 370 udelay(40000); 371 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 372 return 0; 373 374 if (tmp & BMSR_ANEGCOMPLETE) 375 break; 376 377 cntr++; 378 } while (cntr < 200); 379 380 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 381 return(0); 382 383 if (!(tmp & BMSR_ANEGCOMPLETE)) 384 return(0); 385 386 return(gen_get_link_speed(phy_addr)); 387 } 388 /* End of generic PHY functions */ 389 390 391 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 392 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) 393 { 394 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); 395 } 396 397 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) 398 { 399 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 400 } 401 #endif 402 403 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) 404 { 405 u_int16_t data; 406 407 if (davinci_eth_phy_read(phy_addr, 0, &data)) { 408 if (data & (1 << 6)) { /* speed selection MSB */ 409 /* 410 * Check if link detected is giga-bit 411 * If Gigabit mode detected, enable gigbit in MAC 412 */ 413 writel(readl(&adap_emac->MACCONTROL) | 414 EMAC_MACCONTROL_GIGFORCE | 415 EMAC_MACCONTROL_GIGABIT_ENABLE, 416 &adap_emac->MACCONTROL); 417 } 418 } 419 } 420 421 /* Eth device open */ 422 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 423 { 424 dv_reg_p addr; 425 u_int32_t clkdiv, cnt; 426 volatile emac_desc *rx_desc; 427 int index; 428 429 debug_emac("+ emac_open\n"); 430 431 /* Reset EMAC module and disable interrupts in wrapper */ 432 writel(1, &adap_emac->SOFTRESET); 433 while (readl(&adap_emac->SOFTRESET) != 0) 434 ; 435 #if defined(DAVINCI_EMAC_VERSION2) 436 writel(1, &adap_ewrap->softrst); 437 while (readl(&adap_ewrap->softrst) != 0) 438 ; 439 #else 440 writel(0, &adap_ewrap->EWCTL); 441 for (cnt = 0; cnt < 5; cnt++) { 442 clkdiv = readl(&adap_ewrap->EWCTL); 443 } 444 #endif 445 446 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 447 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 448 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 449 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 450 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 451 #endif 452 rx_desc = emac_rx_desc; 453 454 writel(1, &adap_emac->TXCONTROL); 455 writel(1, &adap_emac->RXCONTROL); 456 457 davinci_eth_set_mac_addr(dev); 458 459 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 460 addr = &adap_emac->TX0HDP; 461 for(cnt = 0; cnt < 16; cnt++) 462 writel(0, addr++); 463 464 addr = &adap_emac->RX0HDP; 465 for(cnt = 0; cnt < 16; cnt++) 466 writel(0, addr++); 467 468 /* Clear Statistics (do this before setting MacControl register) */ 469 addr = &adap_emac->RXGOODFRAMES; 470 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 471 writel(0, addr++); 472 473 /* No multicast addressing */ 474 writel(0, &adap_emac->MACHASH1); 475 writel(0, &adap_emac->MACHASH2); 476 477 /* Create RX queue and set receive process in place */ 478 emac_rx_active_head = emac_rx_desc; 479 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 480 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); 481 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; 482 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 483 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 484 rx_desc++; 485 } 486 487 /* Finalize the rx desc list */ 488 rx_desc--; 489 rx_desc->next = 0; 490 emac_rx_active_tail = rx_desc; 491 emac_rx_queue_active = 1; 492 493 davinci_flush_rx_descs(); 494 495 /* Enable TX/RX */ 496 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 497 writel(0, &adap_emac->RXBUFFEROFFSET); 498 499 /* 500 * No fancy configs - Use this for promiscous debug 501 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 502 */ 503 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 504 505 /* Enable ch 0 only */ 506 writel(1, &adap_emac->RXUNICASTSET); 507 508 /* Enable MII interface and Full duplex mode */ 509 #if defined(CONFIG_SOC_DA8XX) || \ 510 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) 511 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 512 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 513 EMAC_MACCONTROL_RMIISPEED_100), 514 &adap_emac->MACCONTROL); 515 #else 516 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 517 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 518 &adap_emac->MACCONTROL); 519 #endif 520 521 /* Init MDIO & get link state */ 522 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 523 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 524 &adap_mdio->CONTROL); 525 526 /* We need to wait for MDIO to start */ 527 udelay(1000); 528 529 index = get_active_phy(); 530 if (index == -1) 531 return(0); 532 533 emac_gigabit_enable(active_phy_addr[index]); 534 535 /* Start receive process */ 536 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); 537 538 debug_emac("- emac_open\n"); 539 540 return(1); 541 } 542 543 /* EMAC Channel Teardown */ 544 static void davinci_eth_ch_teardown(int ch) 545 { 546 dv_reg dly = 0xff; 547 dv_reg cnt; 548 549 debug_emac("+ emac_ch_teardown\n"); 550 551 if (ch == EMAC_CH_TX) { 552 /* Init TX channel teardown */ 553 writel(0, &adap_emac->TXTEARDOWN); 554 do { 555 /* 556 * Wait here for Tx teardown completion interrupt to 557 * occur. Note: A task delay can be called here to pend 558 * rather than occupying CPU cycles - anyway it has 559 * been found that teardown takes very few cpu cycles 560 * and does not affect functionality 561 */ 562 dly--; 563 udelay(1); 564 if (dly == 0) 565 break; 566 cnt = readl(&adap_emac->TX0CP); 567 } while (cnt != 0xfffffffc); 568 writel(cnt, &adap_emac->TX0CP); 569 writel(0, &adap_emac->TX0HDP); 570 } else { 571 /* Init RX channel teardown */ 572 writel(0, &adap_emac->RXTEARDOWN); 573 do { 574 /* 575 * Wait here for Rx teardown completion interrupt to 576 * occur. Note: A task delay can be called here to pend 577 * rather than occupying CPU cycles - anyway it has 578 * been found that teardown takes very few cpu cycles 579 * and does not affect functionality 580 */ 581 dly--; 582 udelay(1); 583 if (dly == 0) 584 break; 585 cnt = readl(&adap_emac->RX0CP); 586 } while (cnt != 0xfffffffc); 587 writel(cnt, &adap_emac->RX0CP); 588 writel(0, &adap_emac->RX0HDP); 589 } 590 591 debug_emac("- emac_ch_teardown\n"); 592 } 593 594 /* Eth device close */ 595 static void davinci_eth_close(struct eth_device *dev) 596 { 597 debug_emac("+ emac_close\n"); 598 599 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 600 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 601 602 /* Reset EMAC module and disable interrupts in wrapper */ 603 writel(1, &adap_emac->SOFTRESET); 604 #if defined(DAVINCI_EMAC_VERSION2) 605 writel(1, &adap_ewrap->softrst); 606 #else 607 writel(0, &adap_ewrap->EWCTL); 608 #endif 609 610 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 611 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 612 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 613 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 614 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 615 #endif 616 debug_emac("- emac_close\n"); 617 } 618 619 static int tx_send_loop = 0; 620 621 /* 622 * This function sends a single packet on the network and returns 623 * positive number (number of bytes transmitted) or negative for error 624 */ 625 static int davinci_eth_send_packet (struct eth_device *dev, 626 void *packet, int length) 627 { 628 int ret_status = -1; 629 int index; 630 tx_send_loop = 0; 631 632 index = get_active_phy(); 633 if (index == -1) { 634 printf(" WARN: emac_send_packet: No link\n"); 635 return (ret_status); 636 } 637 638 emac_gigabit_enable(active_phy_addr[index]); 639 640 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 641 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 642 length = EMAC_MIN_ETHERNET_PKT_SIZE; 643 } 644 645 /* Populate the TX descriptor */ 646 emac_tx_desc->next = 0; 647 emac_tx_desc->buffer = (u_int8_t *) packet; 648 emac_tx_desc->buff_off_len = (length & 0xffff); 649 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 650 EMAC_CPPI_SOP_BIT | 651 EMAC_CPPI_OWNERSHIP_BIT | 652 EMAC_CPPI_EOP_BIT); 653 654 flush_dcache_range((unsigned long)packet, 655 (unsigned long)packet + length); 656 davinci_flush_desc(emac_tx_desc); 657 658 /* Send the packet */ 659 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); 660 661 /* Wait for packet to complete or link down */ 662 while (1) { 663 if (!phy[index].get_link_speed(active_phy_addr[index])) { 664 davinci_eth_ch_teardown (EMAC_CH_TX); 665 return (ret_status); 666 } 667 668 emac_gigabit_enable(active_phy_addr[index]); 669 670 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 671 ret_status = length; 672 break; 673 } 674 tx_send_loop++; 675 } 676 677 return (ret_status); 678 } 679 680 /* 681 * This function handles receipt of a packet from the network 682 */ 683 static int davinci_eth_rcv_packet (struct eth_device *dev) 684 { 685 volatile emac_desc *rx_curr_desc; 686 volatile emac_desc *curr_desc; 687 volatile emac_desc *tail_desc; 688 int status, ret = -1; 689 690 davinci_invalidate_rx_descs(); 691 692 rx_curr_desc = emac_rx_active_head; 693 status = rx_curr_desc->pkt_flag_len; 694 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { 695 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 696 /* Error in packet - discard it and requeue desc */ 697 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 698 } else { 699 unsigned long tmp = (unsigned long)rx_curr_desc->buffer; 700 701 invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); 702 NetReceive (rx_curr_desc->buffer, 703 (rx_curr_desc->buff_off_len & 0xffff)); 704 ret = rx_curr_desc->buff_off_len & 0xffff; 705 } 706 707 /* Ack received packet descriptor */ 708 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); 709 curr_desc = rx_curr_desc; 710 emac_rx_active_head = 711 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); 712 713 if (status & EMAC_CPPI_EOQ_BIT) { 714 if (emac_rx_active_head) { 715 writel(BD_TO_HW((ulong)emac_rx_active_head), 716 &adap_emac->RX0HDP); 717 } else { 718 emac_rx_queue_active = 0; 719 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 720 } 721 } 722 723 /* Recycle RX descriptor */ 724 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 725 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 726 rx_curr_desc->next = 0; 727 davinci_flush_desc(rx_curr_desc); 728 729 if (emac_rx_active_head == 0) { 730 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 731 emac_rx_active_head = curr_desc; 732 emac_rx_active_tail = curr_desc; 733 if (emac_rx_queue_active != 0) { 734 writel(BD_TO_HW((ulong)emac_rx_active_head), 735 &adap_emac->RX0HDP); 736 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 737 emac_rx_queue_active = 1; 738 } 739 } else { 740 tail_desc = emac_rx_active_tail; 741 emac_rx_active_tail = curr_desc; 742 tail_desc->next = BD_TO_HW((ulong) curr_desc); 743 status = tail_desc->pkt_flag_len; 744 if (status & EMAC_CPPI_EOQ_BIT) { 745 davinci_flush_desc(tail_desc); 746 writel(BD_TO_HW((ulong)curr_desc), 747 &adap_emac->RX0HDP); 748 status &= ~EMAC_CPPI_EOQ_BIT; 749 tail_desc->pkt_flag_len = status; 750 } 751 davinci_flush_desc(tail_desc); 752 } 753 return (ret); 754 } 755 return (0); 756 } 757 758 /* 759 * This function initializes the emac hardware. It does NOT initialize 760 * EMAC modules power or pin multiplexors, that is done by board_init() 761 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 762 */ 763 int davinci_emac_initialize(void) 764 { 765 u_int32_t phy_id; 766 u_int16_t tmp; 767 int i; 768 int ret; 769 struct eth_device *dev; 770 771 dev = malloc(sizeof *dev); 772 773 if (dev == NULL) 774 return -1; 775 776 memset(dev, 0, sizeof *dev); 777 sprintf(dev->name, "DaVinci-EMAC"); 778 779 dev->iobase = 0; 780 dev->init = davinci_eth_open; 781 dev->halt = davinci_eth_close; 782 dev->send = davinci_eth_send_packet; 783 dev->recv = davinci_eth_rcv_packet; 784 dev->write_hwaddr = davinci_eth_set_mac_addr; 785 786 eth_register(dev); 787 788 davinci_eth_mdio_enable(); 789 790 /* let the EMAC detect the PHYs */ 791 udelay(5000); 792 793 for (i = 0; i < 256; i++) { 794 if (readl(&adap_mdio->ALIVE)) 795 break; 796 udelay(1000); 797 } 798 799 if (i >= 256) { 800 printf("No ETH PHY detected!!!\n"); 801 return(0); 802 } 803 804 /* Find if PHY(s) is/are connected */ 805 ret = davinci_eth_phy_detect(); 806 if (!ret) 807 return(0); 808 else 809 debug_emac(" %d ETH PHY detected\n", ret); 810 811 /* Get PHY ID and initialize phy_ops for a detected PHY */ 812 for (i = 0; i < num_phy; i++) { 813 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, 814 &tmp)) { 815 active_phy_addr[i] = 0xff; 816 continue; 817 } 818 819 phy_id = (tmp << 16) & 0xffff0000; 820 821 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, 822 &tmp)) { 823 active_phy_addr[i] = 0xff; 824 continue; 825 } 826 827 phy_id |= tmp & 0x0000ffff; 828 829 switch (phy_id) { 830 #ifdef PHY_KSZ8873 831 case PHY_KSZ8873: 832 sprintf(phy[i].name, "KSZ8873 @ 0x%02x", 833 active_phy_addr[i]); 834 phy[i].init = ksz8873_init_phy; 835 phy[i].is_phy_connected = ksz8873_is_phy_connected; 836 phy[i].get_link_speed = ksz8873_get_link_speed; 837 phy[i].auto_negotiate = ksz8873_auto_negotiate; 838 break; 839 #endif 840 #ifdef PHY_LXT972 841 case PHY_LXT972: 842 sprintf(phy[i].name, "LXT972 @ 0x%02x", 843 active_phy_addr[i]); 844 phy[i].init = lxt972_init_phy; 845 phy[i].is_phy_connected = lxt972_is_phy_connected; 846 phy[i].get_link_speed = lxt972_get_link_speed; 847 phy[i].auto_negotiate = lxt972_auto_negotiate; 848 break; 849 #endif 850 #ifdef PHY_DP83848 851 case PHY_DP83848: 852 sprintf(phy[i].name, "DP83848 @ 0x%02x", 853 active_phy_addr[i]); 854 phy[i].init = dp83848_init_phy; 855 phy[i].is_phy_connected = dp83848_is_phy_connected; 856 phy[i].get_link_speed = dp83848_get_link_speed; 857 phy[i].auto_negotiate = dp83848_auto_negotiate; 858 break; 859 #endif 860 #ifdef PHY_ET1011C 861 case PHY_ET1011C: 862 sprintf(phy[i].name, "ET1011C @ 0x%02x", 863 active_phy_addr[i]); 864 phy[i].init = gen_init_phy; 865 phy[i].is_phy_connected = gen_is_phy_connected; 866 phy[i].get_link_speed = et1011c_get_link_speed; 867 phy[i].auto_negotiate = gen_auto_negotiate; 868 break; 869 #endif 870 default: 871 sprintf(phy[i].name, "GENERIC @ 0x%02x", 872 active_phy_addr[i]); 873 phy[i].init = gen_init_phy; 874 phy[i].is_phy_connected = gen_is_phy_connected; 875 phy[i].get_link_speed = gen_get_link_speed; 876 phy[i].auto_negotiate = gen_auto_negotiate; 877 } 878 879 debug("Ethernet PHY: %s\n", phy[i].name); 880 881 miiphy_register(phy[i].name, davinci_mii_phy_read, 882 davinci_mii_phy_write); 883 } 884 885 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 886 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ 887 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) 888 for (i = 0; i < num_phy; i++) { 889 if (phy[i].is_phy_connected(i)) 890 phy[i].auto_negotiate(i); 891 } 892 #endif 893 return(1); 894 } 895