1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License as published by 21 * the Free Software Foundation; either version 2 of the License, or 22 * (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 32 * ---------------------------------------------------------------------------- 33 34 * Modifications: 35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 37 * 38 */ 39 #include <common.h> 40 #include <command.h> 41 #include <net.h> 42 #include <miiphy.h> 43 #include <malloc.h> 44 #include <asm/arch/emac_defs.h> 45 #include <asm/io.h> 46 47 unsigned int emac_dbg = 0; 48 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 49 50 #ifdef DAVINCI_EMAC_GIG_ENABLE 51 #define emac_gigabit_enable() davinci_eth_gigabit_enable() 52 #else 53 #define emac_gigabit_enable() /* no gigabit to enable */ 54 #endif 55 56 static void davinci_eth_mdio_enable(void); 57 58 static int gen_init_phy(int phy_addr); 59 static int gen_is_phy_connected(int phy_addr); 60 static int gen_get_link_speed(int phy_addr); 61 static int gen_auto_negotiate(int phy_addr); 62 63 void eth_mdio_enable(void) 64 { 65 davinci_eth_mdio_enable(); 66 } 67 68 /* EMAC Addresses */ 69 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 70 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 71 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 72 73 /* EMAC descriptors */ 74 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 75 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 76 static volatile emac_desc *emac_rx_active_head = 0; 77 static volatile emac_desc *emac_rx_active_tail = 0; 78 static int emac_rx_queue_active = 0; 79 80 /* Receive packet buffers */ 81 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 82 83 /* PHY address for a discovered PHY (0xff - not found) */ 84 static volatile u_int8_t active_phy_addr = 0xff; 85 86 phy_t phy; 87 88 static int davinci_eth_set_mac_addr(struct eth_device *dev) 89 { 90 unsigned long mac_hi; 91 unsigned long mac_lo; 92 93 /* 94 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 95 * receive) 96 * Using channel 0 only - other channels are disabled 97 * */ 98 writel(0, &adap_emac->MACINDEX); 99 mac_hi = (dev->enetaddr[3] << 24) | 100 (dev->enetaddr[2] << 16) | 101 (dev->enetaddr[1] << 8) | 102 (dev->enetaddr[0]); 103 mac_lo = (dev->enetaddr[5] << 8) | 104 (dev->enetaddr[4]); 105 106 writel(mac_hi, &adap_emac->MACADDRHI); 107 #if defined(DAVINCI_EMAC_VERSION2) 108 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 109 &adap_emac->MACADDRLO); 110 #else 111 writel(mac_lo, &adap_emac->MACADDRLO); 112 #endif 113 114 writel(0, &adap_emac->MACHASH1); 115 writel(0, &adap_emac->MACHASH2); 116 117 /* Set source MAC address - REQUIRED */ 118 writel(mac_hi, &adap_emac->MACSRCADDRHI); 119 writel(mac_lo, &adap_emac->MACSRCADDRLO); 120 121 122 return 0; 123 } 124 125 static void davinci_eth_mdio_enable(void) 126 { 127 u_int32_t clkdiv; 128 129 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 130 131 writel((clkdiv & 0xff) | 132 MDIO_CONTROL_ENABLE | 133 MDIO_CONTROL_FAULT | 134 MDIO_CONTROL_FAULT_ENABLE, 135 &adap_mdio->CONTROL); 136 137 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 138 ; 139 } 140 141 /* 142 * Tries to find an active connected PHY. Returns 1 if address if found. 143 * If no active PHY (or more than one PHY) found returns 0. 144 * Sets active_phy_addr variable. 145 */ 146 static int davinci_eth_phy_detect(void) 147 { 148 u_int32_t phy_act_state; 149 int i; 150 151 active_phy_addr = 0xff; 152 153 phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK; 154 if (phy_act_state == 0) 155 return(0); /* No active PHYs */ 156 157 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 158 159 for (i = 0; i < 32; i++) { 160 if (phy_act_state & (1 << i)) { 161 if (phy_act_state & ~(1 << i)) 162 return(0); /* More than one PHY */ 163 else { 164 active_phy_addr = i; 165 return(1); 166 } 167 } 168 } 169 170 return(0); /* Just to make GCC happy */ 171 } 172 173 174 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 175 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 176 { 177 int tmp; 178 179 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 180 ; 181 182 writel(MDIO_USERACCESS0_GO | 183 MDIO_USERACCESS0_WRITE_READ | 184 ((reg_num & 0x1f) << 21) | 185 ((phy_addr & 0x1f) << 16), 186 &adap_mdio->USERACCESS0); 187 188 /* Wait for command to complete */ 189 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 190 ; 191 192 if (tmp & MDIO_USERACCESS0_ACK) { 193 *data = tmp & 0xffff; 194 return(1); 195 } 196 197 *data = -1; 198 return(0); 199 } 200 201 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 202 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 203 { 204 205 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 206 ; 207 208 writel(MDIO_USERACCESS0_GO | 209 MDIO_USERACCESS0_WRITE_WRITE | 210 ((reg_num & 0x1f) << 21) | 211 ((phy_addr & 0x1f) << 16) | 212 (data & 0xffff), 213 &adap_mdio->USERACCESS0); 214 215 /* Wait for command to complete */ 216 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 217 ; 218 219 return(1); 220 } 221 222 /* PHY functions for a generic PHY */ 223 static int gen_init_phy(int phy_addr) 224 { 225 int ret = 1; 226 227 if (gen_get_link_speed(phy_addr)) { 228 /* Try another time */ 229 ret = gen_get_link_speed(phy_addr); 230 } 231 232 return(ret); 233 } 234 235 static int gen_is_phy_connected(int phy_addr) 236 { 237 u_int16_t dummy; 238 239 return(davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy)); 240 } 241 242 static int gen_get_link_speed(int phy_addr) 243 { 244 u_int16_t tmp; 245 246 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 247 (tmp & 0x04)) { 248 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 249 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 250 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 251 252 /* Speed doesn't matter, there is no setting for it in EMAC. */ 253 if (tmp & (LPA_100FULL | LPA_10FULL)) { 254 /* set EMAC for Full Duplex */ 255 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 256 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 257 &adap_emac->MACCONTROL); 258 } else { 259 /*set EMAC for Half Duplex */ 260 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 261 &adap_emac->MACCONTROL); 262 } 263 264 if (tmp & (LPA_100FULL | LPA_100HALF)) 265 writel(readl(&adap_emac->MACCONTROL) | 266 EMAC_MACCONTROL_RMIISPEED_100, 267 &adap_emac->MACCONTROL); 268 else 269 writel(readl(&adap_emac->MACCONTROL) & 270 ~EMAC_MACCONTROL_RMIISPEED_100, 271 &adap_emac->MACCONTROL); 272 #endif 273 return(1); 274 } 275 276 return(0); 277 } 278 279 static int gen_auto_negotiate(int phy_addr) 280 { 281 u_int16_t tmp; 282 283 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 284 return(0); 285 286 /* Restart Auto_negotiation */ 287 tmp |= BMCR_ANENABLE; 288 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 289 290 /*check AutoNegotiate complete */ 291 udelay (10000); 292 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 293 return(0); 294 295 if (!(tmp & BMSR_ANEGCOMPLETE)) 296 return(0); 297 298 return(gen_get_link_speed(phy_addr)); 299 } 300 /* End of generic PHY functions */ 301 302 303 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 304 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) 305 { 306 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); 307 } 308 309 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) 310 { 311 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 312 } 313 #endif 314 315 static void __attribute__((unused)) davinci_eth_gigabit_enable(void) 316 { 317 u_int16_t data; 318 319 if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) { 320 if (data & (1 << 6)) { /* speed selection MSB */ 321 /* 322 * Check if link detected is giga-bit 323 * If Gigabit mode detected, enable gigbit in MAC 324 */ 325 writel(readl(&adap_emac->MACCONTROL) | 326 EMAC_MACCONTROL_GIGFORCE | 327 EMAC_MACCONTROL_GIGABIT_ENABLE, 328 &adap_emac->MACCONTROL); 329 } 330 } 331 } 332 333 /* Eth device open */ 334 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 335 { 336 dv_reg_p addr; 337 u_int32_t clkdiv, cnt; 338 volatile emac_desc *rx_desc; 339 340 debug_emac("+ emac_open\n"); 341 342 /* Reset EMAC module and disable interrupts in wrapper */ 343 writel(1, &adap_emac->SOFTRESET); 344 while (readl(&adap_emac->SOFTRESET) != 0) 345 ; 346 #if defined(DAVINCI_EMAC_VERSION2) 347 writel(1, &adap_ewrap->softrst); 348 while (readl(&adap_ewrap->softrst) != 0) 349 ; 350 #else 351 writel(0, &adap_ewrap->EWCTL); 352 for (cnt = 0; cnt < 5; cnt++) { 353 clkdiv = readl(&adap_ewrap->EWCTL); 354 } 355 #endif 356 357 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 358 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 359 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 360 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 361 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 362 #endif 363 rx_desc = emac_rx_desc; 364 365 writel(1, &adap_emac->TXCONTROL); 366 writel(1, &adap_emac->RXCONTROL); 367 368 davinci_eth_set_mac_addr(dev); 369 370 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 371 addr = &adap_emac->TX0HDP; 372 for(cnt = 0; cnt < 16; cnt++) 373 writel(0, addr++); 374 375 addr = &adap_emac->RX0HDP; 376 for(cnt = 0; cnt < 16; cnt++) 377 writel(0, addr++); 378 379 /* Clear Statistics (do this before setting MacControl register) */ 380 addr = &adap_emac->RXGOODFRAMES; 381 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 382 writel(0, addr++); 383 384 /* No multicast addressing */ 385 writel(0, &adap_emac->MACHASH1); 386 writel(0, &adap_emac->MACHASH2); 387 388 /* Create RX queue and set receive process in place */ 389 emac_rx_active_head = emac_rx_desc; 390 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 391 rx_desc->next = (u_int32_t)(rx_desc + 1); 392 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 393 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 394 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 395 rx_desc++; 396 } 397 398 /* Finalize the rx desc list */ 399 rx_desc--; 400 rx_desc->next = 0; 401 emac_rx_active_tail = rx_desc; 402 emac_rx_queue_active = 1; 403 404 /* Enable TX/RX */ 405 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 406 writel(0, &adap_emac->RXBUFFEROFFSET); 407 408 /* 409 * No fancy configs - Use this for promiscous debug 410 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 411 */ 412 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 413 414 /* Enable ch 0 only */ 415 writel(1, &adap_emac->RXUNICASTSET); 416 417 /* Enable MII interface and Full duplex mode */ 418 #ifdef CONFIG_SOC_DA8XX 419 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 420 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 421 EMAC_MACCONTROL_RMIISPEED_100), 422 &adap_emac->MACCONTROL); 423 #else 424 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 425 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 426 &adap_emac->MACCONTROL); 427 #endif 428 429 /* Init MDIO & get link state */ 430 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 431 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 432 &adap_mdio->CONTROL); 433 434 /* We need to wait for MDIO to start */ 435 udelay(1000); 436 437 if (!phy.get_link_speed(active_phy_addr)) 438 return(0); 439 440 emac_gigabit_enable(); 441 442 /* Start receive process */ 443 writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); 444 445 debug_emac("- emac_open\n"); 446 447 return(1); 448 } 449 450 /* EMAC Channel Teardown */ 451 static void davinci_eth_ch_teardown(int ch) 452 { 453 dv_reg dly = 0xff; 454 dv_reg cnt; 455 456 debug_emac("+ emac_ch_teardown\n"); 457 458 if (ch == EMAC_CH_TX) { 459 /* Init TX channel teardown */ 460 writel(1, &adap_emac->TXTEARDOWN); 461 do { 462 /* 463 * Wait here for Tx teardown completion interrupt to 464 * occur. Note: A task delay can be called here to pend 465 * rather than occupying CPU cycles - anyway it has 466 * been found that teardown takes very few cpu cycles 467 * and does not affect functionality 468 */ 469 dly--; 470 udelay(1); 471 if (dly == 0) 472 break; 473 cnt = readl(&adap_emac->TX0CP); 474 } while (cnt != 0xfffffffc); 475 writel(cnt, &adap_emac->TX0CP); 476 writel(0, &adap_emac->TX0HDP); 477 } else { 478 /* Init RX channel teardown */ 479 writel(1, &adap_emac->RXTEARDOWN); 480 do { 481 /* 482 * Wait here for Rx teardown completion interrupt to 483 * occur. Note: A task delay can be called here to pend 484 * rather than occupying CPU cycles - anyway it has 485 * been found that teardown takes very few cpu cycles 486 * and does not affect functionality 487 */ 488 dly--; 489 udelay(1); 490 if (dly == 0) 491 break; 492 cnt = readl(&adap_emac->RX0CP); 493 } while (cnt != 0xfffffffc); 494 writel(cnt, &adap_emac->RX0CP); 495 writel(0, &adap_emac->RX0HDP); 496 } 497 498 debug_emac("- emac_ch_teardown\n"); 499 } 500 501 /* Eth device close */ 502 static void davinci_eth_close(struct eth_device *dev) 503 { 504 debug_emac("+ emac_close\n"); 505 506 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 507 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 508 509 /* Reset EMAC module and disable interrupts in wrapper */ 510 writel(1, &adap_emac->SOFTRESET); 511 #if defined(DAVINCI_EMAC_VERSION2) 512 writel(1, &adap_ewrap->softrst); 513 #else 514 writel(0, &adap_ewrap->EWCTL); 515 #endif 516 517 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 518 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 519 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 520 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 521 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 522 #endif 523 debug_emac("- emac_close\n"); 524 } 525 526 static int tx_send_loop = 0; 527 528 /* 529 * This function sends a single packet on the network and returns 530 * positive number (number of bytes transmitted) or negative for error 531 */ 532 static int davinci_eth_send_packet (struct eth_device *dev, 533 volatile void *packet, int length) 534 { 535 int ret_status = -1; 536 537 tx_send_loop = 0; 538 539 /* Return error if no link */ 540 if (!phy.get_link_speed (active_phy_addr)) { 541 printf ("WARN: emac_send_packet: No link\n"); 542 return (ret_status); 543 } 544 545 emac_gigabit_enable(); 546 547 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 548 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 549 length = EMAC_MIN_ETHERNET_PKT_SIZE; 550 } 551 552 /* Populate the TX descriptor */ 553 emac_tx_desc->next = 0; 554 emac_tx_desc->buffer = (u_int8_t *) packet; 555 emac_tx_desc->buff_off_len = (length & 0xffff); 556 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 557 EMAC_CPPI_SOP_BIT | 558 EMAC_CPPI_OWNERSHIP_BIT | 559 EMAC_CPPI_EOP_BIT); 560 /* Send the packet */ 561 writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); 562 563 /* Wait for packet to complete or link down */ 564 while (1) { 565 if (!phy.get_link_speed (active_phy_addr)) { 566 davinci_eth_ch_teardown (EMAC_CH_TX); 567 return (ret_status); 568 } 569 570 emac_gigabit_enable(); 571 572 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 573 ret_status = length; 574 break; 575 } 576 tx_send_loop++; 577 } 578 579 return (ret_status); 580 } 581 582 /* 583 * This function handles receipt of a packet from the network 584 */ 585 static int davinci_eth_rcv_packet (struct eth_device *dev) 586 { 587 volatile emac_desc *rx_curr_desc; 588 volatile emac_desc *curr_desc; 589 volatile emac_desc *tail_desc; 590 int status, ret = -1; 591 592 rx_curr_desc = emac_rx_active_head; 593 status = rx_curr_desc->pkt_flag_len; 594 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { 595 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 596 /* Error in packet - discard it and requeue desc */ 597 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 598 } else { 599 NetReceive (rx_curr_desc->buffer, 600 (rx_curr_desc->buff_off_len & 0xffff)); 601 ret = rx_curr_desc->buff_off_len & 0xffff; 602 } 603 604 /* Ack received packet descriptor */ 605 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); 606 curr_desc = rx_curr_desc; 607 emac_rx_active_head = 608 (volatile emac_desc *) rx_curr_desc->next; 609 610 if (status & EMAC_CPPI_EOQ_BIT) { 611 if (emac_rx_active_head) { 612 writel((unsigned long)emac_rx_active_head, 613 &adap_emac->RX0HDP); 614 } else { 615 emac_rx_queue_active = 0; 616 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 617 } 618 } 619 620 /* Recycle RX descriptor */ 621 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 622 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 623 rx_curr_desc->next = 0; 624 625 if (emac_rx_active_head == 0) { 626 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 627 emac_rx_active_head = curr_desc; 628 emac_rx_active_tail = curr_desc; 629 if (emac_rx_queue_active != 0) { 630 writel((unsigned long)emac_rx_active_head, 631 &adap_emac->RX0HDP); 632 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 633 emac_rx_queue_active = 1; 634 } 635 } else { 636 tail_desc = emac_rx_active_tail; 637 emac_rx_active_tail = curr_desc; 638 tail_desc->next = (unsigned int) curr_desc; 639 status = tail_desc->pkt_flag_len; 640 if (status & EMAC_CPPI_EOQ_BIT) { 641 writel((unsigned long)curr_desc, 642 &adap_emac->RX0HDP); 643 status &= ~EMAC_CPPI_EOQ_BIT; 644 tail_desc->pkt_flag_len = status; 645 } 646 } 647 return (ret); 648 } 649 return (0); 650 } 651 652 /* 653 * This function initializes the emac hardware. It does NOT initialize 654 * EMAC modules power or pin multiplexors, that is done by board_init() 655 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 656 */ 657 int davinci_emac_initialize(void) 658 { 659 u_int32_t phy_id; 660 u_int16_t tmp; 661 int i; 662 struct eth_device *dev; 663 664 dev = malloc(sizeof *dev); 665 666 if (dev == NULL) 667 return -1; 668 669 memset(dev, 0, sizeof *dev); 670 sprintf(dev->name, "DaVinci-EMAC"); 671 672 dev->iobase = 0; 673 dev->init = davinci_eth_open; 674 dev->halt = davinci_eth_close; 675 dev->send = davinci_eth_send_packet; 676 dev->recv = davinci_eth_rcv_packet; 677 dev->write_hwaddr = davinci_eth_set_mac_addr; 678 679 eth_register(dev); 680 681 davinci_eth_mdio_enable(); 682 683 for (i = 0; i < 256; i++) { 684 if (readl(&adap_mdio->ALIVE)) 685 break; 686 udelay(10); 687 } 688 689 if (i >= 256) { 690 printf("No ETH PHY detected!!!\n"); 691 return(0); 692 } 693 694 /* Find if a PHY is connected and get it's address */ 695 if (!davinci_eth_phy_detect()) 696 return(0); 697 698 /* Get PHY ID and initialize phy_ops for a detected PHY */ 699 if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID1, &tmp)) { 700 active_phy_addr = 0xff; 701 return(0); 702 } 703 704 phy_id = (tmp << 16) & 0xffff0000; 705 706 if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID2, &tmp)) { 707 active_phy_addr = 0xff; 708 return(0); 709 } 710 711 phy_id |= tmp & 0x0000ffff; 712 713 switch (phy_id) { 714 case PHY_LXT972: 715 sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); 716 phy.init = lxt972_init_phy; 717 phy.is_phy_connected = lxt972_is_phy_connected; 718 phy.get_link_speed = lxt972_get_link_speed; 719 phy.auto_negotiate = lxt972_auto_negotiate; 720 break; 721 case PHY_DP83848: 722 sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); 723 phy.init = dp83848_init_phy; 724 phy.is_phy_connected = dp83848_is_phy_connected; 725 phy.get_link_speed = dp83848_get_link_speed; 726 phy.auto_negotiate = dp83848_auto_negotiate; 727 break; 728 case PHY_ET1011C: 729 sprintf(phy.name, "ET1011C @ 0x%02x", active_phy_addr); 730 phy.init = gen_init_phy; 731 phy.is_phy_connected = gen_is_phy_connected; 732 phy.get_link_speed = et1011c_get_link_speed; 733 phy.auto_negotiate = gen_auto_negotiate; 734 break; 735 default: 736 sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); 737 phy.init = gen_init_phy; 738 phy.is_phy_connected = gen_is_phy_connected; 739 phy.get_link_speed = gen_get_link_speed; 740 phy.auto_negotiate = gen_auto_negotiate; 741 } 742 743 printf("Ethernet PHY: %s\n", phy.name); 744 745 miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); 746 return(1); 747 } 748