1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License as published by 21 * the Free Software Foundation; either version 2 of the License, or 22 * (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 32 * ---------------------------------------------------------------------------- 33 34 * Modifications: 35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 37 * 38 */ 39 #include <common.h> 40 #include <command.h> 41 #include <net.h> 42 #include <miiphy.h> 43 #include <malloc.h> 44 #include <asm/arch/emac_defs.h> 45 #include <asm/io.h> 46 #include "davinci_emac.h" 47 48 unsigned int emac_dbg = 0; 49 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 50 51 #ifdef EMAC_HW_RAM_ADDR 52 static inline unsigned long BD_TO_HW(unsigned long x) 53 { 54 if (x == 0) 55 return 0; 56 57 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; 58 } 59 60 static inline unsigned long HW_TO_BD(unsigned long x) 61 { 62 if (x == 0) 63 return 0; 64 65 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; 66 } 67 #else 68 #define BD_TO_HW(x) (x) 69 #define HW_TO_BD(x) (x) 70 #endif 71 72 #ifdef DAVINCI_EMAC_GIG_ENABLE 73 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) 74 #else 75 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ 76 #endif 77 78 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) 79 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ 80 EMAC_MDIO_CLOCK_FREQ) - 1) 81 #endif 82 83 static void davinci_eth_mdio_enable(void); 84 85 static int gen_init_phy(int phy_addr); 86 static int gen_is_phy_connected(int phy_addr); 87 static int gen_get_link_speed(int phy_addr); 88 static int gen_auto_negotiate(int phy_addr); 89 90 void eth_mdio_enable(void) 91 { 92 davinci_eth_mdio_enable(); 93 } 94 95 /* EMAC Addresses */ 96 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 97 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 98 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 99 100 /* EMAC descriptors */ 101 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 102 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 103 static volatile emac_desc *emac_rx_active_head = 0; 104 static volatile emac_desc *emac_rx_active_tail = 0; 105 static int emac_rx_queue_active = 0; 106 107 /* Receive packet buffers */ 108 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 109 110 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 111 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 112 #endif 113 114 /* PHY address for a discovered PHY (0xff - not found) */ 115 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 116 117 /* number of PHY found active */ 118 static u_int8_t num_phy; 119 120 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 121 122 static int davinci_eth_set_mac_addr(struct eth_device *dev) 123 { 124 unsigned long mac_hi; 125 unsigned long mac_lo; 126 127 /* 128 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 129 * receive) 130 * Using channel 0 only - other channels are disabled 131 * */ 132 writel(0, &adap_emac->MACINDEX); 133 mac_hi = (dev->enetaddr[3] << 24) | 134 (dev->enetaddr[2] << 16) | 135 (dev->enetaddr[1] << 8) | 136 (dev->enetaddr[0]); 137 mac_lo = (dev->enetaddr[5] << 8) | 138 (dev->enetaddr[4]); 139 140 writel(mac_hi, &adap_emac->MACADDRHI); 141 #if defined(DAVINCI_EMAC_VERSION2) 142 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 143 &adap_emac->MACADDRLO); 144 #else 145 writel(mac_lo, &adap_emac->MACADDRLO); 146 #endif 147 148 writel(0, &adap_emac->MACHASH1); 149 writel(0, &adap_emac->MACHASH2); 150 151 /* Set source MAC address - REQUIRED */ 152 writel(mac_hi, &adap_emac->MACSRCADDRHI); 153 writel(mac_lo, &adap_emac->MACSRCADDRLO); 154 155 156 return 0; 157 } 158 159 static void davinci_eth_mdio_enable(void) 160 { 161 u_int32_t clkdiv; 162 163 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 164 165 writel((clkdiv & 0xff) | 166 MDIO_CONTROL_ENABLE | 167 MDIO_CONTROL_FAULT | 168 MDIO_CONTROL_FAULT_ENABLE, 169 &adap_mdio->CONTROL); 170 171 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 172 ; 173 } 174 175 /* 176 * Tries to find an active connected PHY. Returns 1 if address if found. 177 * If no active PHY (or more than one PHY) found returns 0. 178 * Sets active_phy_addr variable. 179 */ 180 static int davinci_eth_phy_detect(void) 181 { 182 u_int32_t phy_act_state; 183 int i; 184 int j; 185 unsigned int count = 0; 186 187 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) 188 active_phy_addr[i] = 0xff; 189 190 udelay(1000); 191 phy_act_state = readl(&adap_mdio->ALIVE); 192 193 if (phy_act_state == 0) 194 return 0; /* No active PHYs */ 195 196 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 197 198 for (i = 0, j = 0; i < 32; i++) 199 if (phy_act_state & (1 << i)) { 200 count++; 201 if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { 202 active_phy_addr[j++] = i; 203 } else { 204 printf("%s: to many PHYs detected.\n", 205 __func__); 206 count = 0; 207 break; 208 } 209 } 210 211 num_phy = count; 212 213 return count; 214 } 215 216 217 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 218 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 219 { 220 int tmp; 221 222 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 223 ; 224 225 writel(MDIO_USERACCESS0_GO | 226 MDIO_USERACCESS0_WRITE_READ | 227 ((reg_num & 0x1f) << 21) | 228 ((phy_addr & 0x1f) << 16), 229 &adap_mdio->USERACCESS0); 230 231 /* Wait for command to complete */ 232 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 233 ; 234 235 if (tmp & MDIO_USERACCESS0_ACK) { 236 *data = tmp & 0xffff; 237 return(1); 238 } 239 240 *data = -1; 241 return(0); 242 } 243 244 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 245 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 246 { 247 248 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 249 ; 250 251 writel(MDIO_USERACCESS0_GO | 252 MDIO_USERACCESS0_WRITE_WRITE | 253 ((reg_num & 0x1f) << 21) | 254 ((phy_addr & 0x1f) << 16) | 255 (data & 0xffff), 256 &adap_mdio->USERACCESS0); 257 258 /* Wait for command to complete */ 259 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 260 ; 261 262 return(1); 263 } 264 265 /* PHY functions for a generic PHY */ 266 static int gen_init_phy(int phy_addr) 267 { 268 int ret = 1; 269 270 if (gen_get_link_speed(phy_addr)) { 271 /* Try another time */ 272 ret = gen_get_link_speed(phy_addr); 273 } 274 275 return(ret); 276 } 277 278 static int gen_is_phy_connected(int phy_addr) 279 { 280 u_int16_t dummy; 281 282 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); 283 } 284 285 static int get_active_phy(void) 286 { 287 int i; 288 289 for (i = 0; i < num_phy; i++) 290 if (phy[i].get_link_speed(active_phy_addr[i])) 291 return i; 292 293 return -1; /* Return error if no link */ 294 } 295 296 static int gen_get_link_speed(int phy_addr) 297 { 298 u_int16_t tmp; 299 300 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 301 (tmp & 0x04)) { 302 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 303 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 304 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 305 306 /* Speed doesn't matter, there is no setting for it in EMAC. */ 307 if (tmp & (LPA_100FULL | LPA_10FULL)) { 308 /* set EMAC for Full Duplex */ 309 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 310 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 311 &adap_emac->MACCONTROL); 312 } else { 313 /*set EMAC for Half Duplex */ 314 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 315 &adap_emac->MACCONTROL); 316 } 317 318 if (tmp & (LPA_100FULL | LPA_100HALF)) 319 writel(readl(&adap_emac->MACCONTROL) | 320 EMAC_MACCONTROL_RMIISPEED_100, 321 &adap_emac->MACCONTROL); 322 else 323 writel(readl(&adap_emac->MACCONTROL) & 324 ~EMAC_MACCONTROL_RMIISPEED_100, 325 &adap_emac->MACCONTROL); 326 #endif 327 return(1); 328 } 329 330 return(0); 331 } 332 333 static int gen_auto_negotiate(int phy_addr) 334 { 335 u_int16_t tmp; 336 u_int16_t val; 337 unsigned long cntr = 0; 338 339 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 340 return 0; 341 342 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | 343 BMCR_SPEED100; 344 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 345 346 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) 347 return 0; 348 349 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | 350 ADVERTISE_10HALF); 351 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); 352 353 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 354 return(0); 355 356 /* Restart Auto_negotiation */ 357 tmp |= BMCR_ANRESTART; 358 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 359 360 /*check AutoNegotiate complete */ 361 do { 362 udelay(40000); 363 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 364 return 0; 365 366 if (tmp & BMSR_ANEGCOMPLETE) 367 break; 368 369 cntr++; 370 } while (cntr < 200); 371 372 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 373 return(0); 374 375 if (!(tmp & BMSR_ANEGCOMPLETE)) 376 return(0); 377 378 return(gen_get_link_speed(phy_addr)); 379 } 380 /* End of generic PHY functions */ 381 382 383 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 384 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) 385 { 386 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); 387 } 388 389 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) 390 { 391 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 392 } 393 #endif 394 395 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) 396 { 397 u_int16_t data; 398 399 if (davinci_eth_phy_read(phy_addr, 0, &data)) { 400 if (data & (1 << 6)) { /* speed selection MSB */ 401 /* 402 * Check if link detected is giga-bit 403 * If Gigabit mode detected, enable gigbit in MAC 404 */ 405 writel(readl(&adap_emac->MACCONTROL) | 406 EMAC_MACCONTROL_GIGFORCE | 407 EMAC_MACCONTROL_GIGABIT_ENABLE, 408 &adap_emac->MACCONTROL); 409 } 410 } 411 } 412 413 /* Eth device open */ 414 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 415 { 416 dv_reg_p addr; 417 u_int32_t clkdiv, cnt; 418 volatile emac_desc *rx_desc; 419 int index; 420 421 debug_emac("+ emac_open\n"); 422 423 /* Reset EMAC module and disable interrupts in wrapper */ 424 writel(1, &adap_emac->SOFTRESET); 425 while (readl(&adap_emac->SOFTRESET) != 0) 426 ; 427 #if defined(DAVINCI_EMAC_VERSION2) 428 writel(1, &adap_ewrap->softrst); 429 while (readl(&adap_ewrap->softrst) != 0) 430 ; 431 #else 432 writel(0, &adap_ewrap->EWCTL); 433 for (cnt = 0; cnt < 5; cnt++) { 434 clkdiv = readl(&adap_ewrap->EWCTL); 435 } 436 #endif 437 438 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 439 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 440 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 441 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 442 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 443 #endif 444 rx_desc = emac_rx_desc; 445 446 writel(1, &adap_emac->TXCONTROL); 447 writel(1, &adap_emac->RXCONTROL); 448 449 davinci_eth_set_mac_addr(dev); 450 451 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 452 addr = &adap_emac->TX0HDP; 453 for(cnt = 0; cnt < 16; cnt++) 454 writel(0, addr++); 455 456 addr = &adap_emac->RX0HDP; 457 for(cnt = 0; cnt < 16; cnt++) 458 writel(0, addr++); 459 460 /* Clear Statistics (do this before setting MacControl register) */ 461 addr = &adap_emac->RXGOODFRAMES; 462 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 463 writel(0, addr++); 464 465 /* No multicast addressing */ 466 writel(0, &adap_emac->MACHASH1); 467 writel(0, &adap_emac->MACHASH2); 468 469 /* Create RX queue and set receive process in place */ 470 emac_rx_active_head = emac_rx_desc; 471 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 472 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); 473 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 474 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 475 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 476 rx_desc++; 477 } 478 479 /* Finalize the rx desc list */ 480 rx_desc--; 481 rx_desc->next = 0; 482 emac_rx_active_tail = rx_desc; 483 emac_rx_queue_active = 1; 484 485 /* Enable TX/RX */ 486 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 487 writel(0, &adap_emac->RXBUFFEROFFSET); 488 489 /* 490 * No fancy configs - Use this for promiscous debug 491 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 492 */ 493 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 494 495 /* Enable ch 0 only */ 496 writel(1, &adap_emac->RXUNICASTSET); 497 498 /* Enable MII interface and Full duplex mode */ 499 #ifdef CONFIG_SOC_DA8XX 500 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 501 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 502 EMAC_MACCONTROL_RMIISPEED_100), 503 &adap_emac->MACCONTROL); 504 #else 505 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 506 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 507 &adap_emac->MACCONTROL); 508 #endif 509 510 /* Init MDIO & get link state */ 511 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 512 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 513 &adap_mdio->CONTROL); 514 515 /* We need to wait for MDIO to start */ 516 udelay(1000); 517 518 index = get_active_phy(); 519 if (index == -1) 520 return(0); 521 522 emac_gigabit_enable(active_phy_addr[index]); 523 524 /* Start receive process */ 525 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); 526 527 debug_emac("- emac_open\n"); 528 529 return(1); 530 } 531 532 /* EMAC Channel Teardown */ 533 static void davinci_eth_ch_teardown(int ch) 534 { 535 dv_reg dly = 0xff; 536 dv_reg cnt; 537 538 debug_emac("+ emac_ch_teardown\n"); 539 540 if (ch == EMAC_CH_TX) { 541 /* Init TX channel teardown */ 542 writel(0, &adap_emac->TXTEARDOWN); 543 do { 544 /* 545 * Wait here for Tx teardown completion interrupt to 546 * occur. Note: A task delay can be called here to pend 547 * rather than occupying CPU cycles - anyway it has 548 * been found that teardown takes very few cpu cycles 549 * and does not affect functionality 550 */ 551 dly--; 552 udelay(1); 553 if (dly == 0) 554 break; 555 cnt = readl(&adap_emac->TX0CP); 556 } while (cnt != 0xfffffffc); 557 writel(cnt, &adap_emac->TX0CP); 558 writel(0, &adap_emac->TX0HDP); 559 } else { 560 /* Init RX channel teardown */ 561 writel(0, &adap_emac->RXTEARDOWN); 562 do { 563 /* 564 * Wait here for Rx teardown completion interrupt to 565 * occur. Note: A task delay can be called here to pend 566 * rather than occupying CPU cycles - anyway it has 567 * been found that teardown takes very few cpu cycles 568 * and does not affect functionality 569 */ 570 dly--; 571 udelay(1); 572 if (dly == 0) 573 break; 574 cnt = readl(&adap_emac->RX0CP); 575 } while (cnt != 0xfffffffc); 576 writel(cnt, &adap_emac->RX0CP); 577 writel(0, &adap_emac->RX0HDP); 578 } 579 580 debug_emac("- emac_ch_teardown\n"); 581 } 582 583 /* Eth device close */ 584 static void davinci_eth_close(struct eth_device *dev) 585 { 586 debug_emac("+ emac_close\n"); 587 588 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 589 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 590 591 /* Reset EMAC module and disable interrupts in wrapper */ 592 writel(1, &adap_emac->SOFTRESET); 593 #if defined(DAVINCI_EMAC_VERSION2) 594 writel(1, &adap_ewrap->softrst); 595 #else 596 writel(0, &adap_ewrap->EWCTL); 597 #endif 598 599 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 600 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 601 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 602 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 603 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 604 #endif 605 debug_emac("- emac_close\n"); 606 } 607 608 static int tx_send_loop = 0; 609 610 /* 611 * This function sends a single packet on the network and returns 612 * positive number (number of bytes transmitted) or negative for error 613 */ 614 static int davinci_eth_send_packet (struct eth_device *dev, 615 volatile void *packet, int length) 616 { 617 int ret_status = -1; 618 int index; 619 tx_send_loop = 0; 620 621 index = get_active_phy(); 622 if (index == -1) { 623 printf(" WARN: emac_send_packet: No link\n"); 624 return (ret_status); 625 } 626 627 emac_gigabit_enable(active_phy_addr[index]); 628 629 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 630 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 631 length = EMAC_MIN_ETHERNET_PKT_SIZE; 632 } 633 634 /* Populate the TX descriptor */ 635 emac_tx_desc->next = 0; 636 emac_tx_desc->buffer = (u_int8_t *) packet; 637 emac_tx_desc->buff_off_len = (length & 0xffff); 638 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 639 EMAC_CPPI_SOP_BIT | 640 EMAC_CPPI_OWNERSHIP_BIT | 641 EMAC_CPPI_EOP_BIT); 642 /* Send the packet */ 643 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); 644 645 /* Wait for packet to complete or link down */ 646 while (1) { 647 if (!phy[index].get_link_speed(active_phy_addr[index])) { 648 davinci_eth_ch_teardown (EMAC_CH_TX); 649 return (ret_status); 650 } 651 652 emac_gigabit_enable(active_phy_addr[index]); 653 654 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 655 ret_status = length; 656 break; 657 } 658 tx_send_loop++; 659 } 660 661 return (ret_status); 662 } 663 664 /* 665 * This function handles receipt of a packet from the network 666 */ 667 static int davinci_eth_rcv_packet (struct eth_device *dev) 668 { 669 volatile emac_desc *rx_curr_desc; 670 volatile emac_desc *curr_desc; 671 volatile emac_desc *tail_desc; 672 int status, ret = -1; 673 674 rx_curr_desc = emac_rx_active_head; 675 status = rx_curr_desc->pkt_flag_len; 676 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { 677 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 678 /* Error in packet - discard it and requeue desc */ 679 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 680 } else { 681 NetReceive (rx_curr_desc->buffer, 682 (rx_curr_desc->buff_off_len & 0xffff)); 683 ret = rx_curr_desc->buff_off_len & 0xffff; 684 } 685 686 /* Ack received packet descriptor */ 687 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); 688 curr_desc = rx_curr_desc; 689 emac_rx_active_head = 690 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); 691 692 if (status & EMAC_CPPI_EOQ_BIT) { 693 if (emac_rx_active_head) { 694 writel(BD_TO_HW((ulong)emac_rx_active_head), 695 &adap_emac->RX0HDP); 696 } else { 697 emac_rx_queue_active = 0; 698 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 699 } 700 } 701 702 /* Recycle RX descriptor */ 703 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 704 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 705 rx_curr_desc->next = 0; 706 707 if (emac_rx_active_head == 0) { 708 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 709 emac_rx_active_head = curr_desc; 710 emac_rx_active_tail = curr_desc; 711 if (emac_rx_queue_active != 0) { 712 writel(BD_TO_HW((ulong)emac_rx_active_head), 713 &adap_emac->RX0HDP); 714 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 715 emac_rx_queue_active = 1; 716 } 717 } else { 718 tail_desc = emac_rx_active_tail; 719 emac_rx_active_tail = curr_desc; 720 tail_desc->next = BD_TO_HW((ulong) curr_desc); 721 status = tail_desc->pkt_flag_len; 722 if (status & EMAC_CPPI_EOQ_BIT) { 723 writel(BD_TO_HW((ulong)curr_desc), 724 &adap_emac->RX0HDP); 725 status &= ~EMAC_CPPI_EOQ_BIT; 726 tail_desc->pkt_flag_len = status; 727 } 728 } 729 return (ret); 730 } 731 return (0); 732 } 733 734 /* 735 * This function initializes the emac hardware. It does NOT initialize 736 * EMAC modules power or pin multiplexors, that is done by board_init() 737 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 738 */ 739 int davinci_emac_initialize(void) 740 { 741 u_int32_t phy_id; 742 u_int16_t tmp; 743 int i; 744 int ret; 745 struct eth_device *dev; 746 747 dev = malloc(sizeof *dev); 748 749 if (dev == NULL) 750 return -1; 751 752 memset(dev, 0, sizeof *dev); 753 sprintf(dev->name, "DaVinci-EMAC"); 754 755 dev->iobase = 0; 756 dev->init = davinci_eth_open; 757 dev->halt = davinci_eth_close; 758 dev->send = davinci_eth_send_packet; 759 dev->recv = davinci_eth_rcv_packet; 760 dev->write_hwaddr = davinci_eth_set_mac_addr; 761 762 eth_register(dev); 763 764 davinci_eth_mdio_enable(); 765 766 /* let the EMAC detect the PHYs */ 767 udelay(5000); 768 769 for (i = 0; i < 256; i++) { 770 if (readl(&adap_mdio->ALIVE)) 771 break; 772 udelay(1000); 773 } 774 775 if (i >= 256) { 776 printf("No ETH PHY detected!!!\n"); 777 return(0); 778 } 779 780 /* Find if PHY(s) is/are connected */ 781 ret = davinci_eth_phy_detect(); 782 if (!ret) 783 return(0); 784 else 785 debug_emac(" %d ETH PHY detected\n", ret); 786 787 /* Get PHY ID and initialize phy_ops for a detected PHY */ 788 for (i = 0; i < num_phy; i++) { 789 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, 790 &tmp)) { 791 active_phy_addr[i] = 0xff; 792 continue; 793 } 794 795 phy_id = (tmp << 16) & 0xffff0000; 796 797 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, 798 &tmp)) { 799 active_phy_addr[i] = 0xff; 800 continue; 801 } 802 803 phy_id |= tmp & 0x0000ffff; 804 805 switch (phy_id) { 806 #ifdef PHY_KSZ8873 807 case PHY_KSZ8873: 808 sprintf(phy[i].name, "KSZ8873 @ 0x%02x", 809 active_phy_addr[i]); 810 phy[i].init = ksz8873_init_phy; 811 phy[i].is_phy_connected = ksz8873_is_phy_connected; 812 phy[i].get_link_speed = ksz8873_get_link_speed; 813 phy[i].auto_negotiate = ksz8873_auto_negotiate; 814 break; 815 #endif 816 #ifdef PHY_LXT972 817 case PHY_LXT972: 818 sprintf(phy[i].name, "LXT972 @ 0x%02x", 819 active_phy_addr[i]); 820 phy[i].init = lxt972_init_phy; 821 phy[i].is_phy_connected = lxt972_is_phy_connected; 822 phy[i].get_link_speed = lxt972_get_link_speed; 823 phy[i].auto_negotiate = lxt972_auto_negotiate; 824 break; 825 #endif 826 #ifdef PHY_DP83848 827 case PHY_DP83848: 828 sprintf(phy[i].name, "DP83848 @ 0x%02x", 829 active_phy_addr[i]); 830 phy[i].init = dp83848_init_phy; 831 phy[i].is_phy_connected = dp83848_is_phy_connected; 832 phy[i].get_link_speed = dp83848_get_link_speed; 833 phy[i].auto_negotiate = dp83848_auto_negotiate; 834 break; 835 #endif 836 #ifdef PHY_ET1011C 837 case PHY_ET1011C: 838 sprintf(phy[i].name, "ET1011C @ 0x%02x", 839 active_phy_addr[i]); 840 phy[i].init = gen_init_phy; 841 phy[i].is_phy_connected = gen_is_phy_connected; 842 phy[i].get_link_speed = et1011c_get_link_speed; 843 phy[i].auto_negotiate = gen_auto_negotiate; 844 break; 845 #endif 846 default: 847 sprintf(phy[i].name, "GENERIC @ 0x%02x", 848 active_phy_addr[i]); 849 phy[i].init = gen_init_phy; 850 phy[i].is_phy_connected = gen_is_phy_connected; 851 phy[i].get_link_speed = gen_get_link_speed; 852 phy[i].auto_negotiate = gen_auto_negotiate; 853 } 854 855 debug("Ethernet PHY: %s\n", phy[i].name); 856 857 miiphy_register(phy[i].name, davinci_mii_phy_read, 858 davinci_mii_phy_write); 859 } 860 return(1); 861 } 862