1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 * 21 * Modifications: 22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 23 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 24 */ 25 #include <common.h> 26 #include <command.h> 27 #include <net.h> 28 #include <miiphy.h> 29 #include <malloc.h> 30 #include <netdev.h> 31 #include <linux/compiler.h> 32 #include <asm/arch/emac_defs.h> 33 #include <asm/io.h> 34 #include "davinci_emac.h" 35 36 unsigned int emac_dbg = 0; 37 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 38 39 #ifdef EMAC_HW_RAM_ADDR 40 static inline unsigned long BD_TO_HW(unsigned long x) 41 { 42 if (x == 0) 43 return 0; 44 45 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; 46 } 47 48 static inline unsigned long HW_TO_BD(unsigned long x) 49 { 50 if (x == 0) 51 return 0; 52 53 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; 54 } 55 #else 56 #define BD_TO_HW(x) (x) 57 #define HW_TO_BD(x) (x) 58 #endif 59 60 #ifdef DAVINCI_EMAC_GIG_ENABLE 61 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) 62 #else 63 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ 64 #endif 65 66 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) 67 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ 68 EMAC_MDIO_CLOCK_FREQ) - 1) 69 #endif 70 71 static void davinci_eth_mdio_enable(void); 72 73 static int gen_init_phy(int phy_addr); 74 static int gen_is_phy_connected(int phy_addr); 75 static int gen_get_link_speed(int phy_addr); 76 static int gen_auto_negotiate(int phy_addr); 77 78 void eth_mdio_enable(void) 79 { 80 davinci_eth_mdio_enable(); 81 } 82 83 /* EMAC Addresses */ 84 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 85 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 86 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 87 88 /* EMAC descriptors */ 89 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 90 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 91 static volatile emac_desc *emac_rx_active_head = 0; 92 static volatile emac_desc *emac_rx_active_tail = 0; 93 static int emac_rx_queue_active = 0; 94 95 /* Receive packet buffers */ 96 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] 97 __aligned(ARCH_DMA_MINALIGN); 98 99 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 100 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 101 #endif 102 103 /* PHY address for a discovered PHY (0xff - not found) */ 104 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 105 106 /* number of PHY found active */ 107 static u_int8_t num_phy; 108 109 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 110 111 static inline void davinci_flush_rx_descs(void) 112 { 113 /* flush the whole RX descs area */ 114 flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 115 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 116 } 117 118 static inline void davinci_invalidate_rx_descs(void) 119 { 120 /* invalidate the whole RX descs area */ 121 invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 122 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 123 } 124 125 static inline void davinci_flush_desc(emac_desc *desc) 126 { 127 flush_dcache_range((unsigned long)desc, 128 (unsigned long)desc + sizeof(*desc)); 129 } 130 131 static int davinci_eth_set_mac_addr(struct eth_device *dev) 132 { 133 unsigned long mac_hi; 134 unsigned long mac_lo; 135 136 /* 137 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 138 * receive) 139 * Using channel 0 only - other channels are disabled 140 * */ 141 writel(0, &adap_emac->MACINDEX); 142 mac_hi = (dev->enetaddr[3] << 24) | 143 (dev->enetaddr[2] << 16) | 144 (dev->enetaddr[1] << 8) | 145 (dev->enetaddr[0]); 146 mac_lo = (dev->enetaddr[5] << 8) | 147 (dev->enetaddr[4]); 148 149 writel(mac_hi, &adap_emac->MACADDRHI); 150 #if defined(DAVINCI_EMAC_VERSION2) 151 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 152 &adap_emac->MACADDRLO); 153 #else 154 writel(mac_lo, &adap_emac->MACADDRLO); 155 #endif 156 157 writel(0, &adap_emac->MACHASH1); 158 writel(0, &adap_emac->MACHASH2); 159 160 /* Set source MAC address - REQUIRED */ 161 writel(mac_hi, &adap_emac->MACSRCADDRHI); 162 writel(mac_lo, &adap_emac->MACSRCADDRLO); 163 164 165 return 0; 166 } 167 168 static void davinci_eth_mdio_enable(void) 169 { 170 u_int32_t clkdiv; 171 172 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 173 174 writel((clkdiv & 0xff) | 175 MDIO_CONTROL_ENABLE | 176 MDIO_CONTROL_FAULT | 177 MDIO_CONTROL_FAULT_ENABLE, 178 &adap_mdio->CONTROL); 179 180 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 181 ; 182 } 183 184 /* 185 * Tries to find an active connected PHY. Returns 1 if address if found. 186 * If no active PHY (or more than one PHY) found returns 0. 187 * Sets active_phy_addr variable. 188 */ 189 static int davinci_eth_phy_detect(void) 190 { 191 u_int32_t phy_act_state; 192 int i; 193 int j; 194 unsigned int count = 0; 195 196 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) 197 active_phy_addr[i] = 0xff; 198 199 udelay(1000); 200 phy_act_state = readl(&adap_mdio->ALIVE); 201 202 if (phy_act_state == 0) 203 return 0; /* No active PHYs */ 204 205 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 206 207 for (i = 0, j = 0; i < 32; i++) 208 if (phy_act_state & (1 << i)) { 209 count++; 210 if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { 211 active_phy_addr[j++] = i; 212 } else { 213 printf("%s: to many PHYs detected.\n", 214 __func__); 215 count = 0; 216 break; 217 } 218 } 219 220 num_phy = count; 221 222 return count; 223 } 224 225 226 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 227 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 228 { 229 int tmp; 230 231 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 232 ; 233 234 writel(MDIO_USERACCESS0_GO | 235 MDIO_USERACCESS0_WRITE_READ | 236 ((reg_num & 0x1f) << 21) | 237 ((phy_addr & 0x1f) << 16), 238 &adap_mdio->USERACCESS0); 239 240 /* Wait for command to complete */ 241 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 242 ; 243 244 if (tmp & MDIO_USERACCESS0_ACK) { 245 *data = tmp & 0xffff; 246 return(1); 247 } 248 249 *data = -1; 250 return(0); 251 } 252 253 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 254 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 255 { 256 257 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 258 ; 259 260 writel(MDIO_USERACCESS0_GO | 261 MDIO_USERACCESS0_WRITE_WRITE | 262 ((reg_num & 0x1f) << 21) | 263 ((phy_addr & 0x1f) << 16) | 264 (data & 0xffff), 265 &adap_mdio->USERACCESS0); 266 267 /* Wait for command to complete */ 268 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 269 ; 270 271 return(1); 272 } 273 274 /* PHY functions for a generic PHY */ 275 static int gen_init_phy(int phy_addr) 276 { 277 int ret = 1; 278 279 if (gen_get_link_speed(phy_addr)) { 280 /* Try another time */ 281 ret = gen_get_link_speed(phy_addr); 282 } 283 284 return(ret); 285 } 286 287 static int gen_is_phy_connected(int phy_addr) 288 { 289 u_int16_t dummy; 290 291 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); 292 } 293 294 static int get_active_phy(void) 295 { 296 int i; 297 298 for (i = 0; i < num_phy; i++) 299 if (phy[i].get_link_speed(active_phy_addr[i])) 300 return i; 301 302 return -1; /* Return error if no link */ 303 } 304 305 static int gen_get_link_speed(int phy_addr) 306 { 307 u_int16_t tmp; 308 309 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 310 (tmp & 0x04)) { 311 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 312 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 313 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 314 315 /* Speed doesn't matter, there is no setting for it in EMAC. */ 316 if (tmp & (LPA_100FULL | LPA_10FULL)) { 317 /* set EMAC for Full Duplex */ 318 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 319 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 320 &adap_emac->MACCONTROL); 321 } else { 322 /*set EMAC for Half Duplex */ 323 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 324 &adap_emac->MACCONTROL); 325 } 326 327 if (tmp & (LPA_100FULL | LPA_100HALF)) 328 writel(readl(&adap_emac->MACCONTROL) | 329 EMAC_MACCONTROL_RMIISPEED_100, 330 &adap_emac->MACCONTROL); 331 else 332 writel(readl(&adap_emac->MACCONTROL) & 333 ~EMAC_MACCONTROL_RMIISPEED_100, 334 &adap_emac->MACCONTROL); 335 #endif 336 return(1); 337 } 338 339 return(0); 340 } 341 342 static int gen_auto_negotiate(int phy_addr) 343 { 344 u_int16_t tmp; 345 u_int16_t val; 346 unsigned long cntr = 0; 347 348 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 349 return 0; 350 351 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | 352 BMCR_SPEED100; 353 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 354 355 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) 356 return 0; 357 358 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | 359 ADVERTISE_10HALF); 360 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); 361 362 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 363 return(0); 364 365 /* Restart Auto_negotiation */ 366 tmp |= BMCR_ANRESTART; 367 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 368 369 /*check AutoNegotiate complete */ 370 do { 371 udelay(40000); 372 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 373 return 0; 374 375 if (tmp & BMSR_ANEGCOMPLETE) 376 break; 377 378 cntr++; 379 } while (cntr < 200); 380 381 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 382 return(0); 383 384 if (!(tmp & BMSR_ANEGCOMPLETE)) 385 return(0); 386 387 return(gen_get_link_speed(phy_addr)); 388 } 389 /* End of generic PHY functions */ 390 391 392 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 393 static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, 394 int reg) 395 { 396 unsigned short value = 0; 397 int retval = (davinci_eth_phy_read(addr, reg, &value) ? 0 : 1); 398 if (retval < 0) 399 return retval; 400 return value; 401 } 402 403 static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad, 404 int reg, u16 value) 405 { 406 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 407 } 408 #endif 409 410 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) 411 { 412 u_int16_t data; 413 414 if (davinci_eth_phy_read(phy_addr, 0, &data)) { 415 if (data & (1 << 6)) { /* speed selection MSB */ 416 /* 417 * Check if link detected is giga-bit 418 * If Gigabit mode detected, enable gigbit in MAC 419 */ 420 writel(readl(&adap_emac->MACCONTROL) | 421 EMAC_MACCONTROL_GIGFORCE | 422 EMAC_MACCONTROL_GIGABIT_ENABLE, 423 &adap_emac->MACCONTROL); 424 } 425 } 426 } 427 428 /* Eth device open */ 429 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 430 { 431 dv_reg_p addr; 432 u_int32_t clkdiv, cnt; 433 volatile emac_desc *rx_desc; 434 int index; 435 436 debug_emac("+ emac_open\n"); 437 438 /* Reset EMAC module and disable interrupts in wrapper */ 439 writel(1, &adap_emac->SOFTRESET); 440 while (readl(&adap_emac->SOFTRESET) != 0) 441 ; 442 #if defined(DAVINCI_EMAC_VERSION2) 443 writel(1, &adap_ewrap->softrst); 444 while (readl(&adap_ewrap->softrst) != 0) 445 ; 446 #else 447 writel(0, &adap_ewrap->EWCTL); 448 for (cnt = 0; cnt < 5; cnt++) { 449 clkdiv = readl(&adap_ewrap->EWCTL); 450 } 451 #endif 452 453 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 454 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 455 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 456 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 457 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 458 #endif 459 rx_desc = emac_rx_desc; 460 461 writel(1, &adap_emac->TXCONTROL); 462 writel(1, &adap_emac->RXCONTROL); 463 464 davinci_eth_set_mac_addr(dev); 465 466 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 467 addr = &adap_emac->TX0HDP; 468 for (cnt = 0; cnt < 8; cnt++) 469 writel(0, addr++); 470 471 addr = &adap_emac->RX0HDP; 472 for (cnt = 0; cnt < 8; cnt++) 473 writel(0, addr++); 474 475 /* Clear Statistics (do this before setting MacControl register) */ 476 addr = &adap_emac->RXGOODFRAMES; 477 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 478 writel(0, addr++); 479 480 /* No multicast addressing */ 481 writel(0, &adap_emac->MACHASH1); 482 writel(0, &adap_emac->MACHASH2); 483 484 /* Create RX queue and set receive process in place */ 485 emac_rx_active_head = emac_rx_desc; 486 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 487 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); 488 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; 489 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 490 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 491 rx_desc++; 492 } 493 494 /* Finalize the rx desc list */ 495 rx_desc--; 496 rx_desc->next = 0; 497 emac_rx_active_tail = rx_desc; 498 emac_rx_queue_active = 1; 499 500 davinci_flush_rx_descs(); 501 502 /* Enable TX/RX */ 503 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 504 writel(0, &adap_emac->RXBUFFEROFFSET); 505 506 /* 507 * No fancy configs - Use this for promiscous debug 508 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 509 */ 510 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 511 512 /* Enable ch 0 only */ 513 writel(1, &adap_emac->RXUNICASTSET); 514 515 /* Enable MII interface and Full duplex mode */ 516 #if defined(CONFIG_SOC_DA8XX) || \ 517 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) 518 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 519 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 520 EMAC_MACCONTROL_RMIISPEED_100), 521 &adap_emac->MACCONTROL); 522 #else 523 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 524 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 525 &adap_emac->MACCONTROL); 526 #endif 527 528 /* Init MDIO & get link state */ 529 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 530 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 531 &adap_mdio->CONTROL); 532 533 /* We need to wait for MDIO to start */ 534 udelay(1000); 535 536 index = get_active_phy(); 537 if (index == -1) 538 return(0); 539 540 emac_gigabit_enable(active_phy_addr[index]); 541 542 /* Start receive process */ 543 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); 544 545 debug_emac("- emac_open\n"); 546 547 return(1); 548 } 549 550 /* EMAC Channel Teardown */ 551 static void davinci_eth_ch_teardown(int ch) 552 { 553 dv_reg dly = 0xff; 554 dv_reg cnt; 555 556 debug_emac("+ emac_ch_teardown\n"); 557 558 if (ch == EMAC_CH_TX) { 559 /* Init TX channel teardown */ 560 writel(0, &adap_emac->TXTEARDOWN); 561 do { 562 /* 563 * Wait here for Tx teardown completion interrupt to 564 * occur. Note: A task delay can be called here to pend 565 * rather than occupying CPU cycles - anyway it has 566 * been found that teardown takes very few cpu cycles 567 * and does not affect functionality 568 */ 569 dly--; 570 udelay(1); 571 if (dly == 0) 572 break; 573 cnt = readl(&adap_emac->TX0CP); 574 } while (cnt != 0xfffffffc); 575 writel(cnt, &adap_emac->TX0CP); 576 writel(0, &adap_emac->TX0HDP); 577 } else { 578 /* Init RX channel teardown */ 579 writel(0, &adap_emac->RXTEARDOWN); 580 do { 581 /* 582 * Wait here for Rx teardown completion interrupt to 583 * occur. Note: A task delay can be called here to pend 584 * rather than occupying CPU cycles - anyway it has 585 * been found that teardown takes very few cpu cycles 586 * and does not affect functionality 587 */ 588 dly--; 589 udelay(1); 590 if (dly == 0) 591 break; 592 cnt = readl(&adap_emac->RX0CP); 593 } while (cnt != 0xfffffffc); 594 writel(cnt, &adap_emac->RX0CP); 595 writel(0, &adap_emac->RX0HDP); 596 } 597 598 debug_emac("- emac_ch_teardown\n"); 599 } 600 601 /* Eth device close */ 602 static void davinci_eth_close(struct eth_device *dev) 603 { 604 debug_emac("+ emac_close\n"); 605 606 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 607 if (readl(&adap_emac->RXCONTROL) & 1) 608 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 609 610 /* Reset EMAC module and disable interrupts in wrapper */ 611 writel(1, &adap_emac->SOFTRESET); 612 #if defined(DAVINCI_EMAC_VERSION2) 613 writel(1, &adap_ewrap->softrst); 614 #else 615 writel(0, &adap_ewrap->EWCTL); 616 #endif 617 618 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 619 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 620 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 621 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 622 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 623 #endif 624 debug_emac("- emac_close\n"); 625 } 626 627 static int tx_send_loop = 0; 628 629 /* 630 * This function sends a single packet on the network and returns 631 * positive number (number of bytes transmitted) or negative for error 632 */ 633 static int davinci_eth_send_packet (struct eth_device *dev, 634 void *packet, int length) 635 { 636 int ret_status = -1; 637 int index; 638 tx_send_loop = 0; 639 640 index = get_active_phy(); 641 if (index == -1) { 642 printf(" WARN: emac_send_packet: No link\n"); 643 return (ret_status); 644 } 645 646 emac_gigabit_enable(active_phy_addr[index]); 647 648 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 649 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 650 length = EMAC_MIN_ETHERNET_PKT_SIZE; 651 } 652 653 /* Populate the TX descriptor */ 654 emac_tx_desc->next = 0; 655 emac_tx_desc->buffer = (u_int8_t *) packet; 656 emac_tx_desc->buff_off_len = (length & 0xffff); 657 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 658 EMAC_CPPI_SOP_BIT | 659 EMAC_CPPI_OWNERSHIP_BIT | 660 EMAC_CPPI_EOP_BIT); 661 662 flush_dcache_range((unsigned long)packet, 663 (unsigned long)packet + length); 664 davinci_flush_desc(emac_tx_desc); 665 666 /* Send the packet */ 667 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); 668 669 /* Wait for packet to complete or link down */ 670 while (1) { 671 if (!phy[index].get_link_speed(active_phy_addr[index])) { 672 davinci_eth_ch_teardown (EMAC_CH_TX); 673 return (ret_status); 674 } 675 676 emac_gigabit_enable(active_phy_addr[index]); 677 678 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 679 ret_status = length; 680 break; 681 } 682 tx_send_loop++; 683 } 684 685 return (ret_status); 686 } 687 688 /* 689 * This function handles receipt of a packet from the network 690 */ 691 static int davinci_eth_rcv_packet (struct eth_device *dev) 692 { 693 volatile emac_desc *rx_curr_desc; 694 volatile emac_desc *curr_desc; 695 volatile emac_desc *tail_desc; 696 int status, ret = -1; 697 698 davinci_invalidate_rx_descs(); 699 700 rx_curr_desc = emac_rx_active_head; 701 if (!rx_curr_desc) 702 return 0; 703 status = rx_curr_desc->pkt_flag_len; 704 if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) { 705 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 706 /* Error in packet - discard it and requeue desc */ 707 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 708 } else { 709 unsigned long tmp = (unsigned long)rx_curr_desc->buffer; 710 711 invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); 712 net_process_received_packet( 713 rx_curr_desc->buffer, 714 rx_curr_desc->buff_off_len & 0xffff); 715 ret = rx_curr_desc->buff_off_len & 0xffff; 716 } 717 718 /* Ack received packet descriptor */ 719 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); 720 curr_desc = rx_curr_desc; 721 emac_rx_active_head = 722 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); 723 724 if (status & EMAC_CPPI_EOQ_BIT) { 725 if (emac_rx_active_head) { 726 writel(BD_TO_HW((ulong)emac_rx_active_head), 727 &adap_emac->RX0HDP); 728 } else { 729 emac_rx_queue_active = 0; 730 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 731 } 732 } 733 734 /* Recycle RX descriptor */ 735 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 736 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 737 rx_curr_desc->next = 0; 738 davinci_flush_desc(rx_curr_desc); 739 740 if (emac_rx_active_head == 0) { 741 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 742 emac_rx_active_head = curr_desc; 743 emac_rx_active_tail = curr_desc; 744 if (emac_rx_queue_active != 0) { 745 writel(BD_TO_HW((ulong)emac_rx_active_head), 746 &adap_emac->RX0HDP); 747 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 748 emac_rx_queue_active = 1; 749 } 750 } else { 751 tail_desc = emac_rx_active_tail; 752 emac_rx_active_tail = curr_desc; 753 tail_desc->next = BD_TO_HW((ulong) curr_desc); 754 status = tail_desc->pkt_flag_len; 755 if (status & EMAC_CPPI_EOQ_BIT) { 756 davinci_flush_desc(tail_desc); 757 writel(BD_TO_HW((ulong)curr_desc), 758 &adap_emac->RX0HDP); 759 status &= ~EMAC_CPPI_EOQ_BIT; 760 tail_desc->pkt_flag_len = status; 761 } 762 davinci_flush_desc(tail_desc); 763 } 764 return (ret); 765 } 766 return (0); 767 } 768 769 /* 770 * This function initializes the emac hardware. It does NOT initialize 771 * EMAC modules power or pin multiplexors, that is done by board_init() 772 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 773 */ 774 int davinci_emac_initialize(void) 775 { 776 u_int32_t phy_id; 777 u_int16_t tmp; 778 int i; 779 int ret; 780 struct eth_device *dev; 781 782 dev = malloc(sizeof *dev); 783 784 if (dev == NULL) 785 return -1; 786 787 memset(dev, 0, sizeof *dev); 788 strcpy(dev->name, "DaVinci-EMAC"); 789 790 dev->iobase = 0; 791 dev->init = davinci_eth_open; 792 dev->halt = davinci_eth_close; 793 dev->send = davinci_eth_send_packet; 794 dev->recv = davinci_eth_rcv_packet; 795 dev->write_hwaddr = davinci_eth_set_mac_addr; 796 797 eth_register(dev); 798 799 davinci_eth_mdio_enable(); 800 801 /* let the EMAC detect the PHYs */ 802 udelay(5000); 803 804 for (i = 0; i < 256; i++) { 805 if (readl(&adap_mdio->ALIVE)) 806 break; 807 udelay(1000); 808 } 809 810 if (i >= 256) { 811 printf("No ETH PHY detected!!!\n"); 812 return(0); 813 } 814 815 /* Find if PHY(s) is/are connected */ 816 ret = davinci_eth_phy_detect(); 817 if (!ret) 818 return(0); 819 else 820 debug_emac(" %d ETH PHY detected\n", ret); 821 822 /* Get PHY ID and initialize phy_ops for a detected PHY */ 823 for (i = 0; i < num_phy; i++) { 824 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, 825 &tmp)) { 826 active_phy_addr[i] = 0xff; 827 continue; 828 } 829 830 phy_id = (tmp << 16) & 0xffff0000; 831 832 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, 833 &tmp)) { 834 active_phy_addr[i] = 0xff; 835 continue; 836 } 837 838 phy_id |= tmp & 0x0000ffff; 839 840 switch (phy_id) { 841 #ifdef PHY_KSZ8873 842 case PHY_KSZ8873: 843 sprintf(phy[i].name, "KSZ8873 @ 0x%02x", 844 active_phy_addr[i]); 845 phy[i].init = ksz8873_init_phy; 846 phy[i].is_phy_connected = ksz8873_is_phy_connected; 847 phy[i].get_link_speed = ksz8873_get_link_speed; 848 phy[i].auto_negotiate = ksz8873_auto_negotiate; 849 break; 850 #endif 851 #ifdef PHY_LXT972 852 case PHY_LXT972: 853 sprintf(phy[i].name, "LXT972 @ 0x%02x", 854 active_phy_addr[i]); 855 phy[i].init = lxt972_init_phy; 856 phy[i].is_phy_connected = lxt972_is_phy_connected; 857 phy[i].get_link_speed = lxt972_get_link_speed; 858 phy[i].auto_negotiate = lxt972_auto_negotiate; 859 break; 860 #endif 861 #ifdef PHY_DP83848 862 case PHY_DP83848: 863 sprintf(phy[i].name, "DP83848 @ 0x%02x", 864 active_phy_addr[i]); 865 phy[i].init = dp83848_init_phy; 866 phy[i].is_phy_connected = dp83848_is_phy_connected; 867 phy[i].get_link_speed = dp83848_get_link_speed; 868 phy[i].auto_negotiate = dp83848_auto_negotiate; 869 break; 870 #endif 871 #ifdef PHY_ET1011C 872 case PHY_ET1011C: 873 sprintf(phy[i].name, "ET1011C @ 0x%02x", 874 active_phy_addr[i]); 875 phy[i].init = gen_init_phy; 876 phy[i].is_phy_connected = gen_is_phy_connected; 877 phy[i].get_link_speed = et1011c_get_link_speed; 878 phy[i].auto_negotiate = gen_auto_negotiate; 879 break; 880 #endif 881 default: 882 sprintf(phy[i].name, "GENERIC @ 0x%02x", 883 active_phy_addr[i]); 884 phy[i].init = gen_init_phy; 885 phy[i].is_phy_connected = gen_is_phy_connected; 886 phy[i].get_link_speed = gen_get_link_speed; 887 phy[i].auto_negotiate = gen_auto_negotiate; 888 } 889 890 debug("Ethernet PHY: %s\n", phy[i].name); 891 892 int retval; 893 struct mii_dev *mdiodev = mdio_alloc(); 894 if (!mdiodev) 895 return -ENOMEM; 896 strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); 897 mdiodev->read = davinci_mii_phy_read; 898 mdiodev->write = davinci_mii_phy_write; 899 900 retval = mdio_register(mdiodev); 901 if (retval < 0) 902 return retval; 903 } 904 905 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 906 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ 907 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) 908 for (i = 0; i < num_phy; i++) { 909 if (phy[i].is_phy_connected(i)) 910 phy[i].auto_negotiate(i); 911 } 912 #endif 913 return(1); 914 } 915