1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License as published by 21 * the Free Software Foundation; either version 2 of the License, or 22 * (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 32 * ---------------------------------------------------------------------------- 33 34 * Modifications: 35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 37 * 38 */ 39 #include <common.h> 40 #include <command.h> 41 #include <net.h> 42 #include <miiphy.h> 43 #include <malloc.h> 44 #include <asm/arch/emac_defs.h> 45 #include <asm/io.h> 46 47 unsigned int emac_dbg = 0; 48 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 49 50 #ifdef DAVINCI_EMAC_GIG_ENABLE 51 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) 52 #else 53 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ 54 #endif 55 56 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) 57 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ 58 EMAC_MDIO_CLOCK_FREQ) - 1) 59 #endif 60 61 static void davinci_eth_mdio_enable(void); 62 63 static int gen_init_phy(int phy_addr); 64 static int gen_is_phy_connected(int phy_addr); 65 static int gen_get_link_speed(int phy_addr); 66 static int gen_auto_negotiate(int phy_addr); 67 68 void eth_mdio_enable(void) 69 { 70 davinci_eth_mdio_enable(); 71 } 72 73 /* EMAC Addresses */ 74 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 75 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 76 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 77 78 /* EMAC descriptors */ 79 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 80 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 81 static volatile emac_desc *emac_rx_active_head = 0; 82 static volatile emac_desc *emac_rx_active_tail = 0; 83 static int emac_rx_queue_active = 0; 84 85 /* Receive packet buffers */ 86 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 87 88 #define MAX_PHY 3 89 90 /* PHY address for a discovered PHY (0xff - not found) */ 91 static u_int8_t active_phy_addr[MAX_PHY] = { 0xff, 0xff, 0xff }; 92 93 /* number of PHY found active */ 94 static u_int8_t num_phy; 95 96 phy_t phy[MAX_PHY]; 97 98 static int davinci_eth_set_mac_addr(struct eth_device *dev) 99 { 100 unsigned long mac_hi; 101 unsigned long mac_lo; 102 103 /* 104 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 105 * receive) 106 * Using channel 0 only - other channels are disabled 107 * */ 108 writel(0, &adap_emac->MACINDEX); 109 mac_hi = (dev->enetaddr[3] << 24) | 110 (dev->enetaddr[2] << 16) | 111 (dev->enetaddr[1] << 8) | 112 (dev->enetaddr[0]); 113 mac_lo = (dev->enetaddr[5] << 8) | 114 (dev->enetaddr[4]); 115 116 writel(mac_hi, &adap_emac->MACADDRHI); 117 #if defined(DAVINCI_EMAC_VERSION2) 118 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 119 &adap_emac->MACADDRLO); 120 #else 121 writel(mac_lo, &adap_emac->MACADDRLO); 122 #endif 123 124 writel(0, &adap_emac->MACHASH1); 125 writel(0, &adap_emac->MACHASH2); 126 127 /* Set source MAC address - REQUIRED */ 128 writel(mac_hi, &adap_emac->MACSRCADDRHI); 129 writel(mac_lo, &adap_emac->MACSRCADDRLO); 130 131 132 return 0; 133 } 134 135 static void davinci_eth_mdio_enable(void) 136 { 137 u_int32_t clkdiv; 138 139 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 140 141 writel((clkdiv & 0xff) | 142 MDIO_CONTROL_ENABLE | 143 MDIO_CONTROL_FAULT | 144 MDIO_CONTROL_FAULT_ENABLE, 145 &adap_mdio->CONTROL); 146 147 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 148 ; 149 } 150 151 /* 152 * Tries to find an active connected PHY. Returns 1 if address if found. 153 * If no active PHY (or more than one PHY) found returns 0. 154 * Sets active_phy_addr variable. 155 */ 156 static int davinci_eth_phy_detect(void) 157 { 158 u_int32_t phy_act_state; 159 int i; 160 int j; 161 unsigned int count = 0; 162 163 active_phy_addr[0] = 0xff; 164 active_phy_addr[1] = 0xff; 165 active_phy_addr[2] = 0xff; 166 167 udelay(1000); 168 phy_act_state = readl(&adap_mdio->ALIVE); 169 170 if (phy_act_state == 0) 171 return 0; /* No active PHYs */ 172 173 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 174 175 for (i = 0, j = 0; i < 32; i++) 176 if (phy_act_state & (1 << i)) { 177 count++; 178 active_phy_addr[j++] = i; 179 } 180 181 num_phy = count; 182 183 return count; 184 } 185 186 187 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 188 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 189 { 190 int tmp; 191 192 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 193 ; 194 195 writel(MDIO_USERACCESS0_GO | 196 MDIO_USERACCESS0_WRITE_READ | 197 ((reg_num & 0x1f) << 21) | 198 ((phy_addr & 0x1f) << 16), 199 &adap_mdio->USERACCESS0); 200 201 /* Wait for command to complete */ 202 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 203 ; 204 205 if (tmp & MDIO_USERACCESS0_ACK) { 206 *data = tmp & 0xffff; 207 return(1); 208 } 209 210 *data = -1; 211 return(0); 212 } 213 214 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 215 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 216 { 217 218 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 219 ; 220 221 writel(MDIO_USERACCESS0_GO | 222 MDIO_USERACCESS0_WRITE_WRITE | 223 ((reg_num & 0x1f) << 21) | 224 ((phy_addr & 0x1f) << 16) | 225 (data & 0xffff), 226 &adap_mdio->USERACCESS0); 227 228 /* Wait for command to complete */ 229 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 230 ; 231 232 return(1); 233 } 234 235 /* PHY functions for a generic PHY */ 236 static int gen_init_phy(int phy_addr) 237 { 238 int ret = 1; 239 240 if (gen_get_link_speed(phy_addr)) { 241 /* Try another time */ 242 ret = gen_get_link_speed(phy_addr); 243 } 244 245 return(ret); 246 } 247 248 static int gen_is_phy_connected(int phy_addr) 249 { 250 u_int16_t dummy; 251 252 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); 253 } 254 255 static int get_active_phy(void) 256 { 257 int i; 258 259 for (i = 0; i < num_phy; i++) 260 if (phy[i].get_link_speed(active_phy_addr[i])) 261 return i; 262 263 return -1; /* Return error if no link */ 264 } 265 266 static int gen_get_link_speed(int phy_addr) 267 { 268 u_int16_t tmp; 269 270 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 271 (tmp & 0x04)) { 272 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 273 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 274 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 275 276 /* Speed doesn't matter, there is no setting for it in EMAC. */ 277 if (tmp & (LPA_100FULL | LPA_10FULL)) { 278 /* set EMAC for Full Duplex */ 279 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 280 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 281 &adap_emac->MACCONTROL); 282 } else { 283 /*set EMAC for Half Duplex */ 284 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 285 &adap_emac->MACCONTROL); 286 } 287 288 if (tmp & (LPA_100FULL | LPA_100HALF)) 289 writel(readl(&adap_emac->MACCONTROL) | 290 EMAC_MACCONTROL_RMIISPEED_100, 291 &adap_emac->MACCONTROL); 292 else 293 writel(readl(&adap_emac->MACCONTROL) & 294 ~EMAC_MACCONTROL_RMIISPEED_100, 295 &adap_emac->MACCONTROL); 296 #endif 297 return(1); 298 } 299 300 return(0); 301 } 302 303 static int gen_auto_negotiate(int phy_addr) 304 { 305 u_int16_t tmp; 306 u_int16_t val; 307 unsigned long cntr = 0; 308 309 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 310 return 0; 311 312 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | 313 BMCR_SPEED100; 314 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 315 316 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) 317 return 0; 318 319 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | 320 ADVERTISE_10HALF); 321 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); 322 323 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 324 return(0); 325 326 /* Restart Auto_negotiation */ 327 tmp |= BMCR_ANRESTART; 328 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 329 330 /*check AutoNegotiate complete */ 331 do { 332 udelay(40000); 333 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 334 return 0; 335 336 if (tmp & BMSR_ANEGCOMPLETE) 337 break; 338 339 cntr++; 340 } while (cntr < 200); 341 342 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 343 return(0); 344 345 if (!(tmp & BMSR_ANEGCOMPLETE)) 346 return(0); 347 348 return(gen_get_link_speed(phy_addr)); 349 } 350 /* End of generic PHY functions */ 351 352 353 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 354 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) 355 { 356 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); 357 } 358 359 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) 360 { 361 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 362 } 363 #endif 364 365 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) 366 { 367 u_int16_t data; 368 369 if (davinci_eth_phy_read(phy_addr, 0, &data)) { 370 if (data & (1 << 6)) { /* speed selection MSB */ 371 /* 372 * Check if link detected is giga-bit 373 * If Gigabit mode detected, enable gigbit in MAC 374 */ 375 writel(readl(&adap_emac->MACCONTROL) | 376 EMAC_MACCONTROL_GIGFORCE | 377 EMAC_MACCONTROL_GIGABIT_ENABLE, 378 &adap_emac->MACCONTROL); 379 } 380 } 381 } 382 383 /* Eth device open */ 384 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 385 { 386 dv_reg_p addr; 387 u_int32_t clkdiv, cnt; 388 volatile emac_desc *rx_desc; 389 int index; 390 391 debug_emac("+ emac_open\n"); 392 393 /* Reset EMAC module and disable interrupts in wrapper */ 394 writel(1, &adap_emac->SOFTRESET); 395 while (readl(&adap_emac->SOFTRESET) != 0) 396 ; 397 #if defined(DAVINCI_EMAC_VERSION2) 398 writel(1, &adap_ewrap->softrst); 399 while (readl(&adap_ewrap->softrst) != 0) 400 ; 401 #else 402 writel(0, &adap_ewrap->EWCTL); 403 for (cnt = 0; cnt < 5; cnt++) { 404 clkdiv = readl(&adap_ewrap->EWCTL); 405 } 406 #endif 407 408 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 409 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 410 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 411 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 412 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 413 #endif 414 rx_desc = emac_rx_desc; 415 416 writel(1, &adap_emac->TXCONTROL); 417 writel(1, &adap_emac->RXCONTROL); 418 419 davinci_eth_set_mac_addr(dev); 420 421 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 422 addr = &adap_emac->TX0HDP; 423 for(cnt = 0; cnt < 16; cnt++) 424 writel(0, addr++); 425 426 addr = &adap_emac->RX0HDP; 427 for(cnt = 0; cnt < 16; cnt++) 428 writel(0, addr++); 429 430 /* Clear Statistics (do this before setting MacControl register) */ 431 addr = &adap_emac->RXGOODFRAMES; 432 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 433 writel(0, addr++); 434 435 /* No multicast addressing */ 436 writel(0, &adap_emac->MACHASH1); 437 writel(0, &adap_emac->MACHASH2); 438 439 /* Create RX queue and set receive process in place */ 440 emac_rx_active_head = emac_rx_desc; 441 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 442 rx_desc->next = (u_int32_t)(rx_desc + 1); 443 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 444 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 445 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 446 rx_desc++; 447 } 448 449 /* Finalize the rx desc list */ 450 rx_desc--; 451 rx_desc->next = 0; 452 emac_rx_active_tail = rx_desc; 453 emac_rx_queue_active = 1; 454 455 /* Enable TX/RX */ 456 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 457 writel(0, &adap_emac->RXBUFFEROFFSET); 458 459 /* 460 * No fancy configs - Use this for promiscous debug 461 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 462 */ 463 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 464 465 /* Enable ch 0 only */ 466 writel(1, &adap_emac->RXUNICASTSET); 467 468 /* Enable MII interface and Full duplex mode */ 469 #ifdef CONFIG_SOC_DA8XX 470 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 471 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 472 EMAC_MACCONTROL_RMIISPEED_100), 473 &adap_emac->MACCONTROL); 474 #else 475 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 476 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 477 &adap_emac->MACCONTROL); 478 #endif 479 480 /* Init MDIO & get link state */ 481 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 482 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 483 &adap_mdio->CONTROL); 484 485 /* We need to wait for MDIO to start */ 486 udelay(1000); 487 488 index = get_active_phy(); 489 if (index == -1) 490 return(0); 491 492 emac_gigabit_enable(active_phy_addr[index]); 493 494 /* Start receive process */ 495 writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); 496 497 debug_emac("- emac_open\n"); 498 499 return(1); 500 } 501 502 /* EMAC Channel Teardown */ 503 static void davinci_eth_ch_teardown(int ch) 504 { 505 dv_reg dly = 0xff; 506 dv_reg cnt; 507 508 debug_emac("+ emac_ch_teardown\n"); 509 510 if (ch == EMAC_CH_TX) { 511 /* Init TX channel teardown */ 512 writel(0, &adap_emac->TXTEARDOWN); 513 do { 514 /* 515 * Wait here for Tx teardown completion interrupt to 516 * occur. Note: A task delay can be called here to pend 517 * rather than occupying CPU cycles - anyway it has 518 * been found that teardown takes very few cpu cycles 519 * and does not affect functionality 520 */ 521 dly--; 522 udelay(1); 523 if (dly == 0) 524 break; 525 cnt = readl(&adap_emac->TX0CP); 526 } while (cnt != 0xfffffffc); 527 writel(cnt, &adap_emac->TX0CP); 528 writel(0, &adap_emac->TX0HDP); 529 } else { 530 /* Init RX channel teardown */ 531 writel(0, &adap_emac->RXTEARDOWN); 532 do { 533 /* 534 * Wait here for Rx teardown completion interrupt to 535 * occur. Note: A task delay can be called here to pend 536 * rather than occupying CPU cycles - anyway it has 537 * been found that teardown takes very few cpu cycles 538 * and does not affect functionality 539 */ 540 dly--; 541 udelay(1); 542 if (dly == 0) 543 break; 544 cnt = readl(&adap_emac->RX0CP); 545 } while (cnt != 0xfffffffc); 546 writel(cnt, &adap_emac->RX0CP); 547 writel(0, &adap_emac->RX0HDP); 548 } 549 550 debug_emac("- emac_ch_teardown\n"); 551 } 552 553 /* Eth device close */ 554 static void davinci_eth_close(struct eth_device *dev) 555 { 556 debug_emac("+ emac_close\n"); 557 558 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 559 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 560 561 /* Reset EMAC module and disable interrupts in wrapper */ 562 writel(1, &adap_emac->SOFTRESET); 563 #if defined(DAVINCI_EMAC_VERSION2) 564 writel(1, &adap_ewrap->softrst); 565 #else 566 writel(0, &adap_ewrap->EWCTL); 567 #endif 568 569 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 570 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 571 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 572 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 573 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 574 #endif 575 debug_emac("- emac_close\n"); 576 } 577 578 static int tx_send_loop = 0; 579 580 /* 581 * This function sends a single packet on the network and returns 582 * positive number (number of bytes transmitted) or negative for error 583 */ 584 static int davinci_eth_send_packet (struct eth_device *dev, 585 volatile void *packet, int length) 586 { 587 int ret_status = -1; 588 int index; 589 tx_send_loop = 0; 590 591 index = get_active_phy(); 592 if (index == -1) { 593 printf(" WARN: emac_send_packet: No link\n"); 594 return (ret_status); 595 } 596 597 emac_gigabit_enable(active_phy_addr[index]); 598 599 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 600 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 601 length = EMAC_MIN_ETHERNET_PKT_SIZE; 602 } 603 604 /* Populate the TX descriptor */ 605 emac_tx_desc->next = 0; 606 emac_tx_desc->buffer = (u_int8_t *) packet; 607 emac_tx_desc->buff_off_len = (length & 0xffff); 608 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 609 EMAC_CPPI_SOP_BIT | 610 EMAC_CPPI_OWNERSHIP_BIT | 611 EMAC_CPPI_EOP_BIT); 612 /* Send the packet */ 613 writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); 614 615 /* Wait for packet to complete or link down */ 616 while (1) { 617 if (!phy[index].get_link_speed(active_phy_addr[index])) { 618 davinci_eth_ch_teardown (EMAC_CH_TX); 619 return (ret_status); 620 } 621 622 emac_gigabit_enable(active_phy_addr[index]); 623 624 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 625 ret_status = length; 626 break; 627 } 628 tx_send_loop++; 629 } 630 631 return (ret_status); 632 } 633 634 /* 635 * This function handles receipt of a packet from the network 636 */ 637 static int davinci_eth_rcv_packet (struct eth_device *dev) 638 { 639 volatile emac_desc *rx_curr_desc; 640 volatile emac_desc *curr_desc; 641 volatile emac_desc *tail_desc; 642 int status, ret = -1; 643 644 rx_curr_desc = emac_rx_active_head; 645 status = rx_curr_desc->pkt_flag_len; 646 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { 647 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 648 /* Error in packet - discard it and requeue desc */ 649 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 650 } else { 651 NetReceive (rx_curr_desc->buffer, 652 (rx_curr_desc->buff_off_len & 0xffff)); 653 ret = rx_curr_desc->buff_off_len & 0xffff; 654 } 655 656 /* Ack received packet descriptor */ 657 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); 658 curr_desc = rx_curr_desc; 659 emac_rx_active_head = 660 (volatile emac_desc *) rx_curr_desc->next; 661 662 if (status & EMAC_CPPI_EOQ_BIT) { 663 if (emac_rx_active_head) { 664 writel((unsigned long)emac_rx_active_head, 665 &adap_emac->RX0HDP); 666 } else { 667 emac_rx_queue_active = 0; 668 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 669 } 670 } 671 672 /* Recycle RX descriptor */ 673 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 674 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 675 rx_curr_desc->next = 0; 676 677 if (emac_rx_active_head == 0) { 678 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 679 emac_rx_active_head = curr_desc; 680 emac_rx_active_tail = curr_desc; 681 if (emac_rx_queue_active != 0) { 682 writel((unsigned long)emac_rx_active_head, 683 &adap_emac->RX0HDP); 684 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 685 emac_rx_queue_active = 1; 686 } 687 } else { 688 tail_desc = emac_rx_active_tail; 689 emac_rx_active_tail = curr_desc; 690 tail_desc->next = (unsigned int) curr_desc; 691 status = tail_desc->pkt_flag_len; 692 if (status & EMAC_CPPI_EOQ_BIT) { 693 writel((unsigned long)curr_desc, 694 &adap_emac->RX0HDP); 695 status &= ~EMAC_CPPI_EOQ_BIT; 696 tail_desc->pkt_flag_len = status; 697 } 698 } 699 return (ret); 700 } 701 return (0); 702 } 703 704 /* 705 * This function initializes the emac hardware. It does NOT initialize 706 * EMAC modules power or pin multiplexors, that is done by board_init() 707 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 708 */ 709 int davinci_emac_initialize(void) 710 { 711 u_int32_t phy_id; 712 u_int16_t tmp; 713 int i; 714 int ret; 715 struct eth_device *dev; 716 717 dev = malloc(sizeof *dev); 718 719 if (dev == NULL) 720 return -1; 721 722 memset(dev, 0, sizeof *dev); 723 sprintf(dev->name, "DaVinci-EMAC"); 724 725 dev->iobase = 0; 726 dev->init = davinci_eth_open; 727 dev->halt = davinci_eth_close; 728 dev->send = davinci_eth_send_packet; 729 dev->recv = davinci_eth_rcv_packet; 730 dev->write_hwaddr = davinci_eth_set_mac_addr; 731 732 eth_register(dev); 733 734 davinci_eth_mdio_enable(); 735 736 /* let the EMAC detect the PHYs */ 737 udelay(5000); 738 739 for (i = 0; i < 256; i++) { 740 if (readl(&adap_mdio->ALIVE)) 741 break; 742 udelay(1000); 743 } 744 745 if (i >= 256) { 746 printf("No ETH PHY detected!!!\n"); 747 return(0); 748 } 749 750 /* Find if PHY(s) is/are connected */ 751 ret = davinci_eth_phy_detect(); 752 if (!ret) 753 return(0); 754 else 755 printf(" %d ETH PHY detected\n", ret); 756 757 /* Get PHY ID and initialize phy_ops for a detected PHY */ 758 for (i = 0; i < num_phy; i++) { 759 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, 760 &tmp)) { 761 active_phy_addr[i] = 0xff; 762 continue; 763 } 764 765 phy_id = (tmp << 16) & 0xffff0000; 766 767 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, 768 &tmp)) { 769 active_phy_addr[i] = 0xff; 770 continue; 771 } 772 773 phy_id |= tmp & 0x0000ffff; 774 775 switch (phy_id) { 776 case PHY_KSZ8873: 777 sprintf(phy[i].name, "KSZ8873 @ 0x%02x", 778 active_phy_addr[i]); 779 phy[i].init = ksz8873_init_phy; 780 phy[i].is_phy_connected = ksz8873_is_phy_connected; 781 phy[i].get_link_speed = ksz8873_get_link_speed; 782 phy[i].auto_negotiate = ksz8873_auto_negotiate; 783 break; 784 case PHY_LXT972: 785 sprintf(phy[i].name, "LXT972 @ 0x%02x", 786 active_phy_addr[i]); 787 phy[i].init = lxt972_init_phy; 788 phy[i].is_phy_connected = lxt972_is_phy_connected; 789 phy[i].get_link_speed = lxt972_get_link_speed; 790 phy[i].auto_negotiate = lxt972_auto_negotiate; 791 break; 792 case PHY_DP83848: 793 sprintf(phy[i].name, "DP83848 @ 0x%02x", 794 active_phy_addr[i]); 795 phy[i].init = dp83848_init_phy; 796 phy[i].is_phy_connected = dp83848_is_phy_connected; 797 phy[i].get_link_speed = dp83848_get_link_speed; 798 phy[i].auto_negotiate = dp83848_auto_negotiate; 799 break; 800 case PHY_ET1011C: 801 sprintf(phy[i].name, "ET1011C @ 0x%02x", 802 active_phy_addr[i]); 803 phy[i].init = gen_init_phy; 804 phy[i].is_phy_connected = gen_is_phy_connected; 805 phy[i].get_link_speed = et1011c_get_link_speed; 806 phy[i].auto_negotiate = gen_auto_negotiate; 807 break; 808 default: 809 sprintf(phy[i].name, "GENERIC @ 0x%02x", 810 active_phy_addr[i]); 811 phy[i].init = gen_init_phy; 812 phy[i].is_phy_connected = gen_is_phy_connected; 813 phy[i].get_link_speed = gen_get_link_speed; 814 phy[i].auto_negotiate = gen_auto_negotiate; 815 } 816 817 debug("Ethernet PHY: %s\n", phy[i].name); 818 819 miiphy_register(phy[i].name, davinci_mii_phy_read, 820 davinci_mii_phy_write); 821 } 822 return(1); 823 } 824