1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 * 21 * Modifications: 22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 23 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 24 */ 25 #include <common.h> 26 #include <command.h> 27 #include <net.h> 28 #include <miiphy.h> 29 #include <malloc.h> 30 #include <netdev.h> 31 #include <linux/compiler.h> 32 #include <asm/arch/emac_defs.h> 33 #include <asm/io.h> 34 #include "davinci_emac.h" 35 36 unsigned int emac_dbg = 0; 37 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 38 39 #ifdef EMAC_HW_RAM_ADDR 40 static inline unsigned long BD_TO_HW(unsigned long x) 41 { 42 if (x == 0) 43 return 0; 44 45 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; 46 } 47 48 static inline unsigned long HW_TO_BD(unsigned long x) 49 { 50 if (x == 0) 51 return 0; 52 53 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; 54 } 55 #else 56 #define BD_TO_HW(x) (x) 57 #define HW_TO_BD(x) (x) 58 #endif 59 60 #ifdef DAVINCI_EMAC_GIG_ENABLE 61 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) 62 #else 63 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ 64 #endif 65 66 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) 67 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ 68 EMAC_MDIO_CLOCK_FREQ) - 1) 69 #endif 70 71 static void davinci_eth_mdio_enable(void); 72 73 static int gen_init_phy(int phy_addr); 74 static int gen_is_phy_connected(int phy_addr); 75 static int gen_get_link_speed(int phy_addr); 76 static int gen_auto_negotiate(int phy_addr); 77 78 void eth_mdio_enable(void) 79 { 80 davinci_eth_mdio_enable(); 81 } 82 83 /* EMAC Addresses */ 84 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 85 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 86 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 87 88 /* EMAC descriptors */ 89 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 90 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 91 static volatile emac_desc *emac_rx_active_head = 0; 92 static volatile emac_desc *emac_rx_active_tail = 0; 93 static int emac_rx_queue_active = 0; 94 95 /* Receive packet buffers */ 96 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] 97 __aligned(ARCH_DMA_MINALIGN); 98 99 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 100 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 101 #endif 102 103 /* PHY address for a discovered PHY (0xff - not found) */ 104 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 105 106 /* number of PHY found active */ 107 static u_int8_t num_phy; 108 109 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 110 111 static inline void davinci_flush_rx_descs(void) 112 { 113 /* flush the whole RX descs area */ 114 flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 115 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 116 } 117 118 static inline void davinci_invalidate_rx_descs(void) 119 { 120 /* invalidate the whole RX descs area */ 121 invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 122 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 123 } 124 125 static inline void davinci_flush_desc(emac_desc *desc) 126 { 127 flush_dcache_range((unsigned long)desc, 128 (unsigned long)desc + sizeof(*desc)); 129 } 130 131 static int davinci_eth_set_mac_addr(struct eth_device *dev) 132 { 133 unsigned long mac_hi; 134 unsigned long mac_lo; 135 136 /* 137 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 138 * receive) 139 * Using channel 0 only - other channels are disabled 140 * */ 141 writel(0, &adap_emac->MACINDEX); 142 mac_hi = (dev->enetaddr[3] << 24) | 143 (dev->enetaddr[2] << 16) | 144 (dev->enetaddr[1] << 8) | 145 (dev->enetaddr[0]); 146 mac_lo = (dev->enetaddr[5] << 8) | 147 (dev->enetaddr[4]); 148 149 writel(mac_hi, &adap_emac->MACADDRHI); 150 #if defined(DAVINCI_EMAC_VERSION2) 151 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 152 &adap_emac->MACADDRLO); 153 #else 154 writel(mac_lo, &adap_emac->MACADDRLO); 155 #endif 156 157 writel(0, &adap_emac->MACHASH1); 158 writel(0, &adap_emac->MACHASH2); 159 160 /* Set source MAC address - REQUIRED */ 161 writel(mac_hi, &adap_emac->MACSRCADDRHI); 162 writel(mac_lo, &adap_emac->MACSRCADDRLO); 163 164 165 return 0; 166 } 167 168 static void davinci_eth_mdio_enable(void) 169 { 170 u_int32_t clkdiv; 171 172 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 173 174 writel((clkdiv & 0xff) | 175 MDIO_CONTROL_ENABLE | 176 MDIO_CONTROL_FAULT | 177 MDIO_CONTROL_FAULT_ENABLE, 178 &adap_mdio->CONTROL); 179 180 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 181 ; 182 } 183 184 /* 185 * Tries to find an active connected PHY. Returns 1 if address if found. 186 * If no active PHY (or more than one PHY) found returns 0. 187 * Sets active_phy_addr variable. 188 */ 189 static int davinci_eth_phy_detect(void) 190 { 191 u_int32_t phy_act_state; 192 int i; 193 int j; 194 unsigned int count = 0; 195 196 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) 197 active_phy_addr[i] = 0xff; 198 199 udelay(1000); 200 phy_act_state = readl(&adap_mdio->ALIVE); 201 202 if (phy_act_state == 0) 203 return 0; /* No active PHYs */ 204 205 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 206 207 for (i = 0, j = 0; i < 32; i++) 208 if (phy_act_state & (1 << i)) { 209 count++; 210 if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { 211 active_phy_addr[j++] = i; 212 } else { 213 printf("%s: to many PHYs detected.\n", 214 __func__); 215 count = 0; 216 break; 217 } 218 } 219 220 num_phy = count; 221 222 return count; 223 } 224 225 226 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 227 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 228 { 229 int tmp; 230 231 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 232 ; 233 234 writel(MDIO_USERACCESS0_GO | 235 MDIO_USERACCESS0_WRITE_READ | 236 ((reg_num & 0x1f) << 21) | 237 ((phy_addr & 0x1f) << 16), 238 &adap_mdio->USERACCESS0); 239 240 /* Wait for command to complete */ 241 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 242 ; 243 244 if (tmp & MDIO_USERACCESS0_ACK) { 245 *data = tmp & 0xffff; 246 return 0; 247 } 248 249 return -EIO; 250 } 251 252 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 253 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 254 { 255 256 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 257 ; 258 259 writel(MDIO_USERACCESS0_GO | 260 MDIO_USERACCESS0_WRITE_WRITE | 261 ((reg_num & 0x1f) << 21) | 262 ((phy_addr & 0x1f) << 16) | 263 (data & 0xffff), 264 &adap_mdio->USERACCESS0); 265 266 /* Wait for command to complete */ 267 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 268 ; 269 270 return 0; 271 } 272 273 /* PHY functions for a generic PHY */ 274 static int gen_init_phy(int phy_addr) 275 { 276 int ret = 1; 277 278 if (gen_get_link_speed(phy_addr)) { 279 /* Try another time */ 280 ret = gen_get_link_speed(phy_addr); 281 } 282 283 return(ret); 284 } 285 286 static int gen_is_phy_connected(int phy_addr) 287 { 288 u_int16_t dummy; 289 290 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); 291 } 292 293 static int get_active_phy(void) 294 { 295 int i; 296 297 for (i = 0; i < num_phy; i++) 298 if (phy[i].get_link_speed(active_phy_addr[i])) 299 return i; 300 301 return -1; /* Return error if no link */ 302 } 303 304 static int gen_get_link_speed(int phy_addr) 305 { 306 u_int16_t tmp; 307 308 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 309 (tmp & 0x04)) { 310 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 311 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 312 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 313 314 /* Speed doesn't matter, there is no setting for it in EMAC. */ 315 if (tmp & (LPA_100FULL | LPA_10FULL)) { 316 /* set EMAC for Full Duplex */ 317 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 318 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 319 &adap_emac->MACCONTROL); 320 } else { 321 /*set EMAC for Half Duplex */ 322 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 323 &adap_emac->MACCONTROL); 324 } 325 326 if (tmp & (LPA_100FULL | LPA_100HALF)) 327 writel(readl(&adap_emac->MACCONTROL) | 328 EMAC_MACCONTROL_RMIISPEED_100, 329 &adap_emac->MACCONTROL); 330 else 331 writel(readl(&adap_emac->MACCONTROL) & 332 ~EMAC_MACCONTROL_RMIISPEED_100, 333 &adap_emac->MACCONTROL); 334 #endif 335 return(1); 336 } 337 338 return(0); 339 } 340 341 static int gen_auto_negotiate(int phy_addr) 342 { 343 u_int16_t tmp; 344 u_int16_t val; 345 unsigned long cntr = 0; 346 347 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 348 return 0; 349 350 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | 351 BMCR_SPEED100; 352 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 353 354 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) 355 return 0; 356 357 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | 358 ADVERTISE_10HALF); 359 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); 360 361 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 362 return(0); 363 364 /* Restart Auto_negotiation */ 365 tmp |= BMCR_ANRESTART; 366 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 367 368 /*check AutoNegotiate complete */ 369 do { 370 udelay(40000); 371 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 372 return 0; 373 374 if (tmp & BMSR_ANEGCOMPLETE) 375 break; 376 377 cntr++; 378 } while (cntr < 200); 379 380 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 381 return(0); 382 383 if (!(tmp & BMSR_ANEGCOMPLETE)) 384 return(0); 385 386 return(gen_get_link_speed(phy_addr)); 387 } 388 /* End of generic PHY functions */ 389 390 391 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 392 static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, 393 int reg) 394 { 395 unsigned short value = 0; 396 int retval = davinci_eth_phy_read(addr, reg, &value); 397 if (retval < 0) 398 return retval; 399 return value; 400 } 401 402 static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad, 403 int reg, u16 value) 404 { 405 return davinci_eth_phy_write(addr, reg, value); 406 } 407 #endif 408 409 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) 410 { 411 u_int16_t data; 412 413 if (davinci_eth_phy_read(phy_addr, 0, &data)) { 414 if (data & (1 << 6)) { /* speed selection MSB */ 415 /* 416 * Check if link detected is giga-bit 417 * If Gigabit mode detected, enable gigbit in MAC 418 */ 419 writel(readl(&adap_emac->MACCONTROL) | 420 EMAC_MACCONTROL_GIGFORCE | 421 EMAC_MACCONTROL_GIGABIT_ENABLE, 422 &adap_emac->MACCONTROL); 423 } 424 } 425 } 426 427 /* Eth device open */ 428 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 429 { 430 dv_reg_p addr; 431 u_int32_t clkdiv, cnt; 432 volatile emac_desc *rx_desc; 433 int index; 434 435 debug_emac("+ emac_open\n"); 436 437 /* Reset EMAC module and disable interrupts in wrapper */ 438 writel(1, &adap_emac->SOFTRESET); 439 while (readl(&adap_emac->SOFTRESET) != 0) 440 ; 441 #if defined(DAVINCI_EMAC_VERSION2) 442 writel(1, &adap_ewrap->softrst); 443 while (readl(&adap_ewrap->softrst) != 0) 444 ; 445 #else 446 writel(0, &adap_ewrap->EWCTL); 447 for (cnt = 0; cnt < 5; cnt++) { 448 clkdiv = readl(&adap_ewrap->EWCTL); 449 } 450 #endif 451 452 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 453 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 454 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 455 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 456 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 457 #endif 458 rx_desc = emac_rx_desc; 459 460 writel(1, &adap_emac->TXCONTROL); 461 writel(1, &adap_emac->RXCONTROL); 462 463 davinci_eth_set_mac_addr(dev); 464 465 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 466 addr = &adap_emac->TX0HDP; 467 for (cnt = 0; cnt < 8; cnt++) 468 writel(0, addr++); 469 470 addr = &adap_emac->RX0HDP; 471 for (cnt = 0; cnt < 8; cnt++) 472 writel(0, addr++); 473 474 /* Clear Statistics (do this before setting MacControl register) */ 475 addr = &adap_emac->RXGOODFRAMES; 476 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 477 writel(0, addr++); 478 479 /* No multicast addressing */ 480 writel(0, &adap_emac->MACHASH1); 481 writel(0, &adap_emac->MACHASH2); 482 483 /* Create RX queue and set receive process in place */ 484 emac_rx_active_head = emac_rx_desc; 485 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 486 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); 487 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; 488 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 489 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 490 rx_desc++; 491 } 492 493 /* Finalize the rx desc list */ 494 rx_desc--; 495 rx_desc->next = 0; 496 emac_rx_active_tail = rx_desc; 497 emac_rx_queue_active = 1; 498 499 davinci_flush_rx_descs(); 500 501 /* Enable TX/RX */ 502 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 503 writel(0, &adap_emac->RXBUFFEROFFSET); 504 505 /* 506 * No fancy configs - Use this for promiscous debug 507 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 508 */ 509 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 510 511 /* Enable ch 0 only */ 512 writel(1, &adap_emac->RXUNICASTSET); 513 514 /* Enable MII interface and Full duplex mode */ 515 #if defined(CONFIG_SOC_DA8XX) || \ 516 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) 517 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 518 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 519 EMAC_MACCONTROL_RMIISPEED_100), 520 &adap_emac->MACCONTROL); 521 #else 522 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 523 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 524 &adap_emac->MACCONTROL); 525 #endif 526 527 /* Init MDIO & get link state */ 528 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 529 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 530 &adap_mdio->CONTROL); 531 532 /* We need to wait for MDIO to start */ 533 udelay(1000); 534 535 index = get_active_phy(); 536 if (index == -1) 537 return(0); 538 539 emac_gigabit_enable(active_phy_addr[index]); 540 541 /* Start receive process */ 542 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); 543 544 debug_emac("- emac_open\n"); 545 546 return(1); 547 } 548 549 /* EMAC Channel Teardown */ 550 static void davinci_eth_ch_teardown(int ch) 551 { 552 dv_reg dly = 0xff; 553 dv_reg cnt; 554 555 debug_emac("+ emac_ch_teardown\n"); 556 557 if (ch == EMAC_CH_TX) { 558 /* Init TX channel teardown */ 559 writel(0, &adap_emac->TXTEARDOWN); 560 do { 561 /* 562 * Wait here for Tx teardown completion interrupt to 563 * occur. Note: A task delay can be called here to pend 564 * rather than occupying CPU cycles - anyway it has 565 * been found that teardown takes very few cpu cycles 566 * and does not affect functionality 567 */ 568 dly--; 569 udelay(1); 570 if (dly == 0) 571 break; 572 cnt = readl(&adap_emac->TX0CP); 573 } while (cnt != 0xfffffffc); 574 writel(cnt, &adap_emac->TX0CP); 575 writel(0, &adap_emac->TX0HDP); 576 } else { 577 /* Init RX channel teardown */ 578 writel(0, &adap_emac->RXTEARDOWN); 579 do { 580 /* 581 * Wait here for Rx teardown completion interrupt to 582 * occur. Note: A task delay can be called here to pend 583 * rather than occupying CPU cycles - anyway it has 584 * been found that teardown takes very few cpu cycles 585 * and does not affect functionality 586 */ 587 dly--; 588 udelay(1); 589 if (dly == 0) 590 break; 591 cnt = readl(&adap_emac->RX0CP); 592 } while (cnt != 0xfffffffc); 593 writel(cnt, &adap_emac->RX0CP); 594 writel(0, &adap_emac->RX0HDP); 595 } 596 597 debug_emac("- emac_ch_teardown\n"); 598 } 599 600 /* Eth device close */ 601 static void davinci_eth_close(struct eth_device *dev) 602 { 603 debug_emac("+ emac_close\n"); 604 605 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 606 if (readl(&adap_emac->RXCONTROL) & 1) 607 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 608 609 /* Reset EMAC module and disable interrupts in wrapper */ 610 writel(1, &adap_emac->SOFTRESET); 611 #if defined(DAVINCI_EMAC_VERSION2) 612 writel(1, &adap_ewrap->softrst); 613 #else 614 writel(0, &adap_ewrap->EWCTL); 615 #endif 616 617 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 618 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 619 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 620 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 621 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 622 #endif 623 debug_emac("- emac_close\n"); 624 } 625 626 static int tx_send_loop = 0; 627 628 /* 629 * This function sends a single packet on the network and returns 630 * positive number (number of bytes transmitted) or negative for error 631 */ 632 static int davinci_eth_send_packet (struct eth_device *dev, 633 void *packet, int length) 634 { 635 int ret_status = -1; 636 int index; 637 tx_send_loop = 0; 638 639 index = get_active_phy(); 640 if (index == -1) { 641 printf(" WARN: emac_send_packet: No link\n"); 642 return (ret_status); 643 } 644 645 emac_gigabit_enable(active_phy_addr[index]); 646 647 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 648 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 649 length = EMAC_MIN_ETHERNET_PKT_SIZE; 650 } 651 652 /* Populate the TX descriptor */ 653 emac_tx_desc->next = 0; 654 emac_tx_desc->buffer = (u_int8_t *) packet; 655 emac_tx_desc->buff_off_len = (length & 0xffff); 656 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 657 EMAC_CPPI_SOP_BIT | 658 EMAC_CPPI_OWNERSHIP_BIT | 659 EMAC_CPPI_EOP_BIT); 660 661 flush_dcache_range((unsigned long)packet, 662 (unsigned long)packet + length); 663 davinci_flush_desc(emac_tx_desc); 664 665 /* Send the packet */ 666 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); 667 668 /* Wait for packet to complete or link down */ 669 while (1) { 670 if (!phy[index].get_link_speed(active_phy_addr[index])) { 671 davinci_eth_ch_teardown (EMAC_CH_TX); 672 return (ret_status); 673 } 674 675 emac_gigabit_enable(active_phy_addr[index]); 676 677 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 678 ret_status = length; 679 break; 680 } 681 tx_send_loop++; 682 } 683 684 return (ret_status); 685 } 686 687 /* 688 * This function handles receipt of a packet from the network 689 */ 690 static int davinci_eth_rcv_packet (struct eth_device *dev) 691 { 692 volatile emac_desc *rx_curr_desc; 693 volatile emac_desc *curr_desc; 694 volatile emac_desc *tail_desc; 695 int status, ret = -1; 696 697 davinci_invalidate_rx_descs(); 698 699 rx_curr_desc = emac_rx_active_head; 700 if (!rx_curr_desc) 701 return 0; 702 status = rx_curr_desc->pkt_flag_len; 703 if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) { 704 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 705 /* Error in packet - discard it and requeue desc */ 706 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 707 } else { 708 unsigned long tmp = (unsigned long)rx_curr_desc->buffer; 709 710 invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); 711 net_process_received_packet( 712 rx_curr_desc->buffer, 713 rx_curr_desc->buff_off_len & 0xffff); 714 ret = rx_curr_desc->buff_off_len & 0xffff; 715 } 716 717 /* Ack received packet descriptor */ 718 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); 719 curr_desc = rx_curr_desc; 720 emac_rx_active_head = 721 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); 722 723 if (status & EMAC_CPPI_EOQ_BIT) { 724 if (emac_rx_active_head) { 725 writel(BD_TO_HW((ulong)emac_rx_active_head), 726 &adap_emac->RX0HDP); 727 } else { 728 emac_rx_queue_active = 0; 729 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 730 } 731 } 732 733 /* Recycle RX descriptor */ 734 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 735 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 736 rx_curr_desc->next = 0; 737 davinci_flush_desc(rx_curr_desc); 738 739 if (emac_rx_active_head == 0) { 740 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 741 emac_rx_active_head = curr_desc; 742 emac_rx_active_tail = curr_desc; 743 if (emac_rx_queue_active != 0) { 744 writel(BD_TO_HW((ulong)emac_rx_active_head), 745 &adap_emac->RX0HDP); 746 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 747 emac_rx_queue_active = 1; 748 } 749 } else { 750 tail_desc = emac_rx_active_tail; 751 emac_rx_active_tail = curr_desc; 752 tail_desc->next = BD_TO_HW((ulong) curr_desc); 753 status = tail_desc->pkt_flag_len; 754 if (status & EMAC_CPPI_EOQ_BIT) { 755 davinci_flush_desc(tail_desc); 756 writel(BD_TO_HW((ulong)curr_desc), 757 &adap_emac->RX0HDP); 758 status &= ~EMAC_CPPI_EOQ_BIT; 759 tail_desc->pkt_flag_len = status; 760 } 761 davinci_flush_desc(tail_desc); 762 } 763 return (ret); 764 } 765 return (0); 766 } 767 768 /* 769 * This function initializes the emac hardware. It does NOT initialize 770 * EMAC modules power or pin multiplexors, that is done by board_init() 771 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 772 */ 773 int davinci_emac_initialize(void) 774 { 775 u_int32_t phy_id; 776 u_int16_t tmp; 777 int i; 778 int ret; 779 struct eth_device *dev; 780 781 dev = malloc(sizeof *dev); 782 783 if (dev == NULL) 784 return -1; 785 786 memset(dev, 0, sizeof *dev); 787 strcpy(dev->name, "DaVinci-EMAC"); 788 789 dev->iobase = 0; 790 dev->init = davinci_eth_open; 791 dev->halt = davinci_eth_close; 792 dev->send = davinci_eth_send_packet; 793 dev->recv = davinci_eth_rcv_packet; 794 dev->write_hwaddr = davinci_eth_set_mac_addr; 795 796 eth_register(dev); 797 798 davinci_eth_mdio_enable(); 799 800 /* let the EMAC detect the PHYs */ 801 udelay(5000); 802 803 for (i = 0; i < 256; i++) { 804 if (readl(&adap_mdio->ALIVE)) 805 break; 806 udelay(1000); 807 } 808 809 if (i >= 256) { 810 printf("No ETH PHY detected!!!\n"); 811 return(0); 812 } 813 814 /* Find if PHY(s) is/are connected */ 815 ret = davinci_eth_phy_detect(); 816 if (!ret) 817 return(0); 818 else 819 debug_emac(" %d ETH PHY detected\n", ret); 820 821 /* Get PHY ID and initialize phy_ops for a detected PHY */ 822 for (i = 0; i < num_phy; i++) { 823 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, 824 &tmp)) { 825 active_phy_addr[i] = 0xff; 826 continue; 827 } 828 829 phy_id = (tmp << 16) & 0xffff0000; 830 831 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, 832 &tmp)) { 833 active_phy_addr[i] = 0xff; 834 continue; 835 } 836 837 phy_id |= tmp & 0x0000ffff; 838 839 switch (phy_id) { 840 #ifdef PHY_KSZ8873 841 case PHY_KSZ8873: 842 sprintf(phy[i].name, "KSZ8873 @ 0x%02x", 843 active_phy_addr[i]); 844 phy[i].init = ksz8873_init_phy; 845 phy[i].is_phy_connected = ksz8873_is_phy_connected; 846 phy[i].get_link_speed = ksz8873_get_link_speed; 847 phy[i].auto_negotiate = ksz8873_auto_negotiate; 848 break; 849 #endif 850 #ifdef PHY_LXT972 851 case PHY_LXT972: 852 sprintf(phy[i].name, "LXT972 @ 0x%02x", 853 active_phy_addr[i]); 854 phy[i].init = lxt972_init_phy; 855 phy[i].is_phy_connected = lxt972_is_phy_connected; 856 phy[i].get_link_speed = lxt972_get_link_speed; 857 phy[i].auto_negotiate = lxt972_auto_negotiate; 858 break; 859 #endif 860 #ifdef PHY_DP83848 861 case PHY_DP83848: 862 sprintf(phy[i].name, "DP83848 @ 0x%02x", 863 active_phy_addr[i]); 864 phy[i].init = dp83848_init_phy; 865 phy[i].is_phy_connected = dp83848_is_phy_connected; 866 phy[i].get_link_speed = dp83848_get_link_speed; 867 phy[i].auto_negotiate = dp83848_auto_negotiate; 868 break; 869 #endif 870 #ifdef PHY_ET1011C 871 case PHY_ET1011C: 872 sprintf(phy[i].name, "ET1011C @ 0x%02x", 873 active_phy_addr[i]); 874 phy[i].init = gen_init_phy; 875 phy[i].is_phy_connected = gen_is_phy_connected; 876 phy[i].get_link_speed = et1011c_get_link_speed; 877 phy[i].auto_negotiate = gen_auto_negotiate; 878 break; 879 #endif 880 default: 881 sprintf(phy[i].name, "GENERIC @ 0x%02x", 882 active_phy_addr[i]); 883 phy[i].init = gen_init_phy; 884 phy[i].is_phy_connected = gen_is_phy_connected; 885 phy[i].get_link_speed = gen_get_link_speed; 886 phy[i].auto_negotiate = gen_auto_negotiate; 887 } 888 889 debug("Ethernet PHY: %s\n", phy[i].name); 890 891 int retval; 892 struct mii_dev *mdiodev = mdio_alloc(); 893 if (!mdiodev) 894 return -ENOMEM; 895 strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); 896 mdiodev->read = davinci_mii_phy_read; 897 mdiodev->write = davinci_mii_phy_write; 898 899 retval = mdio_register(mdiodev); 900 if (retval < 0) 901 return retval; 902 } 903 904 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 905 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ 906 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) 907 for (i = 0; i < num_phy; i++) { 908 if (phy[i].is_phy_connected(i)) 909 phy[i].auto_negotiate(i); 910 } 911 #endif 912 return(1); 913 } 914