1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License as published by 21 * the Free Software Foundation; either version 2 of the License, or 22 * (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 32 * ---------------------------------------------------------------------------- 33 34 * Modifications: 35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 37 * 38 */ 39 #include <common.h> 40 #include <command.h> 41 #include <net.h> 42 #include <miiphy.h> 43 #include <malloc.h> 44 #include <linux/compiler.h> 45 #include <asm/arch/emac_defs.h> 46 #include <asm/io.h> 47 #include "davinci_emac.h" 48 49 unsigned int emac_dbg = 0; 50 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 51 52 #ifdef EMAC_HW_RAM_ADDR 53 static inline unsigned long BD_TO_HW(unsigned long x) 54 { 55 if (x == 0) 56 return 0; 57 58 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; 59 } 60 61 static inline unsigned long HW_TO_BD(unsigned long x) 62 { 63 if (x == 0) 64 return 0; 65 66 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; 67 } 68 #else 69 #define BD_TO_HW(x) (x) 70 #define HW_TO_BD(x) (x) 71 #endif 72 73 #ifdef DAVINCI_EMAC_GIG_ENABLE 74 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) 75 #else 76 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ 77 #endif 78 79 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) 80 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ 81 EMAC_MDIO_CLOCK_FREQ) - 1) 82 #endif 83 84 static void davinci_eth_mdio_enable(void); 85 86 static int gen_init_phy(int phy_addr); 87 static int gen_is_phy_connected(int phy_addr); 88 static int gen_get_link_speed(int phy_addr); 89 static int gen_auto_negotiate(int phy_addr); 90 91 void eth_mdio_enable(void) 92 { 93 davinci_eth_mdio_enable(); 94 } 95 96 /* EMAC Addresses */ 97 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 98 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 99 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 100 101 /* EMAC descriptors */ 102 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 103 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 104 static volatile emac_desc *emac_rx_active_head = 0; 105 static volatile emac_desc *emac_rx_active_tail = 0; 106 static int emac_rx_queue_active = 0; 107 108 /* Receive packet buffers */ 109 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] 110 __aligned(ARCH_DMA_MINALIGN); 111 112 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 113 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 114 #endif 115 116 /* PHY address for a discovered PHY (0xff - not found) */ 117 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 118 119 /* number of PHY found active */ 120 static u_int8_t num_phy; 121 122 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; 123 124 static inline void davinci_flush_rx_descs(void) 125 { 126 /* flush the whole RX descs area */ 127 flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 128 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 129 } 130 131 static inline void davinci_invalidate_rx_descs(void) 132 { 133 /* invalidate the whole RX descs area */ 134 invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, 135 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 136 } 137 138 static inline void davinci_flush_desc(emac_desc *desc) 139 { 140 flush_dcache_range((unsigned long)desc, 141 (unsigned long)desc + sizeof(*desc)); 142 } 143 144 static int davinci_eth_set_mac_addr(struct eth_device *dev) 145 { 146 unsigned long mac_hi; 147 unsigned long mac_lo; 148 149 /* 150 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 151 * receive) 152 * Using channel 0 only - other channels are disabled 153 * */ 154 writel(0, &adap_emac->MACINDEX); 155 mac_hi = (dev->enetaddr[3] << 24) | 156 (dev->enetaddr[2] << 16) | 157 (dev->enetaddr[1] << 8) | 158 (dev->enetaddr[0]); 159 mac_lo = (dev->enetaddr[5] << 8) | 160 (dev->enetaddr[4]); 161 162 writel(mac_hi, &adap_emac->MACADDRHI); 163 #if defined(DAVINCI_EMAC_VERSION2) 164 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 165 &adap_emac->MACADDRLO); 166 #else 167 writel(mac_lo, &adap_emac->MACADDRLO); 168 #endif 169 170 writel(0, &adap_emac->MACHASH1); 171 writel(0, &adap_emac->MACHASH2); 172 173 /* Set source MAC address - REQUIRED */ 174 writel(mac_hi, &adap_emac->MACSRCADDRHI); 175 writel(mac_lo, &adap_emac->MACSRCADDRLO); 176 177 178 return 0; 179 } 180 181 static void davinci_eth_mdio_enable(void) 182 { 183 u_int32_t clkdiv; 184 185 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 186 187 writel((clkdiv & 0xff) | 188 MDIO_CONTROL_ENABLE | 189 MDIO_CONTROL_FAULT | 190 MDIO_CONTROL_FAULT_ENABLE, 191 &adap_mdio->CONTROL); 192 193 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 194 ; 195 } 196 197 /* 198 * Tries to find an active connected PHY. Returns 1 if address if found. 199 * If no active PHY (or more than one PHY) found returns 0. 200 * Sets active_phy_addr variable. 201 */ 202 static int davinci_eth_phy_detect(void) 203 { 204 u_int32_t phy_act_state; 205 int i; 206 int j; 207 unsigned int count = 0; 208 209 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) 210 active_phy_addr[i] = 0xff; 211 212 udelay(1000); 213 phy_act_state = readl(&adap_mdio->ALIVE); 214 215 if (phy_act_state == 0) 216 return 0; /* No active PHYs */ 217 218 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 219 220 for (i = 0, j = 0; i < 32; i++) 221 if (phy_act_state & (1 << i)) { 222 count++; 223 if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { 224 active_phy_addr[j++] = i; 225 } else { 226 printf("%s: to many PHYs detected.\n", 227 __func__); 228 count = 0; 229 break; 230 } 231 } 232 233 num_phy = count; 234 235 return count; 236 } 237 238 239 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 240 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 241 { 242 int tmp; 243 244 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 245 ; 246 247 writel(MDIO_USERACCESS0_GO | 248 MDIO_USERACCESS0_WRITE_READ | 249 ((reg_num & 0x1f) << 21) | 250 ((phy_addr & 0x1f) << 16), 251 &adap_mdio->USERACCESS0); 252 253 /* Wait for command to complete */ 254 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 255 ; 256 257 if (tmp & MDIO_USERACCESS0_ACK) { 258 *data = tmp & 0xffff; 259 return(1); 260 } 261 262 *data = -1; 263 return(0); 264 } 265 266 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 267 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 268 { 269 270 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 271 ; 272 273 writel(MDIO_USERACCESS0_GO | 274 MDIO_USERACCESS0_WRITE_WRITE | 275 ((reg_num & 0x1f) << 21) | 276 ((phy_addr & 0x1f) << 16) | 277 (data & 0xffff), 278 &adap_mdio->USERACCESS0); 279 280 /* Wait for command to complete */ 281 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 282 ; 283 284 return(1); 285 } 286 287 /* PHY functions for a generic PHY */ 288 static int gen_init_phy(int phy_addr) 289 { 290 int ret = 1; 291 292 if (gen_get_link_speed(phy_addr)) { 293 /* Try another time */ 294 ret = gen_get_link_speed(phy_addr); 295 } 296 297 return(ret); 298 } 299 300 static int gen_is_phy_connected(int phy_addr) 301 { 302 u_int16_t dummy; 303 304 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); 305 } 306 307 static int get_active_phy(void) 308 { 309 int i; 310 311 for (i = 0; i < num_phy; i++) 312 if (phy[i].get_link_speed(active_phy_addr[i])) 313 return i; 314 315 return -1; /* Return error if no link */ 316 } 317 318 static int gen_get_link_speed(int phy_addr) 319 { 320 u_int16_t tmp; 321 322 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && 323 (tmp & 0x04)) { 324 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 325 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 326 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); 327 328 /* Speed doesn't matter, there is no setting for it in EMAC. */ 329 if (tmp & (LPA_100FULL | LPA_10FULL)) { 330 /* set EMAC for Full Duplex */ 331 writel(EMAC_MACCONTROL_MIIEN_ENABLE | 332 EMAC_MACCONTROL_FULLDUPLEX_ENABLE, 333 &adap_emac->MACCONTROL); 334 } else { 335 /*set EMAC for Half Duplex */ 336 writel(EMAC_MACCONTROL_MIIEN_ENABLE, 337 &adap_emac->MACCONTROL); 338 } 339 340 if (tmp & (LPA_100FULL | LPA_100HALF)) 341 writel(readl(&adap_emac->MACCONTROL) | 342 EMAC_MACCONTROL_RMIISPEED_100, 343 &adap_emac->MACCONTROL); 344 else 345 writel(readl(&adap_emac->MACCONTROL) & 346 ~EMAC_MACCONTROL_RMIISPEED_100, 347 &adap_emac->MACCONTROL); 348 #endif 349 return(1); 350 } 351 352 return(0); 353 } 354 355 static int gen_auto_negotiate(int phy_addr) 356 { 357 u_int16_t tmp; 358 u_int16_t val; 359 unsigned long cntr = 0; 360 361 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 362 return 0; 363 364 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | 365 BMCR_SPEED100; 366 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 367 368 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) 369 return 0; 370 371 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | 372 ADVERTISE_10HALF); 373 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); 374 375 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 376 return(0); 377 378 /* Restart Auto_negotiation */ 379 tmp |= BMCR_ANRESTART; 380 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); 381 382 /*check AutoNegotiate complete */ 383 do { 384 udelay(40000); 385 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 386 return 0; 387 388 if (tmp & BMSR_ANEGCOMPLETE) 389 break; 390 391 cntr++; 392 } while (cntr < 200); 393 394 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) 395 return(0); 396 397 if (!(tmp & BMSR_ANEGCOMPLETE)) 398 return(0); 399 400 return(gen_get_link_speed(phy_addr)); 401 } 402 /* End of generic PHY functions */ 403 404 405 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 406 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) 407 { 408 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); 409 } 410 411 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) 412 { 413 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 414 } 415 #endif 416 417 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) 418 { 419 u_int16_t data; 420 421 if (davinci_eth_phy_read(phy_addr, 0, &data)) { 422 if (data & (1 << 6)) { /* speed selection MSB */ 423 /* 424 * Check if link detected is giga-bit 425 * If Gigabit mode detected, enable gigbit in MAC 426 */ 427 writel(readl(&adap_emac->MACCONTROL) | 428 EMAC_MACCONTROL_GIGFORCE | 429 EMAC_MACCONTROL_GIGABIT_ENABLE, 430 &adap_emac->MACCONTROL); 431 } 432 } 433 } 434 435 /* Eth device open */ 436 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 437 { 438 dv_reg_p addr; 439 u_int32_t clkdiv, cnt; 440 volatile emac_desc *rx_desc; 441 int index; 442 443 debug_emac("+ emac_open\n"); 444 445 /* Reset EMAC module and disable interrupts in wrapper */ 446 writel(1, &adap_emac->SOFTRESET); 447 while (readl(&adap_emac->SOFTRESET) != 0) 448 ; 449 #if defined(DAVINCI_EMAC_VERSION2) 450 writel(1, &adap_ewrap->softrst); 451 while (readl(&adap_ewrap->softrst) != 0) 452 ; 453 #else 454 writel(0, &adap_ewrap->EWCTL); 455 for (cnt = 0; cnt < 5; cnt++) { 456 clkdiv = readl(&adap_ewrap->EWCTL); 457 } 458 #endif 459 460 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 461 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 462 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 463 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 464 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 465 #endif 466 rx_desc = emac_rx_desc; 467 468 writel(1, &adap_emac->TXCONTROL); 469 writel(1, &adap_emac->RXCONTROL); 470 471 davinci_eth_set_mac_addr(dev); 472 473 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 474 addr = &adap_emac->TX0HDP; 475 for(cnt = 0; cnt < 16; cnt++) 476 writel(0, addr++); 477 478 addr = &adap_emac->RX0HDP; 479 for(cnt = 0; cnt < 16; cnt++) 480 writel(0, addr++); 481 482 /* Clear Statistics (do this before setting MacControl register) */ 483 addr = &adap_emac->RXGOODFRAMES; 484 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 485 writel(0, addr++); 486 487 /* No multicast addressing */ 488 writel(0, &adap_emac->MACHASH1); 489 writel(0, &adap_emac->MACHASH2); 490 491 /* Create RX queue and set receive process in place */ 492 emac_rx_active_head = emac_rx_desc; 493 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 494 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); 495 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; 496 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 497 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 498 rx_desc++; 499 } 500 501 /* Finalize the rx desc list */ 502 rx_desc--; 503 rx_desc->next = 0; 504 emac_rx_active_tail = rx_desc; 505 emac_rx_queue_active = 1; 506 507 davinci_flush_rx_descs(); 508 509 /* Enable TX/RX */ 510 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 511 writel(0, &adap_emac->RXBUFFEROFFSET); 512 513 /* 514 * No fancy configs - Use this for promiscous debug 515 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 516 */ 517 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 518 519 /* Enable ch 0 only */ 520 writel(1, &adap_emac->RXUNICASTSET); 521 522 /* Enable MII interface and Full duplex mode */ 523 #ifdef CONFIG_SOC_DA8XX 524 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 525 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 526 EMAC_MACCONTROL_RMIISPEED_100), 527 &adap_emac->MACCONTROL); 528 #else 529 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 530 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 531 &adap_emac->MACCONTROL); 532 #endif 533 534 /* Init MDIO & get link state */ 535 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; 536 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 537 &adap_mdio->CONTROL); 538 539 /* We need to wait for MDIO to start */ 540 udelay(1000); 541 542 index = get_active_phy(); 543 if (index == -1) 544 return(0); 545 546 emac_gigabit_enable(active_phy_addr[index]); 547 548 /* Start receive process */ 549 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); 550 551 debug_emac("- emac_open\n"); 552 553 return(1); 554 } 555 556 /* EMAC Channel Teardown */ 557 static void davinci_eth_ch_teardown(int ch) 558 { 559 dv_reg dly = 0xff; 560 dv_reg cnt; 561 562 debug_emac("+ emac_ch_teardown\n"); 563 564 if (ch == EMAC_CH_TX) { 565 /* Init TX channel teardown */ 566 writel(0, &adap_emac->TXTEARDOWN); 567 do { 568 /* 569 * Wait here for Tx teardown completion interrupt to 570 * occur. Note: A task delay can be called here to pend 571 * rather than occupying CPU cycles - anyway it has 572 * been found that teardown takes very few cpu cycles 573 * and does not affect functionality 574 */ 575 dly--; 576 udelay(1); 577 if (dly == 0) 578 break; 579 cnt = readl(&adap_emac->TX0CP); 580 } while (cnt != 0xfffffffc); 581 writel(cnt, &adap_emac->TX0CP); 582 writel(0, &adap_emac->TX0HDP); 583 } else { 584 /* Init RX channel teardown */ 585 writel(0, &adap_emac->RXTEARDOWN); 586 do { 587 /* 588 * Wait here for Rx teardown completion interrupt to 589 * occur. Note: A task delay can be called here to pend 590 * rather than occupying CPU cycles - anyway it has 591 * been found that teardown takes very few cpu cycles 592 * and does not affect functionality 593 */ 594 dly--; 595 udelay(1); 596 if (dly == 0) 597 break; 598 cnt = readl(&adap_emac->RX0CP); 599 } while (cnt != 0xfffffffc); 600 writel(cnt, &adap_emac->RX0CP); 601 writel(0, &adap_emac->RX0HDP); 602 } 603 604 debug_emac("- emac_ch_teardown\n"); 605 } 606 607 /* Eth device close */ 608 static void davinci_eth_close(struct eth_device *dev) 609 { 610 debug_emac("+ emac_close\n"); 611 612 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 613 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 614 615 /* Reset EMAC module and disable interrupts in wrapper */ 616 writel(1, &adap_emac->SOFTRESET); 617 #if defined(DAVINCI_EMAC_VERSION2) 618 writel(1, &adap_ewrap->softrst); 619 #else 620 writel(0, &adap_ewrap->EWCTL); 621 #endif 622 623 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ 624 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 625 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; 626 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; 627 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; 628 #endif 629 debug_emac("- emac_close\n"); 630 } 631 632 static int tx_send_loop = 0; 633 634 /* 635 * This function sends a single packet on the network and returns 636 * positive number (number of bytes transmitted) or negative for error 637 */ 638 static int davinci_eth_send_packet (struct eth_device *dev, 639 volatile void *packet, int length) 640 { 641 int ret_status = -1; 642 int index; 643 tx_send_loop = 0; 644 645 index = get_active_phy(); 646 if (index == -1) { 647 printf(" WARN: emac_send_packet: No link\n"); 648 return (ret_status); 649 } 650 651 emac_gigabit_enable(active_phy_addr[index]); 652 653 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 654 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 655 length = EMAC_MIN_ETHERNET_PKT_SIZE; 656 } 657 658 /* Populate the TX descriptor */ 659 emac_tx_desc->next = 0; 660 emac_tx_desc->buffer = (u_int8_t *) packet; 661 emac_tx_desc->buff_off_len = (length & 0xffff); 662 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 663 EMAC_CPPI_SOP_BIT | 664 EMAC_CPPI_OWNERSHIP_BIT | 665 EMAC_CPPI_EOP_BIT); 666 667 flush_dcache_range((unsigned long)packet, 668 (unsigned long)packet + length); 669 davinci_flush_desc(emac_tx_desc); 670 671 /* Send the packet */ 672 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); 673 674 /* Wait for packet to complete or link down */ 675 while (1) { 676 if (!phy[index].get_link_speed(active_phy_addr[index])) { 677 davinci_eth_ch_teardown (EMAC_CH_TX); 678 return (ret_status); 679 } 680 681 emac_gigabit_enable(active_phy_addr[index]); 682 683 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 684 ret_status = length; 685 break; 686 } 687 tx_send_loop++; 688 } 689 690 return (ret_status); 691 } 692 693 /* 694 * This function handles receipt of a packet from the network 695 */ 696 static int davinci_eth_rcv_packet (struct eth_device *dev) 697 { 698 volatile emac_desc *rx_curr_desc; 699 volatile emac_desc *curr_desc; 700 volatile emac_desc *tail_desc; 701 int status, ret = -1; 702 703 davinci_invalidate_rx_descs(); 704 705 rx_curr_desc = emac_rx_active_head; 706 status = rx_curr_desc->pkt_flag_len; 707 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { 708 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 709 /* Error in packet - discard it and requeue desc */ 710 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 711 } else { 712 unsigned long tmp = (unsigned long)rx_curr_desc->buffer; 713 714 invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); 715 NetReceive (rx_curr_desc->buffer, 716 (rx_curr_desc->buff_off_len & 0xffff)); 717 ret = rx_curr_desc->buff_off_len & 0xffff; 718 } 719 720 /* Ack received packet descriptor */ 721 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); 722 curr_desc = rx_curr_desc; 723 emac_rx_active_head = 724 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); 725 726 if (status & EMAC_CPPI_EOQ_BIT) { 727 if (emac_rx_active_head) { 728 writel(BD_TO_HW((ulong)emac_rx_active_head), 729 &adap_emac->RX0HDP); 730 } else { 731 emac_rx_queue_active = 0; 732 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 733 } 734 } 735 736 /* Recycle RX descriptor */ 737 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 738 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 739 rx_curr_desc->next = 0; 740 davinci_flush_desc(rx_curr_desc); 741 742 if (emac_rx_active_head == 0) { 743 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 744 emac_rx_active_head = curr_desc; 745 emac_rx_active_tail = curr_desc; 746 if (emac_rx_queue_active != 0) { 747 writel(BD_TO_HW((ulong)emac_rx_active_head), 748 &adap_emac->RX0HDP); 749 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 750 emac_rx_queue_active = 1; 751 } 752 } else { 753 tail_desc = emac_rx_active_tail; 754 emac_rx_active_tail = curr_desc; 755 tail_desc->next = BD_TO_HW((ulong) curr_desc); 756 status = tail_desc->pkt_flag_len; 757 if (status & EMAC_CPPI_EOQ_BIT) { 758 davinci_flush_desc(tail_desc); 759 writel(BD_TO_HW((ulong)curr_desc), 760 &adap_emac->RX0HDP); 761 status &= ~EMAC_CPPI_EOQ_BIT; 762 tail_desc->pkt_flag_len = status; 763 } 764 davinci_flush_desc(tail_desc); 765 } 766 return (ret); 767 } 768 return (0); 769 } 770 771 /* 772 * This function initializes the emac hardware. It does NOT initialize 773 * EMAC modules power or pin multiplexors, that is done by board_init() 774 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 775 */ 776 int davinci_emac_initialize(void) 777 { 778 u_int32_t phy_id; 779 u_int16_t tmp; 780 int i; 781 int ret; 782 struct eth_device *dev; 783 784 dev = malloc(sizeof *dev); 785 786 if (dev == NULL) 787 return -1; 788 789 memset(dev, 0, sizeof *dev); 790 sprintf(dev->name, "DaVinci-EMAC"); 791 792 dev->iobase = 0; 793 dev->init = davinci_eth_open; 794 dev->halt = davinci_eth_close; 795 dev->send = davinci_eth_send_packet; 796 dev->recv = davinci_eth_rcv_packet; 797 dev->write_hwaddr = davinci_eth_set_mac_addr; 798 799 eth_register(dev); 800 801 davinci_eth_mdio_enable(); 802 803 /* let the EMAC detect the PHYs */ 804 udelay(5000); 805 806 for (i = 0; i < 256; i++) { 807 if (readl(&adap_mdio->ALIVE)) 808 break; 809 udelay(1000); 810 } 811 812 if (i >= 256) { 813 printf("No ETH PHY detected!!!\n"); 814 return(0); 815 } 816 817 /* Find if PHY(s) is/are connected */ 818 ret = davinci_eth_phy_detect(); 819 if (!ret) 820 return(0); 821 else 822 debug_emac(" %d ETH PHY detected\n", ret); 823 824 /* Get PHY ID and initialize phy_ops for a detected PHY */ 825 for (i = 0; i < num_phy; i++) { 826 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, 827 &tmp)) { 828 active_phy_addr[i] = 0xff; 829 continue; 830 } 831 832 phy_id = (tmp << 16) & 0xffff0000; 833 834 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, 835 &tmp)) { 836 active_phy_addr[i] = 0xff; 837 continue; 838 } 839 840 phy_id |= tmp & 0x0000ffff; 841 842 switch (phy_id) { 843 #ifdef PHY_KSZ8873 844 case PHY_KSZ8873: 845 sprintf(phy[i].name, "KSZ8873 @ 0x%02x", 846 active_phy_addr[i]); 847 phy[i].init = ksz8873_init_phy; 848 phy[i].is_phy_connected = ksz8873_is_phy_connected; 849 phy[i].get_link_speed = ksz8873_get_link_speed; 850 phy[i].auto_negotiate = ksz8873_auto_negotiate; 851 break; 852 #endif 853 #ifdef PHY_LXT972 854 case PHY_LXT972: 855 sprintf(phy[i].name, "LXT972 @ 0x%02x", 856 active_phy_addr[i]); 857 phy[i].init = lxt972_init_phy; 858 phy[i].is_phy_connected = lxt972_is_phy_connected; 859 phy[i].get_link_speed = lxt972_get_link_speed; 860 phy[i].auto_negotiate = lxt972_auto_negotiate; 861 break; 862 #endif 863 #ifdef PHY_DP83848 864 case PHY_DP83848: 865 sprintf(phy[i].name, "DP83848 @ 0x%02x", 866 active_phy_addr[i]); 867 phy[i].init = dp83848_init_phy; 868 phy[i].is_phy_connected = dp83848_is_phy_connected; 869 phy[i].get_link_speed = dp83848_get_link_speed; 870 phy[i].auto_negotiate = dp83848_auto_negotiate; 871 break; 872 #endif 873 #ifdef PHY_ET1011C 874 case PHY_ET1011C: 875 sprintf(phy[i].name, "ET1011C @ 0x%02x", 876 active_phy_addr[i]); 877 phy[i].init = gen_init_phy; 878 phy[i].is_phy_connected = gen_is_phy_connected; 879 phy[i].get_link_speed = et1011c_get_link_speed; 880 phy[i].auto_negotiate = gen_auto_negotiate; 881 break; 882 #endif 883 default: 884 sprintf(phy[i].name, "GENERIC @ 0x%02x", 885 active_phy_addr[i]); 886 phy[i].init = gen_init_phy; 887 phy[i].is_phy_connected = gen_is_phy_connected; 888 phy[i].get_link_speed = gen_get_link_speed; 889 phy[i].auto_negotiate = gen_auto_negotiate; 890 } 891 892 debug("Ethernet PHY: %s\n", phy[i].name); 893 894 miiphy_register(phy[i].name, davinci_mii_phy_read, 895 davinci_mii_phy_write); 896 } 897 return(1); 898 } 899