1 /* 2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright 7 * follows: 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * dm644x_emac.c 12 * 13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM 14 * 15 * Copyright (C) 2005 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License as published by 21 * the Free Software Foundation; either version 2 of the License, or 22 * (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 32 * ---------------------------------------------------------------------------- 33 34 * Modifications: 35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. 36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors 37 * 38 */ 39 #include <common.h> 40 #include <command.h> 41 #include <net.h> 42 #include <miiphy.h> 43 #include <malloc.h> 44 #include <asm/arch/emac_defs.h> 45 #include <asm/io.h> 46 47 unsigned int emac_dbg = 0; 48 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) 49 50 #ifdef DAVINCI_EMAC_GIG_ENABLE 51 #define emac_gigabit_enable() davinci_eth_gigabit_enable() 52 #else 53 #define emac_gigabit_enable() /* no gigabit to enable */ 54 #endif 55 56 static void davinci_eth_mdio_enable(void); 57 58 static int gen_init_phy(int phy_addr); 59 static int gen_is_phy_connected(int phy_addr); 60 static int gen_get_link_speed(int phy_addr); 61 static int gen_auto_negotiate(int phy_addr); 62 63 void eth_mdio_enable(void) 64 { 65 davinci_eth_mdio_enable(); 66 } 67 68 /* EMAC Addresses */ 69 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; 70 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; 71 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; 72 73 /* EMAC descriptors */ 74 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); 75 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); 76 static volatile emac_desc *emac_rx_active_head = 0; 77 static volatile emac_desc *emac_rx_active_tail = 0; 78 static int emac_rx_queue_active = 0; 79 80 /* Receive packet buffers */ 81 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 82 83 /* PHY address for a discovered PHY (0xff - not found) */ 84 static volatile u_int8_t active_phy_addr = 0xff; 85 86 phy_t phy; 87 88 static int davinci_eth_set_mac_addr(struct eth_device *dev) 89 { 90 unsigned long mac_hi; 91 unsigned long mac_lo; 92 93 /* 94 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast 95 * receive) 96 * Using channel 0 only - other channels are disabled 97 * */ 98 writel(0, &adap_emac->MACINDEX); 99 mac_hi = (dev->enetaddr[3] << 24) | 100 (dev->enetaddr[2] << 16) | 101 (dev->enetaddr[1] << 8) | 102 (dev->enetaddr[0]); 103 mac_lo = (dev->enetaddr[5] << 8) | 104 (dev->enetaddr[4]); 105 106 writel(mac_hi, &adap_emac->MACADDRHI); 107 #if defined(DAVINCI_EMAC_VERSION2) 108 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, 109 &adap_emac->MACADDRLO); 110 #else 111 writel(mac_lo, &adap_emac->MACADDRLO); 112 #endif 113 114 writel(0, &adap_emac->MACHASH1); 115 writel(0, &adap_emac->MACHASH2); 116 117 /* Set source MAC address - REQUIRED */ 118 writel(mac_hi, &adap_emac->MACSRCADDRHI); 119 writel(mac_lo, &adap_emac->MACSRCADDRLO); 120 121 122 return 0; 123 } 124 125 static void davinci_eth_mdio_enable(void) 126 { 127 u_int32_t clkdiv; 128 129 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 130 131 writel((clkdiv & 0xff) | 132 MDIO_CONTROL_ENABLE | 133 MDIO_CONTROL_FAULT | 134 MDIO_CONTROL_FAULT_ENABLE, 135 &adap_mdio->CONTROL); 136 137 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) 138 ; 139 } 140 141 /* 142 * Tries to find an active connected PHY. Returns 1 if address if found. 143 * If no active PHY (or more than one PHY) found returns 0. 144 * Sets active_phy_addr variable. 145 */ 146 static int davinci_eth_phy_detect(void) 147 { 148 u_int32_t phy_act_state; 149 int i; 150 151 active_phy_addr = 0xff; 152 153 phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK; 154 if (phy_act_state == 0) 155 return(0); /* No active PHYs */ 156 157 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); 158 159 for (i = 0; i < 32; i++) { 160 if (phy_act_state & (1 << i)) { 161 if (phy_act_state & ~(1 << i)) 162 return(0); /* More than one PHY */ 163 else { 164 active_phy_addr = i; 165 return(1); 166 } 167 } 168 } 169 170 return(0); /* Just to make GCC happy */ 171 } 172 173 174 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ 175 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) 176 { 177 int tmp; 178 179 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 180 ; 181 182 writel(MDIO_USERACCESS0_GO | 183 MDIO_USERACCESS0_WRITE_READ | 184 ((reg_num & 0x1f) << 21) | 185 ((phy_addr & 0x1f) << 16), 186 &adap_mdio->USERACCESS0); 187 188 /* Wait for command to complete */ 189 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) 190 ; 191 192 if (tmp & MDIO_USERACCESS0_ACK) { 193 *data = tmp & 0xffff; 194 return(1); 195 } 196 197 *data = -1; 198 return(0); 199 } 200 201 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ 202 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) 203 { 204 205 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 206 ; 207 208 writel(MDIO_USERACCESS0_GO | 209 MDIO_USERACCESS0_WRITE_WRITE | 210 ((reg_num & 0x1f) << 21) | 211 ((phy_addr & 0x1f) << 16) | 212 (data & 0xffff), 213 &adap_mdio->USERACCESS0); 214 215 /* Wait for command to complete */ 216 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) 217 ; 218 219 return(1); 220 } 221 222 /* PHY functions for a generic PHY */ 223 static int gen_init_phy(int phy_addr) 224 { 225 int ret = 1; 226 227 if (gen_get_link_speed(phy_addr)) { 228 /* Try another time */ 229 ret = gen_get_link_speed(phy_addr); 230 } 231 232 return(ret); 233 } 234 235 static int gen_is_phy_connected(int phy_addr) 236 { 237 u_int16_t dummy; 238 239 return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); 240 } 241 242 static int gen_get_link_speed(int phy_addr) 243 { 244 u_int16_t tmp; 245 246 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) 247 return(1); 248 249 return(0); 250 } 251 252 static int gen_auto_negotiate(int phy_addr) 253 { 254 u_int16_t tmp; 255 256 if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) 257 return(0); 258 259 /* Restart Auto_negotiation */ 260 tmp |= PHY_BMCR_AUTON; 261 davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp); 262 263 /*check AutoNegotiate complete */ 264 udelay (10000); 265 if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) 266 return(0); 267 268 if (!(tmp & PHY_BMSR_AUTN_COMP)) 269 return(0); 270 271 return(gen_get_link_speed(phy_addr)); 272 } 273 /* End of generic PHY functions */ 274 275 276 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 277 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) 278 { 279 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); 280 } 281 282 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) 283 { 284 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); 285 } 286 #endif 287 288 static void __attribute__((unused)) davinci_eth_gigabit_enable(void) 289 { 290 u_int16_t data; 291 292 if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) { 293 if (data & (1 << 6)) { /* speed selection MSB */ 294 /* 295 * Check if link detected is giga-bit 296 * If Gigabit mode detected, enable gigbit in MAC 297 */ 298 writel(EMAC_MACCONTROL_GIGFORCE | 299 EMAC_MACCONTROL_GIGABIT_ENABLE, 300 &adap_emac->MACCONTROL); 301 } 302 } 303 } 304 305 /* Eth device open */ 306 static int davinci_eth_open(struct eth_device *dev, bd_t *bis) 307 { 308 dv_reg_p addr; 309 u_int32_t clkdiv, cnt; 310 volatile emac_desc *rx_desc; 311 312 debug_emac("+ emac_open\n"); 313 314 /* Reset EMAC module and disable interrupts in wrapper */ 315 writel(1, &adap_emac->SOFTRESET); 316 while (readl(&adap_emac->SOFTRESET) != 0) 317 ; 318 #if defined(DAVINCI_EMAC_VERSION2) 319 writel(1, &adap_ewrap->softrst); 320 while (readl(&adap_ewrap->softrst) != 0) 321 ; 322 #else 323 writel(0, &adap_ewrap->EWCTL); 324 for (cnt = 0; cnt < 5; cnt++) { 325 clkdiv = readl(&adap_ewrap->EWCTL); 326 } 327 #endif 328 329 rx_desc = emac_rx_desc; 330 331 writel(1, &adap_emac->TXCONTROL); 332 writel(1, &adap_emac->RXCONTROL); 333 334 davinci_eth_set_mac_addr(dev); 335 336 /* Set DMA 8 TX / 8 RX Head pointers to 0 */ 337 addr = &adap_emac->TX0HDP; 338 for(cnt = 0; cnt < 16; cnt++) 339 writel(0, addr++); 340 341 addr = &adap_emac->RX0HDP; 342 for(cnt = 0; cnt < 16; cnt++) 343 writel(0, addr++); 344 345 /* Clear Statistics (do this before setting MacControl register) */ 346 addr = &adap_emac->RXGOODFRAMES; 347 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) 348 writel(0, addr++); 349 350 /* No multicast addressing */ 351 writel(0, &adap_emac->MACHASH1); 352 writel(0, &adap_emac->MACHASH2); 353 354 /* Create RX queue and set receive process in place */ 355 emac_rx_active_head = emac_rx_desc; 356 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { 357 rx_desc->next = (u_int32_t)(rx_desc + 1); 358 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; 359 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 360 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 361 rx_desc++; 362 } 363 364 /* Finalize the rx desc list */ 365 rx_desc--; 366 rx_desc->next = 0; 367 emac_rx_active_tail = rx_desc; 368 emac_rx_queue_active = 1; 369 370 /* Enable TX/RX */ 371 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); 372 writel(0, &adap_emac->RXBUFFEROFFSET); 373 374 /* 375 * No fancy configs - Use this for promiscous debug 376 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE 377 */ 378 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); 379 380 /* Enable ch 0 only */ 381 writel(1, &adap_emac->RXUNICASTSET); 382 383 /* Enable MII interface and Full duplex mode */ 384 #ifdef CONFIG_SOC_DA8XX 385 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 386 EMAC_MACCONTROL_FULLDUPLEX_ENABLE | 387 EMAC_MACCONTROL_RMIISPEED_100), 388 &adap_emac->MACCONTROL); 389 #else 390 writel((EMAC_MACCONTROL_MIIEN_ENABLE | 391 EMAC_MACCONTROL_FULLDUPLEX_ENABLE), 392 &adap_emac->MACCONTROL); 393 #endif 394 395 /* Init MDIO & get link state */ 396 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; 397 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, 398 &adap_mdio->CONTROL); 399 400 /* We need to wait for MDIO to start */ 401 udelay(1000); 402 403 if (!phy.get_link_speed(active_phy_addr)) 404 return(0); 405 406 emac_gigabit_enable(); 407 408 /* Start receive process */ 409 writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); 410 411 debug_emac("- emac_open\n"); 412 413 return(1); 414 } 415 416 /* EMAC Channel Teardown */ 417 static void davinci_eth_ch_teardown(int ch) 418 { 419 dv_reg dly = 0xff; 420 dv_reg cnt; 421 422 debug_emac("+ emac_ch_teardown\n"); 423 424 if (ch == EMAC_CH_TX) { 425 /* Init TX channel teardown */ 426 writel(1, &adap_emac->TXTEARDOWN); 427 do { 428 /* 429 * Wait here for Tx teardown completion interrupt to 430 * occur. Note: A task delay can be called here to pend 431 * rather than occupying CPU cycles - anyway it has 432 * been found that teardown takes very few cpu cycles 433 * and does not affect functionality 434 */ 435 dly--; 436 udelay(1); 437 if (dly == 0) 438 break; 439 cnt = readl(&adap_emac->TX0CP); 440 } while (cnt != 0xfffffffc); 441 writel(cnt, &adap_emac->TX0CP); 442 writel(0, &adap_emac->TX0HDP); 443 } else { 444 /* Init RX channel teardown */ 445 writel(1, &adap_emac->RXTEARDOWN); 446 do { 447 /* 448 * Wait here for Rx teardown completion interrupt to 449 * occur. Note: A task delay can be called here to pend 450 * rather than occupying CPU cycles - anyway it has 451 * been found that teardown takes very few cpu cycles 452 * and does not affect functionality 453 */ 454 dly--; 455 udelay(1); 456 if (dly == 0) 457 break; 458 cnt = readl(&adap_emac->RX0CP); 459 } while (cnt != 0xfffffffc); 460 writel(cnt, &adap_emac->RX0CP); 461 writel(0, &adap_emac->RX0HDP); 462 } 463 464 debug_emac("- emac_ch_teardown\n"); 465 } 466 467 /* Eth device close */ 468 static void davinci_eth_close(struct eth_device *dev) 469 { 470 debug_emac("+ emac_close\n"); 471 472 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ 473 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ 474 475 /* Reset EMAC module and disable interrupts in wrapper */ 476 writel(1, &adap_emac->SOFTRESET); 477 #if defined(DAVINCI_EMAC_VERSION2) 478 writel(1, &adap_ewrap->softrst); 479 #else 480 writel(0, &adap_ewrap->EWCTL); 481 #endif 482 483 debug_emac("- emac_close\n"); 484 } 485 486 static int tx_send_loop = 0; 487 488 /* 489 * This function sends a single packet on the network and returns 490 * positive number (number of bytes transmitted) or negative for error 491 */ 492 static int davinci_eth_send_packet (struct eth_device *dev, 493 volatile void *packet, int length) 494 { 495 int ret_status = -1; 496 497 tx_send_loop = 0; 498 499 /* Return error if no link */ 500 if (!phy.get_link_speed (active_phy_addr)) { 501 printf ("WARN: emac_send_packet: No link\n"); 502 return (ret_status); 503 } 504 505 emac_gigabit_enable(); 506 507 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ 508 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { 509 length = EMAC_MIN_ETHERNET_PKT_SIZE; 510 } 511 512 /* Populate the TX descriptor */ 513 emac_tx_desc->next = 0; 514 emac_tx_desc->buffer = (u_int8_t *) packet; 515 emac_tx_desc->buff_off_len = (length & 0xffff); 516 emac_tx_desc->pkt_flag_len = ((length & 0xffff) | 517 EMAC_CPPI_SOP_BIT | 518 EMAC_CPPI_OWNERSHIP_BIT | 519 EMAC_CPPI_EOP_BIT); 520 /* Send the packet */ 521 writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); 522 523 /* Wait for packet to complete or link down */ 524 while (1) { 525 if (!phy.get_link_speed (active_phy_addr)) { 526 davinci_eth_ch_teardown (EMAC_CH_TX); 527 return (ret_status); 528 } 529 530 emac_gigabit_enable(); 531 532 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { 533 ret_status = length; 534 break; 535 } 536 tx_send_loop++; 537 } 538 539 return (ret_status); 540 } 541 542 /* 543 * This function handles receipt of a packet from the network 544 */ 545 static int davinci_eth_rcv_packet (struct eth_device *dev) 546 { 547 volatile emac_desc *rx_curr_desc; 548 volatile emac_desc *curr_desc; 549 volatile emac_desc *tail_desc; 550 int status, ret = -1; 551 552 rx_curr_desc = emac_rx_active_head; 553 status = rx_curr_desc->pkt_flag_len; 554 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { 555 if (status & EMAC_CPPI_RX_ERROR_FRAME) { 556 /* Error in packet - discard it and requeue desc */ 557 printf ("WARN: emac_rcv_pkt: Error in packet\n"); 558 } else { 559 NetReceive (rx_curr_desc->buffer, 560 (rx_curr_desc->buff_off_len & 0xffff)); 561 ret = rx_curr_desc->buff_off_len & 0xffff; 562 } 563 564 /* Ack received packet descriptor */ 565 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); 566 curr_desc = rx_curr_desc; 567 emac_rx_active_head = 568 (volatile emac_desc *) rx_curr_desc->next; 569 570 if (status & EMAC_CPPI_EOQ_BIT) { 571 if (emac_rx_active_head) { 572 writel((unsigned long)emac_rx_active_head, 573 &adap_emac->RX0HDP); 574 } else { 575 emac_rx_queue_active = 0; 576 printf ("INFO:emac_rcv_packet: RX Queue not active\n"); 577 } 578 } 579 580 /* Recycle RX descriptor */ 581 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; 582 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; 583 rx_curr_desc->next = 0; 584 585 if (emac_rx_active_head == 0) { 586 printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); 587 emac_rx_active_head = curr_desc; 588 emac_rx_active_tail = curr_desc; 589 if (emac_rx_queue_active != 0) { 590 writel((unsigned long)emac_rx_active_head, 591 &adap_emac->RX0HDP); 592 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); 593 emac_rx_queue_active = 1; 594 } 595 } else { 596 tail_desc = emac_rx_active_tail; 597 emac_rx_active_tail = curr_desc; 598 tail_desc->next = (unsigned int) curr_desc; 599 status = tail_desc->pkt_flag_len; 600 if (status & EMAC_CPPI_EOQ_BIT) { 601 writel((unsigned long)curr_desc, 602 &adap_emac->RX0HDP); 603 status &= ~EMAC_CPPI_EOQ_BIT; 604 tail_desc->pkt_flag_len = status; 605 } 606 } 607 return (ret); 608 } 609 return (0); 610 } 611 612 /* 613 * This function initializes the emac hardware. It does NOT initialize 614 * EMAC modules power or pin multiplexors, that is done by board_init() 615 * much earlier in bootup process. Returns 1 on success, 0 otherwise. 616 */ 617 int davinci_emac_initialize(void) 618 { 619 u_int32_t phy_id; 620 u_int16_t tmp; 621 int i; 622 struct eth_device *dev; 623 624 dev = malloc(sizeof *dev); 625 626 if (dev == NULL) 627 return -1; 628 629 memset(dev, 0, sizeof *dev); 630 631 dev->iobase = 0; 632 dev->init = davinci_eth_open; 633 dev->halt = davinci_eth_close; 634 dev->send = davinci_eth_send_packet; 635 dev->recv = davinci_eth_rcv_packet; 636 dev->write_hwaddr = davinci_eth_set_mac_addr; 637 638 eth_register(dev); 639 640 davinci_eth_mdio_enable(); 641 642 for (i = 0; i < 256; i++) { 643 if (readl(&adap_mdio->ALIVE)) 644 break; 645 udelay(10); 646 } 647 648 if (i >= 256) { 649 printf("No ETH PHY detected!!!\n"); 650 return(0); 651 } 652 653 /* Find if a PHY is connected and get it's address */ 654 if (!davinci_eth_phy_detect()) 655 return(0); 656 657 /* Get PHY ID and initialize phy_ops for a detected PHY */ 658 if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { 659 active_phy_addr = 0xff; 660 return(0); 661 } 662 663 phy_id = (tmp << 16) & 0xffff0000; 664 665 if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { 666 active_phy_addr = 0xff; 667 return(0); 668 } 669 670 phy_id |= tmp & 0x0000ffff; 671 672 switch (phy_id) { 673 case PHY_LXT972: 674 sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); 675 phy.init = lxt972_init_phy; 676 phy.is_phy_connected = lxt972_is_phy_connected; 677 phy.get_link_speed = lxt972_get_link_speed; 678 phy.auto_negotiate = lxt972_auto_negotiate; 679 break; 680 case PHY_DP83848: 681 sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); 682 phy.init = dp83848_init_phy; 683 phy.is_phy_connected = dp83848_is_phy_connected; 684 phy.get_link_speed = dp83848_get_link_speed; 685 phy.auto_negotiate = dp83848_auto_negotiate; 686 break; 687 default: 688 sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); 689 phy.init = gen_init_phy; 690 phy.is_phy_connected = gen_is_phy_connected; 691 phy.get_link_speed = gen_get_link_speed; 692 phy.auto_negotiate = gen_auto_negotiate; 693 } 694 695 printf("Ethernet PHY: %s\n", phy.name); 696 697 miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); 698 return(1); 699 } 700