1 /* 2 * CPSW Ethernet Switch Driver 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <command.h> 18 #include <net.h> 19 #include <miiphy.h> 20 #include <malloc.h> 21 #include <net.h> 22 #include <netdev.h> 23 #include <cpsw.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <phy.h> 27 #include <asm/arch/cpu.h> 28 29 #define BITMASK(bits) (BIT(bits) - 1) 30 #define PHY_REG_MASK 0x1f 31 #define PHY_ID_MASK 0x1f 32 #define NUM_DESCS (PKTBUFSRX * 2) 33 #define PKT_MIN 60 34 #define PKT_MAX (1500 + 14 + 4 + 4) 35 #define CLEAR_BIT 1 36 #define GIGABITEN BIT(7) 37 #define FULLDUPLEXEN BIT(0) 38 #define MIIEN BIT(15) 39 40 /* DMA Registers */ 41 #define CPDMA_TXCONTROL 0x004 42 #define CPDMA_RXCONTROL 0x014 43 #define CPDMA_SOFTRESET 0x01c 44 #define CPDMA_RXFREE 0x0e0 45 #define CPDMA_TXHDP_VER1 0x100 46 #define CPDMA_TXHDP_VER2 0x200 47 #define CPDMA_RXHDP_VER1 0x120 48 #define CPDMA_RXHDP_VER2 0x220 49 #define CPDMA_TXCP_VER1 0x140 50 #define CPDMA_TXCP_VER2 0x240 51 #define CPDMA_RXCP_VER1 0x160 52 #define CPDMA_RXCP_VER2 0x260 53 54 #define CPDMA_RAM_ADDR 0x4a102000 55 56 /* Descriptor mode bits */ 57 #define CPDMA_DESC_SOP BIT(31) 58 #define CPDMA_DESC_EOP BIT(30) 59 #define CPDMA_DESC_OWNER BIT(29) 60 #define CPDMA_DESC_EOQ BIT(28) 61 62 /* 63 * This timeout definition is a worst-case ultra defensive measure against 64 * unexpected controller lock ups. Ideally, we should never ever hit this 65 * scenario in practice. 66 */ 67 #define MDIO_TIMEOUT 100 /* msecs */ 68 #define CPDMA_TIMEOUT 100 /* msecs */ 69 70 struct cpsw_mdio_regs { 71 u32 version; 72 u32 control; 73 #define CONTROL_IDLE BIT(31) 74 #define CONTROL_ENABLE BIT(30) 75 76 u32 alive; 77 u32 link; 78 u32 linkintraw; 79 u32 linkintmasked; 80 u32 __reserved_0[2]; 81 u32 userintraw; 82 u32 userintmasked; 83 u32 userintmaskset; 84 u32 userintmaskclr; 85 u32 __reserved_1[20]; 86 87 struct { 88 u32 access; 89 u32 physel; 90 #define USERACCESS_GO BIT(31) 91 #define USERACCESS_WRITE BIT(30) 92 #define USERACCESS_ACK BIT(29) 93 #define USERACCESS_READ (0) 94 #define USERACCESS_DATA (0xffff) 95 } user[0]; 96 }; 97 98 struct cpsw_regs { 99 u32 id_ver; 100 u32 control; 101 u32 soft_reset; 102 u32 stat_port_en; 103 u32 ptype; 104 }; 105 106 struct cpsw_slave_regs { 107 u32 max_blks; 108 u32 blk_cnt; 109 u32 flow_thresh; 110 u32 port_vlan; 111 u32 tx_pri_map; 112 #ifdef CONFIG_AM33XX 113 u32 gap_thresh; 114 #elif defined(CONFIG_TI814X) 115 u32 ts_ctl; 116 u32 ts_seq_ltype; 117 u32 ts_vlan; 118 #endif 119 u32 sa_lo; 120 u32 sa_hi; 121 }; 122 123 struct cpsw_host_regs { 124 u32 max_blks; 125 u32 blk_cnt; 126 u32 flow_thresh; 127 u32 port_vlan; 128 u32 tx_pri_map; 129 u32 cpdma_tx_pri_map; 130 u32 cpdma_rx_chan_map; 131 }; 132 133 struct cpsw_sliver_regs { 134 u32 id_ver; 135 u32 mac_control; 136 u32 mac_status; 137 u32 soft_reset; 138 u32 rx_maxlen; 139 u32 __reserved_0; 140 u32 rx_pause; 141 u32 tx_pause; 142 u32 __reserved_1; 143 u32 rx_pri_map; 144 }; 145 146 #define ALE_ENTRY_BITS 68 147 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) 148 149 /* ALE Registers */ 150 #define ALE_CONTROL 0x08 151 #define ALE_UNKNOWNVLAN 0x18 152 #define ALE_TABLE_CONTROL 0x20 153 #define ALE_TABLE 0x34 154 #define ALE_PORTCTL 0x40 155 156 #define ALE_TABLE_WRITE BIT(31) 157 158 #define ALE_TYPE_FREE 0 159 #define ALE_TYPE_ADDR 1 160 #define ALE_TYPE_VLAN 2 161 #define ALE_TYPE_VLAN_ADDR 3 162 163 #define ALE_UCAST_PERSISTANT 0 164 #define ALE_UCAST_UNTOUCHED 1 165 #define ALE_UCAST_OUI 2 166 #define ALE_UCAST_TOUCHED 3 167 168 #define ALE_MCAST_FWD 0 169 #define ALE_MCAST_BLOCK_LEARN_FWD 1 170 #define ALE_MCAST_FWD_LEARN 2 171 #define ALE_MCAST_FWD_2 3 172 173 enum cpsw_ale_port_state { 174 ALE_PORT_STATE_DISABLE = 0x00, 175 ALE_PORT_STATE_BLOCK = 0x01, 176 ALE_PORT_STATE_LEARN = 0x02, 177 ALE_PORT_STATE_FORWARD = 0x03, 178 }; 179 180 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ 181 #define ALE_SECURE 1 182 #define ALE_BLOCKED 2 183 184 struct cpsw_slave { 185 struct cpsw_slave_regs *regs; 186 struct cpsw_sliver_regs *sliver; 187 int slave_num; 188 u32 mac_control; 189 struct cpsw_slave_data *data; 190 }; 191 192 struct cpdma_desc { 193 /* hardware fields */ 194 u32 hw_next; 195 u32 hw_buffer; 196 u32 hw_len; 197 u32 hw_mode; 198 /* software fields */ 199 u32 sw_buffer; 200 u32 sw_len; 201 }; 202 203 struct cpdma_chan { 204 struct cpdma_desc *head, *tail; 205 void *hdp, *cp, *rxfree; 206 }; 207 208 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) 209 #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 210 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) 211 212 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) 213 #define chan_read(chan, fld) __raw_readl((chan)->fld) 214 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) 215 216 #define for_each_slave(slave, priv) \ 217 for (slave = (priv)->slaves; slave != (priv)->slaves + \ 218 (priv)->data.slaves; slave++) 219 220 struct cpsw_priv { 221 struct eth_device *dev; 222 struct cpsw_platform_data data; 223 int host_port; 224 225 struct cpsw_regs *regs; 226 void *dma_regs; 227 struct cpsw_host_regs *host_port_regs; 228 void *ale_regs; 229 230 struct cpdma_desc *descs; 231 struct cpdma_desc *desc_free; 232 struct cpdma_chan rx_chan, tx_chan; 233 234 struct cpsw_slave *slaves; 235 struct phy_device *phydev; 236 struct mii_dev *bus; 237 238 u32 mdio_link; 239 u32 phy_mask; 240 }; 241 242 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 243 { 244 int idx; 245 246 idx = start / 32; 247 start -= idx * 32; 248 idx = 2 - idx; /* flip */ 249 return (ale_entry[idx] >> start) & BITMASK(bits); 250 } 251 252 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 253 u32 value) 254 { 255 int idx; 256 257 value &= BITMASK(bits); 258 idx = start / 32; 259 start -= idx * 32; 260 idx = 2 - idx; /* flip */ 261 ale_entry[idx] &= ~(BITMASK(bits) << start); 262 ale_entry[idx] |= (value << start); 263 } 264 265 #define DEFINE_ALE_FIELD(name, start, bits) \ 266 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 267 { \ 268 return cpsw_ale_get_field(ale_entry, start, bits); \ 269 } \ 270 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 271 { \ 272 cpsw_ale_set_field(ale_entry, start, bits, value); \ 273 } 274 275 DEFINE_ALE_FIELD(entry_type, 60, 2) 276 DEFINE_ALE_FIELD(mcast_state, 62, 2) 277 DEFINE_ALE_FIELD(port_mask, 66, 3) 278 DEFINE_ALE_FIELD(ucast_type, 62, 2) 279 DEFINE_ALE_FIELD(port_num, 66, 2) 280 DEFINE_ALE_FIELD(blocked, 65, 1) 281 DEFINE_ALE_FIELD(secure, 64, 1) 282 DEFINE_ALE_FIELD(mcast, 40, 1) 283 284 /* The MAC address field in the ALE entry cannot be macroized as above */ 285 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 286 { 287 int i; 288 289 for (i = 0; i < 6; i++) 290 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 291 } 292 293 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr) 294 { 295 int i; 296 297 for (i = 0; i < 6; i++) 298 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 299 } 300 301 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) 302 { 303 int i; 304 305 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); 306 307 for (i = 0; i < ALE_ENTRY_WORDS; i++) 308 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); 309 310 return idx; 311 } 312 313 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) 314 { 315 int i; 316 317 for (i = 0; i < ALE_ENTRY_WORDS; i++) 318 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); 319 320 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); 321 322 return idx; 323 } 324 325 static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr) 326 { 327 u32 ale_entry[ALE_ENTRY_WORDS]; 328 int type, idx; 329 330 for (idx = 0; idx < priv->data.ale_entries; idx++) { 331 u8 entry_addr[6]; 332 333 cpsw_ale_read(priv, idx, ale_entry); 334 type = cpsw_ale_get_entry_type(ale_entry); 335 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 336 continue; 337 cpsw_ale_get_addr(ale_entry, entry_addr); 338 if (memcmp(entry_addr, addr, 6) == 0) 339 return idx; 340 } 341 return -ENOENT; 342 } 343 344 static int cpsw_ale_match_free(struct cpsw_priv *priv) 345 { 346 u32 ale_entry[ALE_ENTRY_WORDS]; 347 int type, idx; 348 349 for (idx = 0; idx < priv->data.ale_entries; idx++) { 350 cpsw_ale_read(priv, idx, ale_entry); 351 type = cpsw_ale_get_entry_type(ale_entry); 352 if (type == ALE_TYPE_FREE) 353 return idx; 354 } 355 return -ENOENT; 356 } 357 358 static int cpsw_ale_find_ageable(struct cpsw_priv *priv) 359 { 360 u32 ale_entry[ALE_ENTRY_WORDS]; 361 int type, idx; 362 363 for (idx = 0; idx < priv->data.ale_entries; idx++) { 364 cpsw_ale_read(priv, idx, ale_entry); 365 type = cpsw_ale_get_entry_type(ale_entry); 366 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 367 continue; 368 if (cpsw_ale_get_mcast(ale_entry)) 369 continue; 370 type = cpsw_ale_get_ucast_type(ale_entry); 371 if (type != ALE_UCAST_PERSISTANT && 372 type != ALE_UCAST_OUI) 373 return idx; 374 } 375 return -ENOENT; 376 } 377 378 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr, 379 int port, int flags) 380 { 381 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 382 int idx; 383 384 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 385 cpsw_ale_set_addr(ale_entry, addr); 386 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 387 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 388 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 389 cpsw_ale_set_port_num(ale_entry, port); 390 391 idx = cpsw_ale_match_addr(priv, addr); 392 if (idx < 0) 393 idx = cpsw_ale_match_free(priv); 394 if (idx < 0) 395 idx = cpsw_ale_find_ageable(priv); 396 if (idx < 0) 397 return -ENOMEM; 398 399 cpsw_ale_write(priv, idx, ale_entry); 400 return 0; 401 } 402 403 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask) 404 { 405 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 406 int idx, mask; 407 408 idx = cpsw_ale_match_addr(priv, addr); 409 if (idx >= 0) 410 cpsw_ale_read(priv, idx, ale_entry); 411 412 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 413 cpsw_ale_set_addr(ale_entry, addr); 414 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); 415 416 mask = cpsw_ale_get_port_mask(ale_entry); 417 port_mask |= mask; 418 cpsw_ale_set_port_mask(ale_entry, port_mask); 419 420 if (idx < 0) 421 idx = cpsw_ale_match_free(priv); 422 if (idx < 0) 423 idx = cpsw_ale_find_ageable(priv); 424 if (idx < 0) 425 return -ENOMEM; 426 427 cpsw_ale_write(priv, idx, ale_entry); 428 return 0; 429 } 430 431 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) 432 { 433 u32 tmp, mask = BIT(bit); 434 435 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); 436 tmp &= ~mask; 437 tmp |= val ? mask : 0; 438 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); 439 } 440 441 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) 442 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) 443 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) 444 445 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, 446 int val) 447 { 448 int offset = ALE_PORTCTL + 4 * port; 449 u32 tmp, mask = 0x3; 450 451 tmp = __raw_readl(priv->ale_regs + offset); 452 tmp &= ~mask; 453 tmp |= val & mask; 454 __raw_writel(tmp, priv->ale_regs + offset); 455 } 456 457 static struct cpsw_mdio_regs *mdio_regs; 458 459 /* wait until hardware is ready for another user access */ 460 static inline u32 wait_for_user_access(void) 461 { 462 u32 reg = 0; 463 int timeout = MDIO_TIMEOUT; 464 465 while (timeout-- && 466 ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) 467 udelay(10); 468 469 if (timeout == -1) { 470 printf("wait_for_user_access Timeout\n"); 471 return -ETIMEDOUT; 472 } 473 return reg; 474 } 475 476 /* wait until hardware state machine is idle */ 477 static inline void wait_for_idle(void) 478 { 479 int timeout = MDIO_TIMEOUT; 480 481 while (timeout-- && 482 ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) 483 udelay(10); 484 485 if (timeout == -1) 486 printf("wait_for_idle Timeout\n"); 487 } 488 489 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, 490 int dev_addr, int phy_reg) 491 { 492 unsigned short data; 493 u32 reg; 494 495 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 496 return -EINVAL; 497 498 wait_for_user_access(); 499 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | 500 (phy_id << 16)); 501 __raw_writel(reg, &mdio_regs->user[0].access); 502 reg = wait_for_user_access(); 503 504 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; 505 return data; 506 } 507 508 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, 509 int phy_reg, u16 data) 510 { 511 u32 reg; 512 513 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 514 return -EINVAL; 515 516 wait_for_user_access(); 517 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | 518 (phy_id << 16) | (data & USERACCESS_DATA)); 519 __raw_writel(reg, &mdio_regs->user[0].access); 520 wait_for_user_access(); 521 522 return 0; 523 } 524 525 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div) 526 { 527 struct mii_dev *bus = mdio_alloc(); 528 529 mdio_regs = (struct cpsw_mdio_regs *)mdio_base; 530 531 /* set enable and clock divider */ 532 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); 533 534 /* 535 * wait for scan logic to settle: 536 * the scan time consists of (a) a large fixed component, and (b) a 537 * small component that varies with the mii bus frequency. These 538 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x 539 * silicon. Since the effect of (b) was found to be largely 540 * negligible, we keep things simple here. 541 */ 542 udelay(1000); 543 544 bus->read = cpsw_mdio_read; 545 bus->write = cpsw_mdio_write; 546 sprintf(bus->name, name); 547 548 mdio_register(bus); 549 } 550 551 /* Set a self-clearing bit in a register, and wait for it to clear */ 552 static inline void setbit_and_wait_for_clear32(void *addr) 553 { 554 __raw_writel(CLEAR_BIT, addr); 555 while (__raw_readl(addr) & CLEAR_BIT) 556 ; 557 } 558 559 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 560 ((mac)[2] << 16) | ((mac)[3] << 24)) 561 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 562 563 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 564 struct cpsw_priv *priv) 565 { 566 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); 567 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); 568 } 569 570 static void cpsw_slave_update_link(struct cpsw_slave *slave, 571 struct cpsw_priv *priv, int *link) 572 { 573 struct phy_device *phy = priv->phydev; 574 u32 mac_control = 0; 575 576 phy_startup(phy); 577 *link = phy->link; 578 579 if (*link) { /* link up */ 580 mac_control = priv->data.mac_control; 581 if (phy->speed == 1000) 582 mac_control |= GIGABITEN; 583 if (phy->duplex == DUPLEX_FULL) 584 mac_control |= FULLDUPLEXEN; 585 if (phy->speed == 100) 586 mac_control |= MIIEN; 587 } 588 589 if (mac_control == slave->mac_control) 590 return; 591 592 if (mac_control) { 593 printf("link up on port %d, speed %d, %s duplex\n", 594 slave->slave_num, phy->speed, 595 (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 596 } else { 597 printf("link down on port %d\n", slave->slave_num); 598 } 599 600 __raw_writel(mac_control, &slave->sliver->mac_control); 601 slave->mac_control = mac_control; 602 } 603 604 static int cpsw_update_link(struct cpsw_priv *priv) 605 { 606 int link = 0; 607 struct cpsw_slave *slave; 608 609 for_each_slave(slave, priv) 610 cpsw_slave_update_link(slave, priv, &link); 611 priv->mdio_link = readl(&mdio_regs->link); 612 return link; 613 } 614 615 static int cpsw_check_link(struct cpsw_priv *priv) 616 { 617 u32 link = 0; 618 619 link = __raw_readl(&mdio_regs->link) & priv->phy_mask; 620 if ((link) && (link == priv->mdio_link)) 621 return 1; 622 623 return cpsw_update_link(priv); 624 } 625 626 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 627 { 628 if (priv->host_port == 0) 629 return slave_num + 1; 630 else 631 return slave_num; 632 } 633 634 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 635 { 636 u32 slave_port; 637 638 setbit_and_wait_for_clear32(&slave->sliver->soft_reset); 639 640 /* setup priority mapping */ 641 __raw_writel(0x76543210, &slave->sliver->rx_pri_map); 642 __raw_writel(0x33221100, &slave->regs->tx_pri_map); 643 644 /* setup max packet size, and mac address */ 645 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); 646 cpsw_set_slave_mac(slave, priv); 647 648 slave->mac_control = 0; /* no link yet */ 649 650 /* enable forwarding */ 651 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 652 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); 653 654 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); 655 656 priv->phy_mask |= 1 << slave->data->phy_id; 657 } 658 659 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) 660 { 661 struct cpdma_desc *desc = priv->desc_free; 662 663 if (desc) 664 priv->desc_free = desc_read_ptr(desc, hw_next); 665 return desc; 666 } 667 668 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) 669 { 670 if (desc) { 671 desc_write(desc, hw_next, priv->desc_free); 672 priv->desc_free = desc; 673 } 674 } 675 676 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, 677 void *buffer, int len) 678 { 679 struct cpdma_desc *desc, *prev; 680 u32 mode; 681 682 desc = cpdma_desc_alloc(priv); 683 if (!desc) 684 return -ENOMEM; 685 686 if (len < PKT_MIN) 687 len = PKT_MIN; 688 689 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 690 691 desc_write(desc, hw_next, 0); 692 desc_write(desc, hw_buffer, buffer); 693 desc_write(desc, hw_len, len); 694 desc_write(desc, hw_mode, mode | len); 695 desc_write(desc, sw_buffer, buffer); 696 desc_write(desc, sw_len, len); 697 698 if (!chan->head) { 699 /* simple case - first packet enqueued */ 700 chan->head = desc; 701 chan->tail = desc; 702 chan_write(chan, hdp, desc); 703 goto done; 704 } 705 706 /* not the first packet - enqueue at the tail */ 707 prev = chan->tail; 708 desc_write(prev, hw_next, desc); 709 chan->tail = desc; 710 711 /* next check if EOQ has been triggered already */ 712 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) 713 chan_write(chan, hdp, desc); 714 715 done: 716 if (chan->rxfree) 717 chan_write(chan, rxfree, 1); 718 return 0; 719 } 720 721 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, 722 void **buffer, int *len) 723 { 724 struct cpdma_desc *desc = chan->head; 725 u32 status; 726 727 if (!desc) 728 return -ENOENT; 729 730 status = desc_read(desc, hw_mode); 731 732 if (len) 733 *len = status & 0x7ff; 734 735 if (buffer) 736 *buffer = desc_read_ptr(desc, sw_buffer); 737 738 if (status & CPDMA_DESC_OWNER) { 739 if (chan_read(chan, hdp) == 0) { 740 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) 741 chan_write(chan, hdp, desc); 742 } 743 744 return -EBUSY; 745 } 746 747 chan->head = desc_read_ptr(desc, hw_next); 748 chan_write(chan, cp, desc); 749 750 cpdma_desc_free(priv, desc); 751 return 0; 752 } 753 754 static int cpsw_init(struct eth_device *dev, bd_t *bis) 755 { 756 struct cpsw_priv *priv = dev->priv; 757 struct cpsw_slave *slave; 758 int i, ret; 759 760 /* soft reset the controller and initialize priv */ 761 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 762 763 /* initialize and reset the address lookup engine */ 764 cpsw_ale_enable(priv, 1); 765 cpsw_ale_clear(priv, 1); 766 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ 767 768 /* setup host port priority mapping */ 769 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); 770 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 771 772 /* disable priority elevation and enable statistics on all ports */ 773 __raw_writel(0, &priv->regs->ptype); 774 775 /* enable statistics collection only on the host port */ 776 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); 777 778 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); 779 780 cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port, 781 ALE_SECURE); 782 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port); 783 784 for_each_slave(slave, priv) 785 cpsw_slave_init(slave, priv); 786 787 cpsw_update_link(priv); 788 789 /* init descriptor pool */ 790 for (i = 0; i < NUM_DESCS; i++) { 791 desc_write(&priv->descs[i], hw_next, 792 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); 793 } 794 priv->desc_free = &priv->descs[0]; 795 796 /* initialize channels */ 797 if (priv->data.version == CPSW_CTRL_VERSION_2) { 798 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 799 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; 800 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; 801 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 802 803 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 804 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; 805 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; 806 } else { 807 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 808 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; 809 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; 810 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 811 812 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 813 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; 814 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; 815 } 816 817 /* clear dma state */ 818 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 819 820 if (priv->data.version == CPSW_CTRL_VERSION_2) { 821 for (i = 0; i < priv->data.channels; i++) { 822 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 823 * i); 824 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 825 * i); 826 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 827 * i); 828 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 829 * i); 830 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 831 * i); 832 } 833 } else { 834 for (i = 0; i < priv->data.channels; i++) { 835 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 836 * i); 837 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 838 * i); 839 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 840 * i); 841 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 842 * i); 843 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 844 * i); 845 846 } 847 } 848 849 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); 850 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); 851 852 /* submit rx descs */ 853 for (i = 0; i < PKTBUFSRX; i++) { 854 ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i], 855 PKTSIZE); 856 if (ret < 0) { 857 printf("error %d submitting rx desc\n", ret); 858 break; 859 } 860 } 861 862 return 0; 863 } 864 865 static void cpsw_halt(struct eth_device *dev) 866 { 867 struct cpsw_priv *priv = dev->priv; 868 869 writel(0, priv->dma_regs + CPDMA_TXCONTROL); 870 writel(0, priv->dma_regs + CPDMA_RXCONTROL); 871 872 /* soft reset the controller and initialize priv */ 873 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 874 875 /* clear dma state */ 876 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 877 878 priv->data.control(0); 879 } 880 881 static int cpsw_send(struct eth_device *dev, void *packet, int length) 882 { 883 struct cpsw_priv *priv = dev->priv; 884 void *buffer; 885 int len; 886 int timeout = CPDMA_TIMEOUT; 887 888 if (!cpsw_check_link(priv)) 889 return -EIO; 890 891 flush_dcache_range((unsigned long)packet, 892 (unsigned long)packet + length); 893 894 /* first reap completed packets */ 895 while (timeout-- && 896 (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)) 897 ; 898 899 if (timeout == -1) { 900 printf("cpdma_process timeout\n"); 901 return -ETIMEDOUT; 902 } 903 904 return cpdma_submit(priv, &priv->tx_chan, packet, length); 905 } 906 907 static int cpsw_recv(struct eth_device *dev) 908 { 909 struct cpsw_priv *priv = dev->priv; 910 void *buffer; 911 int len; 912 913 cpsw_update_link(priv); 914 915 while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { 916 invalidate_dcache_range((unsigned long)buffer, 917 (unsigned long)buffer + PKTSIZE_ALIGN); 918 NetReceive(buffer, len); 919 cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE); 920 } 921 922 return 0; 923 } 924 925 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, 926 struct cpsw_priv *priv) 927 { 928 void *regs = priv->regs; 929 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 930 slave->slave_num = slave_num; 931 slave->data = data; 932 slave->regs = regs + data->slave_reg_ofs; 933 slave->sliver = regs + data->sliver_reg_ofs; 934 } 935 936 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) 937 { 938 struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv; 939 struct phy_device *phydev; 940 u32 supported = (SUPPORTED_10baseT_Half | 941 SUPPORTED_10baseT_Full | 942 SUPPORTED_100baseT_Half | 943 SUPPORTED_100baseT_Full | 944 SUPPORTED_1000baseT_Full); 945 946 phydev = phy_connect(priv->bus, 947 CONFIG_PHY_ADDR, 948 dev, 949 slave->data->phy_if); 950 951 phydev->supported &= supported; 952 phydev->advertising = phydev->supported; 953 954 priv->phydev = phydev; 955 phy_config(phydev); 956 957 return 1; 958 } 959 960 int cpsw_register(struct cpsw_platform_data *data) 961 { 962 struct cpsw_priv *priv; 963 struct cpsw_slave *slave; 964 void *regs = (void *)data->cpsw_base; 965 struct eth_device *dev; 966 967 dev = calloc(sizeof(*dev), 1); 968 if (!dev) 969 return -ENOMEM; 970 971 priv = calloc(sizeof(*priv), 1); 972 if (!priv) { 973 free(dev); 974 return -ENOMEM; 975 } 976 977 priv->data = *data; 978 priv->dev = dev; 979 980 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); 981 if (!priv->slaves) { 982 free(dev); 983 free(priv); 984 return -ENOMEM; 985 } 986 987 priv->descs = (void *)CPDMA_RAM_ADDR; 988 priv->host_port = data->host_port_num; 989 priv->regs = regs; 990 priv->host_port_regs = regs + data->host_port_reg_ofs; 991 priv->dma_regs = regs + data->cpdma_reg_ofs; 992 priv->ale_regs = regs + data->ale_reg_ofs; 993 994 int idx = 0; 995 996 for_each_slave(slave, priv) { 997 cpsw_slave_setup(slave, idx, priv); 998 idx = idx + 1; 999 } 1000 1001 strcpy(dev->name, "cpsw"); 1002 dev->iobase = 0; 1003 dev->init = cpsw_init; 1004 dev->halt = cpsw_halt; 1005 dev->send = cpsw_send; 1006 dev->recv = cpsw_recv; 1007 dev->priv = priv; 1008 1009 eth_register(dev); 1010 1011 cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div); 1012 priv->bus = miiphy_get_dev_by_name(dev->name); 1013 for_each_slave(slave, priv) 1014 cpsw_phy_init(dev, slave); 1015 1016 return 1; 1017 } 1018