1 /* 2 * CPSW Ethernet Switch Driver 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <command.h> 18 #include <net.h> 19 #include <miiphy.h> 20 #include <malloc.h> 21 #include <net.h> 22 #include <netdev.h> 23 #include <cpsw.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <phy.h> 27 28 #define BITMASK(bits) (BIT(bits) - 1) 29 #define PHY_REG_MASK 0x1f 30 #define PHY_ID_MASK 0x1f 31 #define NUM_DESCS (PKTBUFSRX * 2) 32 #define PKT_MIN 60 33 #define PKT_MAX (1500 + 14 + 4 + 4) 34 #define CLEAR_BIT 1 35 #define GIGABITEN BIT(7) 36 #define FULLDUPLEXEN BIT(0) 37 #define MIIEN BIT(15) 38 39 /* DMA Registers */ 40 #define CPDMA_TXCONTROL 0x004 41 #define CPDMA_RXCONTROL 0x014 42 #define CPDMA_SOFTRESET 0x01c 43 #define CPDMA_RXFREE 0x0e0 44 #define CPDMA_TXHDP_VER1 0x100 45 #define CPDMA_TXHDP_VER2 0x200 46 #define CPDMA_RXHDP_VER1 0x120 47 #define CPDMA_RXHDP_VER2 0x220 48 #define CPDMA_TXCP_VER1 0x140 49 #define CPDMA_TXCP_VER2 0x240 50 #define CPDMA_RXCP_VER1 0x160 51 #define CPDMA_RXCP_VER2 0x260 52 53 #define CPDMA_RAM_ADDR 0x4a102000 54 55 /* Descriptor mode bits */ 56 #define CPDMA_DESC_SOP BIT(31) 57 #define CPDMA_DESC_EOP BIT(30) 58 #define CPDMA_DESC_OWNER BIT(29) 59 #define CPDMA_DESC_EOQ BIT(28) 60 61 /* 62 * This timeout definition is a worst-case ultra defensive measure against 63 * unexpected controller lock ups. Ideally, we should never ever hit this 64 * scenario in practice. 65 */ 66 #define MDIO_TIMEOUT 100 /* msecs */ 67 #define CPDMA_TIMEOUT 100 /* msecs */ 68 69 struct cpsw_mdio_regs { 70 u32 version; 71 u32 control; 72 #define CONTROL_IDLE BIT(31) 73 #define CONTROL_ENABLE BIT(30) 74 75 u32 alive; 76 u32 link; 77 u32 linkintraw; 78 u32 linkintmasked; 79 u32 __reserved_0[2]; 80 u32 userintraw; 81 u32 userintmasked; 82 u32 userintmaskset; 83 u32 userintmaskclr; 84 u32 __reserved_1[20]; 85 86 struct { 87 u32 access; 88 u32 physel; 89 #define USERACCESS_GO BIT(31) 90 #define USERACCESS_WRITE BIT(30) 91 #define USERACCESS_ACK BIT(29) 92 #define USERACCESS_READ (0) 93 #define USERACCESS_DATA (0xffff) 94 } user[0]; 95 }; 96 97 struct cpsw_regs { 98 u32 id_ver; 99 u32 control; 100 u32 soft_reset; 101 u32 stat_port_en; 102 u32 ptype; 103 }; 104 105 struct cpsw_slave_regs { 106 u32 max_blks; 107 u32 blk_cnt; 108 u32 flow_thresh; 109 u32 port_vlan; 110 u32 tx_pri_map; 111 u32 gap_thresh; 112 u32 sa_lo; 113 u32 sa_hi; 114 }; 115 116 struct cpsw_host_regs { 117 u32 max_blks; 118 u32 blk_cnt; 119 u32 flow_thresh; 120 u32 port_vlan; 121 u32 tx_pri_map; 122 u32 cpdma_tx_pri_map; 123 u32 cpdma_rx_chan_map; 124 }; 125 126 struct cpsw_sliver_regs { 127 u32 id_ver; 128 u32 mac_control; 129 u32 mac_status; 130 u32 soft_reset; 131 u32 rx_maxlen; 132 u32 __reserved_0; 133 u32 rx_pause; 134 u32 tx_pause; 135 u32 __reserved_1; 136 u32 rx_pri_map; 137 }; 138 139 #define ALE_ENTRY_BITS 68 140 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) 141 142 /* ALE Registers */ 143 #define ALE_CONTROL 0x08 144 #define ALE_UNKNOWNVLAN 0x18 145 #define ALE_TABLE_CONTROL 0x20 146 #define ALE_TABLE 0x34 147 #define ALE_PORTCTL 0x40 148 149 #define ALE_TABLE_WRITE BIT(31) 150 151 #define ALE_TYPE_FREE 0 152 #define ALE_TYPE_ADDR 1 153 #define ALE_TYPE_VLAN 2 154 #define ALE_TYPE_VLAN_ADDR 3 155 156 #define ALE_UCAST_PERSISTANT 0 157 #define ALE_UCAST_UNTOUCHED 1 158 #define ALE_UCAST_OUI 2 159 #define ALE_UCAST_TOUCHED 3 160 161 #define ALE_MCAST_FWD 0 162 #define ALE_MCAST_BLOCK_LEARN_FWD 1 163 #define ALE_MCAST_FWD_LEARN 2 164 #define ALE_MCAST_FWD_2 3 165 166 enum cpsw_ale_port_state { 167 ALE_PORT_STATE_DISABLE = 0x00, 168 ALE_PORT_STATE_BLOCK = 0x01, 169 ALE_PORT_STATE_LEARN = 0x02, 170 ALE_PORT_STATE_FORWARD = 0x03, 171 }; 172 173 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ 174 #define ALE_SECURE 1 175 #define ALE_BLOCKED 2 176 177 struct cpsw_slave { 178 struct cpsw_slave_regs *regs; 179 struct cpsw_sliver_regs *sliver; 180 int slave_num; 181 u32 mac_control; 182 struct cpsw_slave_data *data; 183 }; 184 185 struct cpdma_desc { 186 /* hardware fields */ 187 u32 hw_next; 188 u32 hw_buffer; 189 u32 hw_len; 190 u32 hw_mode; 191 /* software fields */ 192 u32 sw_buffer; 193 u32 sw_len; 194 }; 195 196 struct cpdma_chan { 197 struct cpdma_desc *head, *tail; 198 void *hdp, *cp, *rxfree; 199 }; 200 201 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) 202 #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 203 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) 204 205 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) 206 #define chan_read(chan, fld) __raw_readl((chan)->fld) 207 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) 208 209 #define for_each_slave(slave, priv) \ 210 for (slave = (priv)->slaves; slave != (priv)->slaves + \ 211 (priv)->data.slaves; slave++) 212 213 struct cpsw_priv { 214 struct eth_device *dev; 215 struct cpsw_platform_data data; 216 int host_port; 217 218 struct cpsw_regs *regs; 219 void *dma_regs; 220 struct cpsw_host_regs *host_port_regs; 221 void *ale_regs; 222 223 struct cpdma_desc *descs; 224 struct cpdma_desc *desc_free; 225 struct cpdma_chan rx_chan, tx_chan; 226 227 struct cpsw_slave *slaves; 228 struct phy_device *phydev; 229 struct mii_dev *bus; 230 231 u32 mdio_link; 232 u32 phy_mask; 233 }; 234 235 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 236 { 237 int idx; 238 239 idx = start / 32; 240 start -= idx * 32; 241 idx = 2 - idx; /* flip */ 242 return (ale_entry[idx] >> start) & BITMASK(bits); 243 } 244 245 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 246 u32 value) 247 { 248 int idx; 249 250 value &= BITMASK(bits); 251 idx = start / 32; 252 start -= idx * 32; 253 idx = 2 - idx; /* flip */ 254 ale_entry[idx] &= ~(BITMASK(bits) << start); 255 ale_entry[idx] |= (value << start); 256 } 257 258 #define DEFINE_ALE_FIELD(name, start, bits) \ 259 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 260 { \ 261 return cpsw_ale_get_field(ale_entry, start, bits); \ 262 } \ 263 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 264 { \ 265 cpsw_ale_set_field(ale_entry, start, bits, value); \ 266 } 267 268 DEFINE_ALE_FIELD(entry_type, 60, 2) 269 DEFINE_ALE_FIELD(mcast_state, 62, 2) 270 DEFINE_ALE_FIELD(port_mask, 66, 3) 271 DEFINE_ALE_FIELD(ucast_type, 62, 2) 272 DEFINE_ALE_FIELD(port_num, 66, 2) 273 DEFINE_ALE_FIELD(blocked, 65, 1) 274 DEFINE_ALE_FIELD(secure, 64, 1) 275 DEFINE_ALE_FIELD(mcast, 40, 1) 276 277 /* The MAC address field in the ALE entry cannot be macroized as above */ 278 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 279 { 280 int i; 281 282 for (i = 0; i < 6; i++) 283 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 284 } 285 286 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr) 287 { 288 int i; 289 290 for (i = 0; i < 6; i++) 291 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 292 } 293 294 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) 295 { 296 int i; 297 298 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); 299 300 for (i = 0; i < ALE_ENTRY_WORDS; i++) 301 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); 302 303 return idx; 304 } 305 306 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) 307 { 308 int i; 309 310 for (i = 0; i < ALE_ENTRY_WORDS; i++) 311 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); 312 313 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); 314 315 return idx; 316 } 317 318 static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr) 319 { 320 u32 ale_entry[ALE_ENTRY_WORDS]; 321 int type, idx; 322 323 for (idx = 0; idx < priv->data.ale_entries; idx++) { 324 u8 entry_addr[6]; 325 326 cpsw_ale_read(priv, idx, ale_entry); 327 type = cpsw_ale_get_entry_type(ale_entry); 328 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 329 continue; 330 cpsw_ale_get_addr(ale_entry, entry_addr); 331 if (memcmp(entry_addr, addr, 6) == 0) 332 return idx; 333 } 334 return -ENOENT; 335 } 336 337 static int cpsw_ale_match_free(struct cpsw_priv *priv) 338 { 339 u32 ale_entry[ALE_ENTRY_WORDS]; 340 int type, idx; 341 342 for (idx = 0; idx < priv->data.ale_entries; idx++) { 343 cpsw_ale_read(priv, idx, ale_entry); 344 type = cpsw_ale_get_entry_type(ale_entry); 345 if (type == ALE_TYPE_FREE) 346 return idx; 347 } 348 return -ENOENT; 349 } 350 351 static int cpsw_ale_find_ageable(struct cpsw_priv *priv) 352 { 353 u32 ale_entry[ALE_ENTRY_WORDS]; 354 int type, idx; 355 356 for (idx = 0; idx < priv->data.ale_entries; idx++) { 357 cpsw_ale_read(priv, idx, ale_entry); 358 type = cpsw_ale_get_entry_type(ale_entry); 359 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 360 continue; 361 if (cpsw_ale_get_mcast(ale_entry)) 362 continue; 363 type = cpsw_ale_get_ucast_type(ale_entry); 364 if (type != ALE_UCAST_PERSISTANT && 365 type != ALE_UCAST_OUI) 366 return idx; 367 } 368 return -ENOENT; 369 } 370 371 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr, 372 int port, int flags) 373 { 374 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 375 int idx; 376 377 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 378 cpsw_ale_set_addr(ale_entry, addr); 379 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 380 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 381 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 382 cpsw_ale_set_port_num(ale_entry, port); 383 384 idx = cpsw_ale_match_addr(priv, addr); 385 if (idx < 0) 386 idx = cpsw_ale_match_free(priv); 387 if (idx < 0) 388 idx = cpsw_ale_find_ageable(priv); 389 if (idx < 0) 390 return -ENOMEM; 391 392 cpsw_ale_write(priv, idx, ale_entry); 393 return 0; 394 } 395 396 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask) 397 { 398 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 399 int idx, mask; 400 401 idx = cpsw_ale_match_addr(priv, addr); 402 if (idx >= 0) 403 cpsw_ale_read(priv, idx, ale_entry); 404 405 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 406 cpsw_ale_set_addr(ale_entry, addr); 407 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); 408 409 mask = cpsw_ale_get_port_mask(ale_entry); 410 port_mask |= mask; 411 cpsw_ale_set_port_mask(ale_entry, port_mask); 412 413 if (idx < 0) 414 idx = cpsw_ale_match_free(priv); 415 if (idx < 0) 416 idx = cpsw_ale_find_ageable(priv); 417 if (idx < 0) 418 return -ENOMEM; 419 420 cpsw_ale_write(priv, idx, ale_entry); 421 return 0; 422 } 423 424 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) 425 { 426 u32 tmp, mask = BIT(bit); 427 428 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); 429 tmp &= ~mask; 430 tmp |= val ? mask : 0; 431 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); 432 } 433 434 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) 435 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) 436 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) 437 438 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, 439 int val) 440 { 441 int offset = ALE_PORTCTL + 4 * port; 442 u32 tmp, mask = 0x3; 443 444 tmp = __raw_readl(priv->ale_regs + offset); 445 tmp &= ~mask; 446 tmp |= val & mask; 447 __raw_writel(tmp, priv->ale_regs + offset); 448 } 449 450 static struct cpsw_mdio_regs *mdio_regs; 451 452 /* wait until hardware is ready for another user access */ 453 static inline u32 wait_for_user_access(void) 454 { 455 u32 reg = 0; 456 int timeout = MDIO_TIMEOUT; 457 458 while (timeout-- && 459 ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) 460 udelay(10); 461 462 if (timeout == -1) { 463 printf("wait_for_user_access Timeout\n"); 464 return -ETIMEDOUT; 465 } 466 return reg; 467 } 468 469 /* wait until hardware state machine is idle */ 470 static inline void wait_for_idle(void) 471 { 472 int timeout = MDIO_TIMEOUT; 473 474 while (timeout-- && 475 ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) 476 udelay(10); 477 478 if (timeout == -1) 479 printf("wait_for_idle Timeout\n"); 480 } 481 482 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, 483 int dev_addr, int phy_reg) 484 { 485 unsigned short data; 486 u32 reg; 487 488 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 489 return -EINVAL; 490 491 wait_for_user_access(); 492 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | 493 (phy_id << 16)); 494 __raw_writel(reg, &mdio_regs->user[0].access); 495 reg = wait_for_user_access(); 496 497 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; 498 return data; 499 } 500 501 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, 502 int phy_reg, u16 data) 503 { 504 u32 reg; 505 506 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 507 return -EINVAL; 508 509 wait_for_user_access(); 510 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | 511 (phy_id << 16) | (data & USERACCESS_DATA)); 512 __raw_writel(reg, &mdio_regs->user[0].access); 513 wait_for_user_access(); 514 515 return 0; 516 } 517 518 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div) 519 { 520 struct mii_dev *bus = mdio_alloc(); 521 522 mdio_regs = (struct cpsw_mdio_regs *)mdio_base; 523 524 /* set enable and clock divider */ 525 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); 526 527 /* 528 * wait for scan logic to settle: 529 * the scan time consists of (a) a large fixed component, and (b) a 530 * small component that varies with the mii bus frequency. These 531 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x 532 * silicon. Since the effect of (b) was found to be largely 533 * negligible, we keep things simple here. 534 */ 535 udelay(1000); 536 537 bus->read = cpsw_mdio_read; 538 bus->write = cpsw_mdio_write; 539 sprintf(bus->name, name); 540 541 mdio_register(bus); 542 } 543 544 /* Set a self-clearing bit in a register, and wait for it to clear */ 545 static inline void setbit_and_wait_for_clear32(void *addr) 546 { 547 __raw_writel(CLEAR_BIT, addr); 548 while (__raw_readl(addr) & CLEAR_BIT) 549 ; 550 } 551 552 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 553 ((mac)[2] << 16) | ((mac)[3] << 24)) 554 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 555 556 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 557 struct cpsw_priv *priv) 558 { 559 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); 560 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); 561 } 562 563 static void cpsw_slave_update_link(struct cpsw_slave *slave, 564 struct cpsw_priv *priv, int *link) 565 { 566 struct phy_device *phy = priv->phydev; 567 u32 mac_control = 0; 568 569 phy_startup(phy); 570 *link = phy->link; 571 572 if (*link) { /* link up */ 573 mac_control = priv->data.mac_control; 574 if (phy->speed == 1000) 575 mac_control |= GIGABITEN; 576 if (phy->duplex == DUPLEX_FULL) 577 mac_control |= FULLDUPLEXEN; 578 if (phy->speed == 100) 579 mac_control |= MIIEN; 580 } 581 582 if (mac_control == slave->mac_control) 583 return; 584 585 if (mac_control) { 586 printf("link up on port %d, speed %d, %s duplex\n", 587 slave->slave_num, phy->speed, 588 (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 589 } else { 590 printf("link down on port %d\n", slave->slave_num); 591 } 592 593 __raw_writel(mac_control, &slave->sliver->mac_control); 594 slave->mac_control = mac_control; 595 } 596 597 static int cpsw_update_link(struct cpsw_priv *priv) 598 { 599 int link = 0; 600 struct cpsw_slave *slave; 601 602 for_each_slave(slave, priv) 603 cpsw_slave_update_link(slave, priv, &link); 604 priv->mdio_link = readl(&mdio_regs->link); 605 return link; 606 } 607 608 static int cpsw_check_link(struct cpsw_priv *priv) 609 { 610 u32 link = 0; 611 612 link = __raw_readl(&mdio_regs->link) & priv->phy_mask; 613 if ((link) && (link == priv->mdio_link)) 614 return 1; 615 616 return cpsw_update_link(priv); 617 } 618 619 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 620 { 621 if (priv->host_port == 0) 622 return slave_num + 1; 623 else 624 return slave_num; 625 } 626 627 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 628 { 629 u32 slave_port; 630 631 setbit_and_wait_for_clear32(&slave->sliver->soft_reset); 632 633 /* setup priority mapping */ 634 __raw_writel(0x76543210, &slave->sliver->rx_pri_map); 635 __raw_writel(0x33221100, &slave->regs->tx_pri_map); 636 637 /* setup max packet size, and mac address */ 638 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); 639 cpsw_set_slave_mac(slave, priv); 640 641 slave->mac_control = 0; /* no link yet */ 642 643 /* enable forwarding */ 644 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 645 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); 646 647 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); 648 649 priv->phy_mask |= 1 << slave->data->phy_id; 650 } 651 652 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) 653 { 654 struct cpdma_desc *desc = priv->desc_free; 655 656 if (desc) 657 priv->desc_free = desc_read_ptr(desc, hw_next); 658 return desc; 659 } 660 661 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) 662 { 663 if (desc) { 664 desc_write(desc, hw_next, priv->desc_free); 665 priv->desc_free = desc; 666 } 667 } 668 669 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, 670 void *buffer, int len) 671 { 672 struct cpdma_desc *desc, *prev; 673 u32 mode; 674 675 desc = cpdma_desc_alloc(priv); 676 if (!desc) 677 return -ENOMEM; 678 679 if (len < PKT_MIN) 680 len = PKT_MIN; 681 682 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 683 684 desc_write(desc, hw_next, 0); 685 desc_write(desc, hw_buffer, buffer); 686 desc_write(desc, hw_len, len); 687 desc_write(desc, hw_mode, mode | len); 688 desc_write(desc, sw_buffer, buffer); 689 desc_write(desc, sw_len, len); 690 691 if (!chan->head) { 692 /* simple case - first packet enqueued */ 693 chan->head = desc; 694 chan->tail = desc; 695 chan_write(chan, hdp, desc); 696 goto done; 697 } 698 699 /* not the first packet - enqueue at the tail */ 700 prev = chan->tail; 701 desc_write(prev, hw_next, desc); 702 chan->tail = desc; 703 704 /* next check if EOQ has been triggered already */ 705 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) 706 chan_write(chan, hdp, desc); 707 708 done: 709 if (chan->rxfree) 710 chan_write(chan, rxfree, 1); 711 return 0; 712 } 713 714 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, 715 void **buffer, int *len) 716 { 717 struct cpdma_desc *desc = chan->head; 718 u32 status; 719 720 if (!desc) 721 return -ENOENT; 722 723 status = desc_read(desc, hw_mode); 724 725 if (len) 726 *len = status & 0x7ff; 727 728 if (buffer) 729 *buffer = desc_read_ptr(desc, sw_buffer); 730 731 if (status & CPDMA_DESC_OWNER) { 732 if (chan_read(chan, hdp) == 0) { 733 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) 734 chan_write(chan, hdp, desc); 735 } 736 737 return -EBUSY; 738 } 739 740 chan->head = desc_read_ptr(desc, hw_next); 741 chan_write(chan, cp, desc); 742 743 cpdma_desc_free(priv, desc); 744 return 0; 745 } 746 747 static int cpsw_init(struct eth_device *dev, bd_t *bis) 748 { 749 struct cpsw_priv *priv = dev->priv; 750 struct cpsw_slave *slave; 751 int i, ret; 752 753 /* soft reset the controller and initialize priv */ 754 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 755 756 /* initialize and reset the address lookup engine */ 757 cpsw_ale_enable(priv, 1); 758 cpsw_ale_clear(priv, 1); 759 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ 760 761 /* setup host port priority mapping */ 762 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); 763 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 764 765 /* disable priority elevation and enable statistics on all ports */ 766 __raw_writel(0, &priv->regs->ptype); 767 768 /* enable statistics collection only on the host port */ 769 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); 770 771 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); 772 773 cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port, 774 ALE_SECURE); 775 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port); 776 777 for_each_slave(slave, priv) 778 cpsw_slave_init(slave, priv); 779 780 cpsw_update_link(priv); 781 782 /* init descriptor pool */ 783 for (i = 0; i < NUM_DESCS; i++) { 784 desc_write(&priv->descs[i], hw_next, 785 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); 786 } 787 priv->desc_free = &priv->descs[0]; 788 789 /* initialize channels */ 790 if (priv->data.version == CPSW_CTRL_VERSION_2) { 791 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 792 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; 793 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; 794 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 795 796 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 797 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; 798 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; 799 } else { 800 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 801 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; 802 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; 803 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 804 805 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 806 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; 807 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; 808 } 809 810 /* clear dma state */ 811 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 812 813 if (priv->data.version == CPSW_CTRL_VERSION_2) { 814 for (i = 0; i < priv->data.channels; i++) { 815 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 816 * i); 817 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 818 * i); 819 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 820 * i); 821 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 822 * i); 823 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 824 * i); 825 } 826 } else { 827 for (i = 0; i < priv->data.channels; i++) { 828 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 829 * i); 830 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 831 * i); 832 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 833 * i); 834 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 835 * i); 836 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 837 * i); 838 839 } 840 } 841 842 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); 843 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); 844 845 /* submit rx descs */ 846 for (i = 0; i < PKTBUFSRX; i++) { 847 ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i], 848 PKTSIZE); 849 if (ret < 0) { 850 printf("error %d submitting rx desc\n", ret); 851 break; 852 } 853 } 854 855 return 0; 856 } 857 858 static void cpsw_halt(struct eth_device *dev) 859 { 860 struct cpsw_priv *priv = dev->priv; 861 862 writel(0, priv->dma_regs + CPDMA_TXCONTROL); 863 writel(0, priv->dma_regs + CPDMA_RXCONTROL); 864 865 /* soft reset the controller and initialize priv */ 866 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 867 868 /* clear dma state */ 869 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 870 871 priv->data.control(0); 872 } 873 874 static int cpsw_send(struct eth_device *dev, void *packet, int length) 875 { 876 struct cpsw_priv *priv = dev->priv; 877 void *buffer; 878 int len; 879 int timeout = CPDMA_TIMEOUT; 880 881 if (!cpsw_check_link(priv)) 882 return -EIO; 883 884 flush_dcache_range((unsigned long)packet, 885 (unsigned long)packet + length); 886 887 /* first reap completed packets */ 888 while (timeout-- && 889 (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)) 890 ; 891 892 if (timeout == -1) { 893 printf("cpdma_process timeout\n"); 894 return -ETIMEDOUT; 895 } 896 897 return cpdma_submit(priv, &priv->tx_chan, packet, length); 898 } 899 900 static int cpsw_recv(struct eth_device *dev) 901 { 902 struct cpsw_priv *priv = dev->priv; 903 void *buffer; 904 int len; 905 906 cpsw_update_link(priv); 907 908 while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { 909 invalidate_dcache_range((unsigned long)buffer, 910 (unsigned long)buffer + PKTSIZE_ALIGN); 911 NetReceive(buffer, len); 912 cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE); 913 } 914 915 return 0; 916 } 917 918 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, 919 struct cpsw_priv *priv) 920 { 921 void *regs = priv->regs; 922 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 923 slave->slave_num = slave_num; 924 slave->data = data; 925 slave->regs = regs + data->slave_reg_ofs; 926 slave->sliver = regs + data->sliver_reg_ofs; 927 } 928 929 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) 930 { 931 struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv; 932 struct phy_device *phydev; 933 u32 supported = (SUPPORTED_10baseT_Half | 934 SUPPORTED_10baseT_Full | 935 SUPPORTED_100baseT_Half | 936 SUPPORTED_100baseT_Full | 937 SUPPORTED_1000baseT_Full); 938 939 phydev = phy_connect(priv->bus, 940 CONFIG_PHY_ADDR, 941 dev, 942 slave->data->phy_if); 943 944 phydev->supported &= supported; 945 phydev->advertising = phydev->supported; 946 947 priv->phydev = phydev; 948 phy_config(phydev); 949 950 return 1; 951 } 952 953 int cpsw_register(struct cpsw_platform_data *data) 954 { 955 struct cpsw_priv *priv; 956 struct cpsw_slave *slave; 957 void *regs = (void *)data->cpsw_base; 958 struct eth_device *dev; 959 960 dev = calloc(sizeof(*dev), 1); 961 if (!dev) 962 return -ENOMEM; 963 964 priv = calloc(sizeof(*priv), 1); 965 if (!priv) { 966 free(dev); 967 return -ENOMEM; 968 } 969 970 priv->data = *data; 971 priv->dev = dev; 972 973 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); 974 if (!priv->slaves) { 975 free(dev); 976 free(priv); 977 return -ENOMEM; 978 } 979 980 priv->descs = (void *)CPDMA_RAM_ADDR; 981 priv->host_port = data->host_port_num; 982 priv->regs = regs; 983 priv->host_port_regs = regs + data->host_port_reg_ofs; 984 priv->dma_regs = regs + data->cpdma_reg_ofs; 985 priv->ale_regs = regs + data->ale_reg_ofs; 986 987 int idx = 0; 988 989 for_each_slave(slave, priv) { 990 cpsw_slave_setup(slave, idx, priv); 991 idx = idx + 1; 992 } 993 994 strcpy(dev->name, "cpsw"); 995 dev->iobase = 0; 996 dev->init = cpsw_init; 997 dev->halt = cpsw_halt; 998 dev->send = cpsw_send; 999 dev->recv = cpsw_recv; 1000 dev->priv = priv; 1001 1002 eth_register(dev); 1003 1004 cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div); 1005 priv->bus = miiphy_get_dev_by_name(dev->name); 1006 for_each_slave(slave, priv) 1007 cpsw_phy_init(dev, slave); 1008 1009 return 1; 1010 } 1011