16a8a5dc4Sgoda.yusuke /* 26a8a5dc4Sgoda.yusuke * AX88796L(NE2000) support 36a8a5dc4Sgoda.yusuke * 46a8a5dc4Sgoda.yusuke * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 56a8a5dc4Sgoda.yusuke * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 76a8a5dc4Sgoda.yusuke */ 86a8a5dc4Sgoda.yusuke 96a8a5dc4Sgoda.yusuke #ifndef __DRIVERS_AX88796L_H__ 106a8a5dc4Sgoda.yusuke #define __DRIVERS_AX88796L_H__ 116a8a5dc4Sgoda.yusuke 126a8a5dc4Sgoda.yusuke #define DP_DATA (0x10 << 1) 136a8a5dc4Sgoda.yusuke #define START_PG 0x40 /* First page of TX buffer */ 146a8a5dc4Sgoda.yusuke #define START_PG2 0x48 156a8a5dc4Sgoda.yusuke #define STOP_PG 0x80 /* Last page +1 of RX ring */ 166a8a5dc4Sgoda.yusuke #define TX_PAGES 12 176a8a5dc4Sgoda.yusuke #define RX_START (START_PG+TX_PAGES) 186a8a5dc4Sgoda.yusuke #define RX_END STOP_PG 196a8a5dc4Sgoda.yusuke 206a8a5dc4Sgoda.yusuke #define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE 216a8a5dc4Sgoda.yusuke #define AX88796L_BYTE_ACCESS 0x00001000 226a8a5dc4Sgoda.yusuke #define AX88796L_OFFSET 0x00000400 236a8a5dc4Sgoda.yusuke #define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ 246a8a5dc4Sgoda.yusuke AX88796L_BYTE_ACCESS + AX88796L_OFFSET 256a8a5dc4Sgoda.yusuke #define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) 266a8a5dc4Sgoda.yusuke #define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) 276a8a5dc4Sgoda.yusuke 286a8a5dc4Sgoda.yusuke #define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) 296a8a5dc4Sgoda.yusuke #define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) 306a8a5dc4Sgoda.yusuke 316a8a5dc4Sgoda.yusuke #define EECS_HIGH (AX88796L_MEMR |= 0x10) 326a8a5dc4Sgoda.yusuke #define EECS_LOW (AX88796L_MEMR &= 0xef) 336a8a5dc4Sgoda.yusuke #define EECLK_HIGH (AX88796L_MEMR |= 0x80) 346a8a5dc4Sgoda.yusuke #define EECLK_LOW (AX88796L_MEMR &= 0x7f) 356a8a5dc4Sgoda.yusuke #define EEDI_HIGH (AX88796L_MEMR |= 0x20) 366a8a5dc4Sgoda.yusuke #define EEDI_LOW (AX88796L_MEMR &= 0xdf) 376a8a5dc4Sgoda.yusuke #define EEDO ((AX88796L_MEMR & 0x40)>>6) 386a8a5dc4Sgoda.yusuke 396a8a5dc4Sgoda.yusuke #define PAGE0_SET (AX88796L_CR &= 0x3f) 406a8a5dc4Sgoda.yusuke #define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) 416a8a5dc4Sgoda.yusuke 426a8a5dc4Sgoda.yusuke #define BIT_DUMMY 0 436a8a5dc4Sgoda.yusuke #define MAC_EEP_READ 1 446a8a5dc4Sgoda.yusuke #define MAC_EEP_WRITE 2 456a8a5dc4Sgoda.yusuke #define MAC_EEP_ERACE 3 466a8a5dc4Sgoda.yusuke #define MAC_EEP_EWEN 4 476a8a5dc4Sgoda.yusuke #define MAC_EEP_EWDS 5 486a8a5dc4Sgoda.yusuke 496a8a5dc4Sgoda.yusuke /* R7780MP Specific code */ 506a8a5dc4Sgoda.yusuke #if defined(CONFIG_R7780MP) 516a8a5dc4Sgoda.yusuke #define ISA_OFFSET 0x1400 526a8a5dc4Sgoda.yusuke #define DP_IN(_b_, _o_, _d_) (_d_) = \ 536a8a5dc4Sgoda.yusuke *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) 546a8a5dc4Sgoda.yusuke #define DP_OUT(_b_, _o_, _d_) \ 556a8a5dc4Sgoda.yusuke *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) 566a8a5dc4Sgoda.yusuke #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) 576a8a5dc4Sgoda.yusuke #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) 586a8a5dc4Sgoda.yusuke #else 596a8a5dc4Sgoda.yusuke /* Please change for your target boards */ 606a8a5dc4Sgoda.yusuke #define ISA_OFFSET 0x0000 616a8a5dc4Sgoda.yusuke #define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) 626a8a5dc4Sgoda.yusuke #define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) 636a8a5dc4Sgoda.yusuke #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) 646a8a5dc4Sgoda.yusuke #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) 656a8a5dc4Sgoda.yusuke #endif 666a8a5dc4Sgoda.yusuke 676a8a5dc4Sgoda.yusuke #endif /* __DRIVERS_AX88796L_H__ */ 68