1 /* 2 * Altera 10/100/1000 triple speed ethernet mac 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef _ALTERA_TSE_H_ 12 #define _ALTERA_TSE_H_ 13 14 #define __packed_1_ __packed __aligned(1) 15 16 /* dma type */ 17 #define ALT_SGDMA 0 18 19 /* SGDMA Stuff */ 20 #define ALT_SGDMA_STATUS_BUSY_MSK BIT(4) 21 22 #define ALT_SGDMA_CONTROL_RUN_MSK BIT(5) 23 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6) 24 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16) 25 26 /* 27 * Descriptor control bit masks & offsets 28 * 29 * Note: The control byte physically occupies bits [31:24] in memory. 30 * The following bit-offsets are expressed relative to the LSB of 31 * the control register bitfield. 32 */ 33 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0) 34 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1) 35 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2) 36 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7) 37 38 /* 39 * Descriptor status bit masks & offsets 40 * 41 * Note: The status byte physically occupies bits [23:16] in memory. 42 * The following bit-offsets are expressed relative to the LSB of 43 * the status register bitfield. 44 */ 45 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7) 46 47 /* 48 * The SGDMA controller buffer descriptor allocates 49 * 64 bits for each address. To support ANSI C, the 50 * struct implementing a descriptor places 32-bits 51 * of padding directly above each address; each pad must 52 * be cleared when initializing a descriptor. 53 */ 54 55 /* 56 * Buffer Descriptor data structure 57 * 58 */ 59 struct alt_sgdma_descriptor { 60 u32 source; /* the address of data to be read. */ 61 u32 source_pad; 62 63 u32 destination; /* the address to write data */ 64 u32 destination_pad; 65 66 u32 next; /* the next descriptor in the list. */ 67 u32 next_pad; 68 69 u16 bytes_to_transfer; /* the number of bytes to transfer */ 70 u8 read_burst; 71 u8 write_burst; 72 73 u16 actual_bytes_transferred;/* bytes transferred by DMA */ 74 u8 descriptor_status; 75 u8 descriptor_control; 76 77 } __packed_1_; 78 79 /* SG-DMA Control/Status Slave registers map */ 80 81 struct alt_sgdma_registers { 82 u32 status; 83 u32 status_pad[3]; 84 u32 control; 85 u32 control_pad[3]; 86 u32 next_descriptor_pointer; 87 u32 descriptor_pad[3]; 88 }; 89 90 /* TSE Stuff */ 91 #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0) 92 #define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1) 93 #define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3) 94 #define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10) 95 #define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13) 96 #define ALTERA_TSE_CMD_ENA_10_MSK BIT(25) 97 98 #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) 99 #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) 100 101 /* MAC register Space */ 102 103 struct alt_tse_mac { 104 u32 megacore_revision; 105 u32 scratch_pad; 106 u32 command_config; 107 u32 mac_addr_0; 108 u32 mac_addr_1; 109 u32 max_frame_length; 110 u32 pause_quanta; 111 u32 rx_sel_empty_threshold; 112 u32 rx_sel_full_threshold; 113 u32 tx_sel_empty_threshold; 114 u32 tx_sel_full_threshold; 115 u32 rx_almost_empty_threshold; 116 u32 rx_almost_full_threshold; 117 u32 tx_almost_empty_threshold; 118 u32 tx_almost_full_threshold; 119 u32 mdio_phy0_addr; 120 u32 mdio_phy1_addr; 121 122 u32 reserved1[0x29]; 123 124 /*FIFO control register. */ 125 u32 tx_cmd_stat; 126 u32 rx_cmd_stat; 127 128 u32 reserved2[0x44]; 129 130 /*Registers 0 to 31 within PHY device 0/1 */ 131 u32 mdio_phy0[0x20]; 132 u32 mdio_phy1[0x20]; 133 134 /*4 Supplemental MAC Addresses */ 135 u32 supp_mac_addr_0_0; 136 u32 supp_mac_addr_0_1; 137 u32 supp_mac_addr_1_0; 138 u32 supp_mac_addr_1_1; 139 u32 supp_mac_addr_2_0; 140 u32 supp_mac_addr_2_1; 141 u32 supp_mac_addr_3_0; 142 u32 supp_mac_addr_3_1; 143 144 u32 reserved3[0x38]; 145 }; 146 147 struct tse_ops { 148 int (*send)(struct udevice *dev, void *packet, int length); 149 int (*recv)(struct udevice *dev, int flags, uchar **packetp); 150 int (*free_pkt)(struct udevice *dev, uchar *packet, int length); 151 void (*stop)(struct udevice *dev); 152 }; 153 154 struct altera_tse_priv { 155 struct alt_tse_mac *mac_dev; 156 void *sgdma_rx; 157 void *sgdma_tx; 158 unsigned int rx_fifo_depth; 159 unsigned int tx_fifo_depth; 160 void *rx_desc; 161 void *tx_desc; 162 unsigned char *rx_buf; 163 unsigned int phyaddr; 164 unsigned int interface; 165 struct phy_device *phydev; 166 struct mii_dev *bus; 167 const struct tse_ops *ops; 168 int dma_type; 169 }; 170 171 #endif /* _ALTERA_TSE_H_ */ 172