1 /* 2 * Altera 10/100/1000 triple speed ethernet mac driver 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <fdt_support.h> 15 #include <memalign.h> 16 #include <miiphy.h> 17 #include <net.h> 18 #include <asm/cache.h> 19 #include <asm/dma-mapping.h> 20 #include <asm/io.h> 21 #include "altera_tse.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static inline void alt_sgdma_construct_descriptor( 26 struct alt_sgdma_descriptor *desc, 27 struct alt_sgdma_descriptor *next, 28 void *read_addr, 29 void *write_addr, 30 u16 length_or_eop, 31 int generate_eop, 32 int read_fixed, 33 int write_fixed_or_sop) 34 { 35 u8 val; 36 37 /* 38 * Mark the "next" descriptor as "not" owned by hardware. This prevents 39 * The SGDMA controller from continuing to process the chain. 40 */ 41 next->descriptor_control = next->descriptor_control & 42 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; 43 44 memset(desc, 0, sizeof(struct alt_sgdma_descriptor)); 45 desc->source = virt_to_phys(read_addr); 46 desc->destination = virt_to_phys(write_addr); 47 desc->next = virt_to_phys(next); 48 desc->bytes_to_transfer = length_or_eop; 49 50 /* 51 * Set the descriptor control block as follows: 52 * - Set "owned by hardware" bit 53 * - Optionally set "generate EOP" bit 54 * - Optionally set the "read from fixed address" bit 55 * - Optionally set the "write to fixed address bit (which serves 56 * serves as a "generate SOP" control bit in memory-to-stream mode). 57 * - Set the 4-bit atlantic channel, if specified 58 * 59 * Note this step is performed after all other descriptor information 60 * has been filled out so that, if the controller already happens to be 61 * pointing at this descriptor, it will not run (via the "owned by 62 * hardware" bit) until all other descriptor has been set up. 63 */ 64 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; 65 if (generate_eop) 66 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK; 67 if (read_fixed) 68 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK; 69 if (write_fixed_or_sop) 70 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK; 71 desc->descriptor_control = val; 72 } 73 74 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs) 75 { 76 int status; 77 ulong ctime; 78 79 /* Wait for the descriptor (chain) to complete */ 80 ctime = get_timer(0); 81 while (1) { 82 status = readl(®s->status); 83 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK)) 84 break; 85 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { 86 status = -ETIMEDOUT; 87 debug("sgdma timeout\n"); 88 break; 89 } 90 } 91 92 /* Clear Run */ 93 writel(0, ®s->control); 94 /* Clear status */ 95 writel(0xff, ®s->status); 96 97 return status; 98 } 99 100 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs, 101 struct alt_sgdma_descriptor *desc) 102 { 103 u32 val; 104 105 /* Point the controller at the descriptor */ 106 writel(virt_to_phys(desc), ®s->next_descriptor_pointer); 107 108 /* 109 * Set up SGDMA controller to: 110 * - Disable interrupt generation 111 * - Run once a valid descriptor is written to controller 112 * - Stop on an error with any particular descriptor 113 */ 114 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK; 115 writel(val, ®s->control); 116 117 return 0; 118 } 119 120 static void tse_adjust_link(struct altera_tse_priv *priv, 121 struct phy_device *phydev) 122 { 123 struct alt_tse_mac *mac_dev = priv->mac_dev; 124 u32 refvar; 125 126 if (!phydev->link) { 127 debug("%s: No link.\n", phydev->dev->name); 128 return; 129 } 130 131 refvar = readl(&mac_dev->command_config); 132 133 if (phydev->duplex) 134 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; 135 else 136 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; 137 138 switch (phydev->speed) { 139 case 1000: 140 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; 141 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 142 break; 143 case 100: 144 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 145 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 146 break; 147 case 10: 148 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 149 refvar |= ALTERA_TSE_CMD_ENA_10_MSK; 150 break; 151 } 152 writel(refvar, &mac_dev->command_config); 153 } 154 155 static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length) 156 { 157 struct altera_tse_priv *priv = dev_get_priv(dev); 158 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; 159 160 alt_sgdma_construct_descriptor( 161 tx_desc, 162 tx_desc + 1, 163 packet, /* read addr */ 164 NULL, /* write addr */ 165 length, /* length or EOP ,will change for each tx */ 166 1, /* gen eop */ 167 0, /* read fixed */ 168 1 /* write fixed or sop */ 169 ); 170 171 /* send the packet */ 172 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc); 173 alt_sgdma_wait_transfer(priv->sgdma_tx); 174 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred); 175 176 return tx_desc->actual_bytes_transferred; 177 } 178 179 static int altera_tse_recv_sgdma(struct udevice *dev, int flags, 180 uchar **packetp) 181 { 182 struct altera_tse_priv *priv = dev_get_priv(dev); 183 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 184 int packet_length; 185 186 if (rx_desc->descriptor_status & 187 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { 188 alt_sgdma_wait_transfer(priv->sgdma_rx); 189 packet_length = rx_desc->actual_bytes_transferred; 190 debug("recv %d bytes\n", packet_length); 191 *packetp = priv->rx_buf; 192 193 return packet_length; 194 } 195 196 return -EAGAIN; 197 } 198 199 static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet, 200 int length) 201 { 202 struct altera_tse_priv *priv = dev_get_priv(dev); 203 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 204 205 alt_sgdma_construct_descriptor( 206 rx_desc, 207 rx_desc + 1, 208 NULL, /* read addr */ 209 priv->rx_buf, /* write addr */ 210 0, /* length or EOP */ 211 0, /* gen eop */ 212 0, /* read fixed */ 213 0 /* write fixed or sop */ 214 ); 215 216 /* setup the sgdma */ 217 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc); 218 debug("recv setup\n"); 219 220 return 0; 221 } 222 223 static void altera_tse_stop_mac(struct altera_tse_priv *priv) 224 { 225 struct alt_tse_mac *mac_dev = priv->mac_dev; 226 u32 status; 227 ulong ctime; 228 229 /* reset the mac */ 230 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); 231 ctime = get_timer(0); 232 while (1) { 233 status = readl(&mac_dev->command_config); 234 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) 235 break; 236 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { 237 debug("Reset mac timeout\n"); 238 break; 239 } 240 } 241 } 242 243 static void altera_tse_stop_sgdma(struct udevice *dev) 244 { 245 struct altera_tse_priv *priv = dev_get_priv(dev); 246 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; 247 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 248 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 249 int ret; 250 251 /* clear rx desc & wait for sgdma to complete */ 252 rx_desc->descriptor_control = 0; 253 writel(0, &rx_sgdma->control); 254 ret = alt_sgdma_wait_transfer(rx_sgdma); 255 if (ret == -ETIMEDOUT) 256 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, 257 &rx_sgdma->control); 258 259 writel(0, &tx_sgdma->control); 260 ret = alt_sgdma_wait_transfer(tx_sgdma); 261 if (ret == -ETIMEDOUT) 262 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, 263 &tx_sgdma->control); 264 } 265 266 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 267 { 268 struct altera_tse_priv *priv = bus->priv; 269 struct alt_tse_mac *mac_dev = priv->mac_dev; 270 u32 value; 271 272 /* set mdio address */ 273 writel(addr, &mac_dev->mdio_phy1_addr); 274 /* get the data */ 275 value = readl(&mac_dev->mdio_phy1[reg]); 276 277 return value & 0xffff; 278 } 279 280 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 281 u16 val) 282 { 283 struct altera_tse_priv *priv = bus->priv; 284 struct alt_tse_mac *mac_dev = priv->mac_dev; 285 286 /* set mdio address */ 287 writel(addr, &mac_dev->mdio_phy1_addr); 288 /* set the data */ 289 writel(val, &mac_dev->mdio_phy1[reg]); 290 291 return 0; 292 } 293 294 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) 295 { 296 struct mii_dev *bus = mdio_alloc(); 297 298 if (!bus) { 299 printf("Failed to allocate MDIO bus\n"); 300 return -ENOMEM; 301 } 302 303 bus->read = tse_mdio_read; 304 bus->write = tse_mdio_write; 305 snprintf(bus->name, sizeof(bus->name), name); 306 307 bus->priv = (void *)priv; 308 309 return mdio_register(bus); 310 } 311 312 static int tse_phy_init(struct altera_tse_priv *priv, void *dev) 313 { 314 struct phy_device *phydev; 315 unsigned int mask = 0xffffffff; 316 317 if (priv->phyaddr) 318 mask = 1 << priv->phyaddr; 319 320 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 321 if (!phydev) 322 return -ENODEV; 323 324 phy_connect_dev(phydev, dev); 325 326 phydev->supported &= PHY_GBIT_FEATURES; 327 phydev->advertising = phydev->supported; 328 329 priv->phydev = phydev; 330 phy_config(phydev); 331 332 return 0; 333 } 334 335 static int altera_tse_write_hwaddr(struct udevice *dev) 336 { 337 struct altera_tse_priv *priv = dev_get_priv(dev); 338 struct alt_tse_mac *mac_dev = priv->mac_dev; 339 struct eth_pdata *pdata = dev_get_platdata(dev); 340 u8 *hwaddr = pdata->enetaddr; 341 u32 mac_lo, mac_hi; 342 343 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) | 344 (hwaddr[1] << 8) | hwaddr[0]; 345 mac_hi = (hwaddr[5] << 8) | hwaddr[4]; 346 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo); 347 348 writel(mac_lo, &mac_dev->mac_addr_0); 349 writel(mac_hi, &mac_dev->mac_addr_1); 350 writel(mac_lo, &mac_dev->supp_mac_addr_0_0); 351 writel(mac_hi, &mac_dev->supp_mac_addr_0_1); 352 writel(mac_lo, &mac_dev->supp_mac_addr_1_0); 353 writel(mac_hi, &mac_dev->supp_mac_addr_1_1); 354 writel(mac_lo, &mac_dev->supp_mac_addr_2_0); 355 writel(mac_hi, &mac_dev->supp_mac_addr_2_1); 356 writel(mac_lo, &mac_dev->supp_mac_addr_3_0); 357 writel(mac_hi, &mac_dev->supp_mac_addr_3_1); 358 359 return 0; 360 } 361 362 static int altera_tse_send(struct udevice *dev, void *packet, int length) 363 { 364 struct altera_tse_priv *priv = dev_get_priv(dev); 365 unsigned long tx_buf = (unsigned long)packet; 366 367 flush_dcache_range(tx_buf, tx_buf + length); 368 369 return priv->ops->send(dev, packet, length); 370 } 371 372 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) 373 { 374 struct altera_tse_priv *priv = dev_get_priv(dev); 375 376 return priv->ops->recv(dev, flags, packetp); 377 } 378 379 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, 380 int length) 381 { 382 struct altera_tse_priv *priv = dev_get_priv(dev); 383 unsigned long rx_buf = (unsigned long)priv->rx_buf; 384 385 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); 386 387 return priv->ops->free_pkt(dev, packet, length); 388 } 389 390 static void altera_tse_stop(struct udevice *dev) 391 { 392 struct altera_tse_priv *priv = dev_get_priv(dev); 393 394 priv->ops->stop(dev); 395 altera_tse_stop_mac(priv); 396 } 397 398 static int altera_tse_start(struct udevice *dev) 399 { 400 struct altera_tse_priv *priv = dev_get_priv(dev); 401 struct alt_tse_mac *mac_dev = priv->mac_dev; 402 u32 val; 403 int ret; 404 405 /* need to create sgdma */ 406 debug("Configuring rx desc\n"); 407 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN); 408 /* start TSE */ 409 debug("Configuring TSE Mac\n"); 410 /* Initialize MAC registers */ 411 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length); 412 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold); 413 writel(0, &mac_dev->rx_sel_full_threshold); 414 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold); 415 writel(0, &mac_dev->tx_sel_full_threshold); 416 writel(8, &mac_dev->rx_almost_empty_threshold); 417 writel(8, &mac_dev->rx_almost_full_threshold); 418 writel(8, &mac_dev->tx_almost_empty_threshold); 419 writel(3, &mac_dev->tx_almost_full_threshold); 420 421 /* NO Shift */ 422 writel(0, &mac_dev->rx_cmd_stat); 423 writel(0, &mac_dev->tx_cmd_stat); 424 425 /* enable MAC */ 426 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; 427 writel(val, &mac_dev->command_config); 428 429 /* Start up the PHY */ 430 ret = phy_startup(priv->phydev); 431 if (ret) { 432 debug("Could not initialize PHY %s\n", 433 priv->phydev->dev->name); 434 return ret; 435 } 436 437 tse_adjust_link(priv, priv->phydev); 438 439 if (!priv->phydev->link) 440 return -EIO; 441 442 return 0; 443 } 444 445 static const struct tse_ops tse_sgdma_ops = { 446 .send = altera_tse_send_sgdma, 447 .recv = altera_tse_recv_sgdma, 448 .free_pkt = altera_tse_free_pkt_sgdma, 449 .stop = altera_tse_stop_sgdma, 450 }; 451 452 static int altera_tse_probe(struct udevice *dev) 453 { 454 struct eth_pdata *pdata = dev_get_platdata(dev); 455 struct altera_tse_priv *priv = dev_get_priv(dev); 456 void *blob = (void *)gd->fdt_blob; 457 int node = dev->of_offset; 458 const char *list, *end; 459 const fdt32_t *cell; 460 void *base, *desc_mem = NULL; 461 unsigned long addr, size; 462 int parent, addrc, sizec; 463 int len, idx; 464 int ret; 465 466 priv->dma_type = dev_get_driver_data(dev); 467 if (priv->dma_type == ALT_SGDMA) 468 priv->ops = &tse_sgdma_ops; 469 /* 470 * decode regs. there are multiple reg tuples, and they need to 471 * match with reg-names. 472 */ 473 parent = fdt_parent_offset(blob, node); 474 of_bus_default_count_cells(blob, parent, &addrc, &sizec); 475 list = fdt_getprop(blob, node, "reg-names", &len); 476 if (!list) 477 return -ENOENT; 478 end = list + len; 479 cell = fdt_getprop(blob, node, "reg", &len); 480 if (!cell) 481 return -ENOENT; 482 idx = 0; 483 while (list < end) { 484 addr = fdt_translate_address((void *)blob, 485 node, cell + idx); 486 size = fdt_addr_to_cpu(cell[idx + addrc]); 487 base = ioremap(addr, size); 488 len = strlen(list); 489 if (strcmp(list, "control_port") == 0) 490 priv->mac_dev = base; 491 else if (strcmp(list, "rx_csr") == 0) 492 priv->sgdma_rx = base; 493 else if (strcmp(list, "tx_csr") == 0) 494 priv->sgdma_tx = base; 495 else if (strcmp(list, "s1") == 0) 496 desc_mem = base; 497 idx += addrc + sizec; 498 list += (len + 1); 499 } 500 /* decode fifo depth */ 501 priv->rx_fifo_depth = fdtdec_get_int(blob, node, 502 "rx-fifo-depth", 0); 503 priv->tx_fifo_depth = fdtdec_get_int(blob, node, 504 "tx-fifo-depth", 0); 505 /* decode phy */ 506 addr = fdtdec_get_int(blob, node, 507 "phy-handle", 0); 508 addr = fdt_node_offset_by_phandle(blob, addr); 509 priv->phyaddr = fdtdec_get_int(blob, addr, 510 "reg", 0); 511 /* init desc */ 512 if (priv->dma_type == ALT_SGDMA) { 513 len = sizeof(struct alt_sgdma_descriptor) * 4; 514 if (!desc_mem) { 515 desc_mem = dma_alloc_coherent(len, &addr); 516 if (!desc_mem) 517 return -ENOMEM; 518 } 519 memset(desc_mem, 0, len); 520 priv->tx_desc = desc_mem; 521 priv->rx_desc = priv->tx_desc + 522 2 * sizeof(struct alt_sgdma_descriptor); 523 } 524 /* allocate recv packet buffer */ 525 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN); 526 if (!priv->rx_buf) 527 return -ENOMEM; 528 529 /* stop controller */ 530 debug("Reset TSE & SGDMAs\n"); 531 altera_tse_stop(dev); 532 533 /* start the phy */ 534 priv->interface = pdata->phy_interface; 535 tse_mdio_init(dev->name, priv); 536 priv->bus = miiphy_get_dev_by_name(dev->name); 537 538 ret = tse_phy_init(priv, dev); 539 540 return ret; 541 } 542 543 static int altera_tse_ofdata_to_platdata(struct udevice *dev) 544 { 545 struct eth_pdata *pdata = dev_get_platdata(dev); 546 const char *phy_mode; 547 548 pdata->phy_interface = -1; 549 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 550 if (phy_mode) 551 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 552 if (pdata->phy_interface == -1) { 553 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 554 return -EINVAL; 555 } 556 557 return 0; 558 } 559 560 static const struct eth_ops altera_tse_ops = { 561 .start = altera_tse_start, 562 .send = altera_tse_send, 563 .recv = altera_tse_recv, 564 .free_pkt = altera_tse_free_pkt, 565 .stop = altera_tse_stop, 566 .write_hwaddr = altera_tse_write_hwaddr, 567 }; 568 569 static const struct udevice_id altera_tse_ids[] = { 570 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA }, 571 {} 572 }; 573 574 U_BOOT_DRIVER(altera_tse) = { 575 .name = "altera_tse", 576 .id = UCLASS_ETH, 577 .of_match = altera_tse_ids, 578 .ops = &altera_tse_ops, 579 .ofdata_to_platdata = altera_tse_ofdata_to_platdata, 580 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 581 .priv_auto_alloc_size = sizeof(struct altera_tse_priv), 582 .probe = altera_tse_probe, 583 }; 584