1 /* 2 * Altera 10/100/1000 triple speed ethernet mac driver 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <config.h> 12 #include <common.h> 13 #include <malloc.h> 14 #include <net.h> 15 #include <command.h> 16 #include <asm/cache.h> 17 #include <asm/dma-mapping.h> 18 #include <miiphy.h> 19 #include "altera_tse.h" 20 21 /* sgdma debug - print descriptor */ 22 static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc) 23 { 24 debug("SGDMA DEBUG :\n"); 25 debug("desc->source : 0x%x \n", (unsigned int)desc->source); 26 debug("desc->destination : 0x%x \n", (unsigned int)desc->destination); 27 debug("desc->next : 0x%x \n", (unsigned int)desc->next); 28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad); 29 debug("desc->destination_pad : 0x%x \n", 30 (unsigned int)desc->destination_pad); 31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad); 32 debug("desc->bytes_to_transfer : 0x%x \n", 33 (unsigned int)desc->bytes_to_transfer); 34 debug("desc->actual_bytes_transferred : 0x%x \n", 35 (unsigned int)desc->actual_bytes_transferred); 36 debug("desc->descriptor_status : 0x%x \n", 37 (unsigned int)desc->descriptor_status); 38 debug("desc->descriptor_control : 0x%x \n", 39 (unsigned int)desc->descriptor_control); 40 } 41 42 /* This is a generic routine that the SGDMA mode-specific routines 43 * call to populate a descriptor. 44 * arg1 :pointer to first SGDMA descriptor. 45 * arg2 :pointer to next SGDMA descriptor. 46 * arg3 :Address to where data to be written. 47 * arg4 :Address from where data to be read. 48 * arg5 :no of byte to transaction. 49 * arg6 :variable indicating to generate start of packet or not 50 * arg7 :read fixed 51 * arg8 :write fixed 52 * arg9 :read burst 53 * arg10 :write burst 54 * arg11 :atlantic_channel number 55 */ 56 static void alt_sgdma_construct_descriptor_burst( 57 volatile struct alt_sgdma_descriptor *desc, 58 volatile struct alt_sgdma_descriptor *next, 59 unsigned int *read_addr, 60 unsigned int *write_addr, 61 unsigned short length_or_eop, 62 int generate_eop, 63 int read_fixed, 64 int write_fixed_or_sop, 65 int read_burst, 66 int write_burst, 67 unsigned char atlantic_channel) 68 { 69 /* 70 * Mark the "next" descriptor as "not" owned by hardware. This prevents 71 * The SGDMA controller from continuing to process the chain. This is 72 * done as a single IO write to bypass cache, without flushing 73 * the entire descriptor, since only the 8-bit descriptor status must 74 * be flushed. 75 */ 76 if (!next) 77 debug("Next descriptor not defined!!\n"); 78 79 next->descriptor_control = (next->descriptor_control & 80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK); 81 82 desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF); 83 desc->destination = 84 (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF); 85 desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF); 86 desc->source_pad = 0x0; 87 desc->destination_pad = 0x0; 88 desc->next_pad = 0x0; 89 desc->bytes_to_transfer = length_or_eop; 90 desc->actual_bytes_transferred = 0; 91 desc->descriptor_status = 0x0; 92 93 /* SGDMA burst not currently supported */ 94 desc->read_burst = 0; 95 desc->write_burst = 0; 96 97 /* 98 * Set the descriptor control block as follows: 99 * - Set "owned by hardware" bit 100 * - Optionally set "generate EOP" bit 101 * - Optionally set the "read from fixed address" bit 102 * - Optionally set the "write to fixed address bit (which serves 103 * serves as a "generate SOP" control bit in memory-to-stream mode). 104 * - Set the 4-bit atlantic channel, if specified 105 * 106 * Note this step is performed after all other descriptor information 107 * has been filled out so that, if the controller already happens to be 108 * pointing at this descriptor, it will not run (via the "owned by 109 * hardware" bit) until all other descriptor has been set up. 110 */ 111 112 desc->descriptor_control = 113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) | 114 (generate_eop ? 115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) | 116 (read_fixed ? 117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) | 118 (write_fixed_or_sop ? 119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) | 120 (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0) 121 ); 122 } 123 124 static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev, 125 volatile struct alt_sgdma_descriptor *desc) 126 { 127 unsigned int status; 128 int counter = 0; 129 130 /* Wait for any pending transfers to complete */ 131 alt_sgdma_print_desc(desc); 132 status = dev->status; 133 134 counter = 0; 135 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { 136 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 137 break; 138 } 139 140 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 141 debug("Timeout waiting sgdma in do sync!\n"); 142 143 /* 144 * Clear any (previous) status register information 145 * that might occlude our error checking later. 146 */ 147 dev->status = 0xFF; 148 149 /* Point the controller at the descriptor */ 150 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; 151 debug("next desc in sgdma 0x%x\n", 152 (unsigned int)dev->next_descriptor_pointer); 153 154 /* 155 * Set up SGDMA controller to: 156 * - Disable interrupt generation 157 * - Run once a valid descriptor is written to controller 158 * - Stop on an error with any particular descriptor 159 */ 160 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | 161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); 162 163 /* Wait for the descriptor (chain) to complete */ 164 status = dev->status; 165 debug("wait for sgdma...."); 166 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) 167 ; 168 debug("done\n"); 169 170 /* Clear Run */ 171 dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK)); 172 173 /* Get & clear status register contents */ 174 status = dev->status; 175 dev->status = 0xFF; 176 177 /* we really should check if the transfer completes properly */ 178 debug("tx sgdma status = 0x%x", status); 179 return 0; 180 } 181 182 static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, 183 volatile struct alt_sgdma_descriptor *desc) 184 { 185 unsigned int status; 186 int counter = 0; 187 188 /* Wait for any pending transfers to complete */ 189 alt_sgdma_print_desc(desc); 190 status = dev->status; 191 192 counter = 0; 193 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { 194 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 195 break; 196 } 197 198 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 199 debug("Timeout waiting sgdma in do async!\n"); 200 201 /* 202 * Clear the RUN bit in the control register. This is needed 203 * to restart the SGDMA engine later on. 204 */ 205 dev->control = 0; 206 207 /* 208 * Clear any (previous) status register information 209 * that might occlude our error checking later. 210 */ 211 dev->status = 0xFF; 212 213 /* Point the controller at the descriptor */ 214 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; 215 216 /* 217 * Set up SGDMA controller to: 218 * - Disable interrupt generation 219 * - Run once a valid descriptor is written to controller 220 * - Stop on an error with any particular descriptor 221 */ 222 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | 223 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); 224 225 /* we really should check if the transfer completes properly */ 226 return 0; 227 } 228 229 /* u-boot interface */ 230 static int tse_adjust_link(struct altera_tse_priv *priv) 231 { 232 unsigned int refvar; 233 234 refvar = priv->mac_dev->command_config.image; 235 236 if (!(priv->duplexity)) 237 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; 238 else 239 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; 240 241 switch (priv->speed) { 242 case 1000: 243 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; 244 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 245 break; 246 case 100: 247 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 248 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 249 break; 250 case 10: 251 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 252 refvar |= ALTERA_TSE_CMD_ENA_10_MSK; 253 break; 254 } 255 priv->mac_dev->command_config.image = refvar; 256 257 return 0; 258 } 259 260 static int tse_eth_send(struct eth_device *dev, 261 volatile void *packet, int length) 262 { 263 struct altera_tse_priv *priv = dev->priv; 264 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 265 volatile struct alt_sgdma_descriptor *tx_desc = 266 (volatile struct alt_sgdma_descriptor *)priv->tx_desc; 267 268 volatile struct alt_sgdma_descriptor *tx_desc_cur = 269 (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; 270 271 flush_dcache((unsigned long)packet, length); 272 alt_sgdma_construct_descriptor_burst( 273 (volatile struct alt_sgdma_descriptor *)&tx_desc[0], 274 (volatile struct alt_sgdma_descriptor *)&tx_desc[1], 275 (unsigned int *)packet, /* read addr */ 276 (unsigned int *)0, 277 length, /* length or EOP ,will change for each tx */ 278 0x1, /* gen eop */ 279 0x0, /* read fixed */ 280 0x1, /* write fixed or sop */ 281 0x0, /* read burst */ 282 0x0, /* write burst */ 283 0x0 /* channel */ 284 ); 285 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length); 286 287 /* send the packet */ 288 debug("sending packet\n"); 289 alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur); 290 debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred); 291 return tx_desc_cur->actual_bytes_transferred; 292 } 293 294 static int tse_eth_rx(struct eth_device *dev) 295 { 296 int packet_length = 0; 297 struct altera_tse_priv *priv = dev->priv; 298 volatile struct alt_sgdma_descriptor *rx_desc = 299 (volatile struct alt_sgdma_descriptor *)priv->rx_desc; 300 volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0]; 301 302 if (rx_desc_cur->descriptor_status & 303 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { 304 debug("got packet\n"); 305 packet_length = rx_desc->actual_bytes_transferred; 306 NetReceive(NetRxPackets[0], packet_length); 307 308 /* start descriptor again */ 309 flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); 310 alt_sgdma_construct_descriptor_burst( 311 (volatile struct alt_sgdma_descriptor *)&rx_desc[0], 312 (volatile struct alt_sgdma_descriptor *)&rx_desc[1], 313 (unsigned int)0x0, /* read addr */ 314 (unsigned int *)NetRxPackets[0], 315 0x0, /* length or EOP */ 316 0x0, /* gen eop */ 317 0x0, /* read fixed */ 318 0x0, /* write fixed or sop */ 319 0x0, /* read burst */ 320 0x0, /* write burst */ 321 0x0 /* channel */ 322 ); 323 324 /* setup the sgdma */ 325 alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); 326 } 327 328 return -1; 329 } 330 331 static void tse_eth_halt(struct eth_device *dev) 332 { 333 /* don't do anything! */ 334 /* this gets called after each uboot */ 335 /* network command. don't need to reset the thing all of the time */ 336 } 337 338 static void tse_eth_reset(struct eth_device *dev) 339 { 340 /* stop sgdmas, disable tse receive */ 341 struct altera_tse_priv *priv = dev->priv; 342 volatile struct alt_tse_mac *mac_dev = priv->mac_dev; 343 volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; 344 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 345 int counter; 346 volatile struct alt_sgdma_descriptor *rx_desc = 347 (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0]; 348 349 /* clear rx desc & wait for sgdma to complete */ 350 rx_desc->descriptor_control = 0; 351 rx_sgdma->control = 0; 352 counter = 0; 353 while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { 354 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 355 break; 356 } 357 358 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { 359 debug("Timeout waiting for rx sgdma!\n"); 360 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 361 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 362 } 363 364 counter = 0; 365 tx_sgdma->control = 0; 366 while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { 367 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 368 break; 369 } 370 371 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { 372 debug("Timeout waiting for tx sgdma!\n"); 373 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 374 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 375 } 376 /* reset the mac */ 377 mac_dev->command_config.bits.transmit_enable = 1; 378 mac_dev->command_config.bits.receive_enable = 1; 379 mac_dev->command_config.bits.software_reset = 1; 380 381 counter = 0; 382 while (mac_dev->command_config.bits.software_reset) { 383 if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR) 384 break; 385 } 386 387 if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR) 388 debug("TSEMAC SW reset bit never cleared!\n"); 389 } 390 391 static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum) 392 { 393 volatile struct alt_tse_mac *mac_dev; 394 unsigned int *mdio_regs; 395 unsigned int data; 396 u16 value; 397 398 mac_dev = priv->mac_dev; 399 400 /* set mdio address */ 401 mac_dev->mdio_phy1_addr = priv->phyaddr; 402 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; 403 404 /* get the data */ 405 data = mdio_regs[regnum]; 406 407 value = data & 0xffff; 408 409 return value; 410 } 411 412 static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, 413 unsigned int value) 414 { 415 volatile struct alt_tse_mac *mac_dev; 416 unsigned int *mdio_regs; 417 unsigned int data; 418 419 mac_dev = priv->mac_dev; 420 421 /* set mdio address */ 422 mac_dev->mdio_phy1_addr = priv->phyaddr; 423 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; 424 425 /* get the data */ 426 data = (unsigned int)value; 427 428 mdio_regs[regnum] = data; 429 430 return 0; 431 } 432 433 /* MDIO access to phy */ 434 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) 435 static int altera_tse_miiphy_write(const char *devname, unsigned char addr, 436 unsigned char reg, unsigned short value) 437 { 438 struct eth_device *dev; 439 struct altera_tse_priv *priv; 440 dev = eth_get_dev_by_name(devname); 441 priv = dev->priv; 442 443 tse_mdio_write(priv, (uint) reg, (uint) value); 444 445 return 0; 446 } 447 448 static int altera_tse_miiphy_read(const char *devname, unsigned char addr, 449 unsigned char reg, unsigned short *value) 450 { 451 struct eth_device *dev; 452 struct altera_tse_priv *priv; 453 volatile struct alt_tse_mac *mac_dev; 454 unsigned int *mdio_regs; 455 456 dev = eth_get_dev_by_name(devname); 457 priv = dev->priv; 458 459 mac_dev = priv->mac_dev; 460 mac_dev->mdio_phy1_addr = (int)addr; 461 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; 462 463 *value = 0xffff & mdio_regs[reg]; 464 465 return 0; 466 467 } 468 #endif 469 470 /* 471 * Also copied from tsec.c 472 */ 473 /* Parse the status register for link, and then do 474 * auto-negotiation 475 */ 476 static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) 477 { 478 /* 479 * Wait if the link is up, and autonegotiation is in progress 480 * (ie - we're capable and it's not done) 481 */ 482 mii_reg = tse_mdio_read(priv, MIIM_STATUS); 483 484 if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE) 485 && !(mii_reg & BMSR_ANEGCOMPLETE)) { 486 int i = 0; 487 488 puts("Waiting for PHY auto negotiation to complete"); 489 while (!(mii_reg & BMSR_ANEGCOMPLETE)) { 490 /* 491 * Timeout reached ? 492 */ 493 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 494 puts(" TIMEOUT !\n"); 495 priv->link = 0; 496 return 0; 497 } 498 499 if ((i++ % 1000) == 0) 500 putc('.'); 501 udelay(1000); /* 1 ms */ 502 mii_reg = tse_mdio_read(priv, MIIM_STATUS); 503 } 504 puts(" done\n"); 505 priv->link = 1; 506 udelay(500000); /* another 500 ms (results in faster booting) */ 507 } else { 508 if (mii_reg & MIIM_STATUS_LINK) { 509 debug("Link is up\n"); 510 priv->link = 1; 511 } else { 512 debug("Link is down\n"); 513 priv->link = 0; 514 } 515 } 516 517 return 0; 518 } 519 520 /* Parse the 88E1011's status register for speed and duplex 521 * information 522 */ 523 static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv) 524 { 525 uint speed; 526 527 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); 528 529 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 530 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 531 int i = 0; 532 533 puts("Waiting for PHY realtime link"); 534 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 535 /* Timeout reached ? */ 536 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 537 puts(" TIMEOUT !\n"); 538 priv->link = 0; 539 break; 540 } 541 542 if ((i++ == 1000) == 0) { 543 i = 0; 544 puts("."); 545 } 546 udelay(1000); /* 1 ms */ 547 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); 548 } 549 puts(" done\n"); 550 udelay(500000); /* another 500 ms (results in faster booting) */ 551 } else { 552 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 553 priv->link = 1; 554 else 555 priv->link = 0; 556 } 557 558 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 559 priv->duplexity = 1; 560 else 561 priv->duplexity = 0; 562 563 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 564 565 switch (speed) { 566 case MIIM_88E1011_PHYSTAT_GBIT: 567 priv->speed = 1000; 568 debug("PHY Speed is 1000Mbit\n"); 569 break; 570 case MIIM_88E1011_PHYSTAT_100: 571 debug("PHY Speed is 100Mbit\n"); 572 priv->speed = 100; 573 break; 574 default: 575 debug("PHY Speed is 10Mbit\n"); 576 priv->speed = 10; 577 } 578 579 return 0; 580 } 581 582 static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) 583 { 584 uint mii_data = tse_mdio_read(priv, mii_reg); 585 mii_data &= 0xfff0; 586 mii_data |= 0xb; 587 return mii_data; 588 } 589 590 static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) 591 { 592 uint mii_data = tse_mdio_read(priv, mii_reg); 593 mii_data &= ~0x82; 594 mii_data |= 0x82; 595 return mii_data; 596 } 597 598 /* 599 * Returns which value to write to the control register. 600 * For 10/100, the value is slightly different 601 */ 602 static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv) 603 { 604 return MIIM_CONTROL_INIT; 605 } 606 607 /* 608 * PHY & MDIO code 609 * Need to add SGMII stuff 610 * 611 */ 612 613 static struct phy_info phy_info_M88E1111S = { 614 0x01410cc, 615 "Marvell 88E1111S", 616 4, 617 (struct phy_cmd[]){ /* config */ 618 /* Reset and configure the PHY */ 619 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 620 {MIIM_88E1111_PHY_EXT_SR, 0x848f, 621 &mii_m88e1111s_setmode_sr}, 622 /* Delay RGMII TX and RX */ 623 {MIIM_88E1111_PHY_EXT_CR, 0x0cd2, 624 &mii_m88e1111s_setmode_cr}, 625 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 626 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 627 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 628 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 629 {miim_end,} 630 }, 631 (struct phy_cmd[]){ /* startup */ 632 /* Status is read once to clear old link state */ 633 {MIIM_STATUS, miim_read, NULL}, 634 /* Auto-negotiate */ 635 {MIIM_STATUS, miim_read, &mii_parse_sr}, 636 /* Read the status */ 637 {MIIM_88E1011_PHY_STATUS, miim_read, 638 &mii_parse_88E1011_psr}, 639 {miim_end,} 640 }, 641 (struct phy_cmd[]){ /* shutdown */ 642 {miim_end,} 643 }, 644 }; 645 646 /* a generic flavor. */ 647 static struct phy_info phy_info_generic = { 648 0, 649 "Unknown/Generic PHY", 650 32, 651 (struct phy_cmd[]){ /* config */ 652 {MII_BMCR, BMCR_RESET, NULL}, 653 {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL}, 654 {miim_end,} 655 }, 656 (struct phy_cmd[]){ /* startup */ 657 {MII_BMSR, miim_read, NULL}, 658 {MII_BMSR, miim_read, &mii_parse_sr}, 659 {miim_end,} 660 }, 661 (struct phy_cmd[]){ /* shutdown */ 662 {miim_end,} 663 } 664 }; 665 666 static struct phy_info *phy_info[] = { 667 &phy_info_M88E1111S, 668 NULL 669 }; 670 671 /* Grab the identifier of the device's PHY, and search through 672 * all of the known PHYs to see if one matches. If so, return 673 * it, if not, return NULL 674 */ 675 static struct phy_info *get_phy_info(struct eth_device *dev) 676 { 677 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; 678 uint phy_reg, phy_ID; 679 int i; 680 struct phy_info *theInfo = NULL; 681 682 /* Grab the bits from PHYIR1, and put them in the upper half */ 683 phy_reg = tse_mdio_read(priv, MIIM_PHYIR1); 684 phy_ID = (phy_reg & 0xffff) << 16; 685 686 /* Grab the bits from PHYIR2, and put them in the lower half */ 687 phy_reg = tse_mdio_read(priv, MIIM_PHYIR2); 688 phy_ID |= (phy_reg & 0xffff); 689 690 /* loop through all the known PHY types, and find one that */ 691 /* matches the ID we read from the PHY. */ 692 for (i = 0; phy_info[i]; i++) { 693 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 694 theInfo = phy_info[i]; 695 break; 696 } 697 } 698 699 if (theInfo == NULL) { 700 theInfo = &phy_info_generic; 701 debug("%s: No support for PHY id %x; assuming generic\n", 702 dev->name, phy_ID); 703 } else 704 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 705 706 return theInfo; 707 } 708 709 /* Execute the given series of commands on the given device's 710 * PHY, running functions as necessary 711 */ 712 static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd) 713 { 714 int i; 715 uint result; 716 717 for (i = 0; cmd->mii_reg != miim_end; i++) { 718 if (cmd->mii_data == miim_read) { 719 result = tse_mdio_read(priv, cmd->mii_reg); 720 721 if (cmd->funct != NULL) 722 (*(cmd->funct)) (result, priv); 723 724 } else { 725 if (cmd->funct != NULL) 726 result = (*(cmd->funct)) (cmd->mii_reg, priv); 727 else 728 result = cmd->mii_data; 729 730 tse_mdio_write(priv, cmd->mii_reg, result); 731 732 } 733 cmd++; 734 } 735 } 736 737 /* Phy init code */ 738 static int init_phy(struct eth_device *dev) 739 { 740 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; 741 struct phy_info *curphy; 742 743 /* Get the cmd structure corresponding to the attached 744 * PHY */ 745 curphy = get_phy_info(dev); 746 747 if (curphy == NULL) { 748 priv->phyinfo = NULL; 749 debug("%s: No PHY found\n", dev->name); 750 751 return 0; 752 } else 753 debug("%s found\n", curphy->name); 754 priv->phyinfo = curphy; 755 756 phy_run_commands(priv, priv->phyinfo->config); 757 758 return 1; 759 } 760 761 static int tse_set_mac_address(struct eth_device *dev) 762 { 763 struct altera_tse_priv *priv = dev->priv; 764 volatile struct alt_tse_mac *mac_dev = priv->mac_dev; 765 766 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n", 767 dev->enetaddr[5], dev->enetaddr[4], 768 dev->enetaddr[3], dev->enetaddr[2], 769 dev->enetaddr[1], dev->enetaddr[0]); 770 mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | 771 (dev->enetaddr[2]) << 16 | 772 (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); 773 774 mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | 775 (dev->enetaddr[4])) & 0xFFFF); 776 777 /* Set the MAC address */ 778 mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; 779 mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; 780 781 /* Set the MAC address */ 782 mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; 783 mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; 784 785 /* Set the MAC address */ 786 mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; 787 mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; 788 789 /* Set the MAC address */ 790 mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; 791 mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; 792 return 0; 793 } 794 795 static int tse_eth_init(struct eth_device *dev, bd_t * bd) 796 { 797 int dat; 798 struct altera_tse_priv *priv = dev->priv; 799 volatile struct alt_tse_mac *mac_dev = priv->mac_dev; 800 volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; 801 volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 802 volatile struct alt_sgdma_descriptor *rx_desc_cur = 803 (volatile struct alt_sgdma_descriptor *)&rx_desc[0]; 804 805 /* stop controller */ 806 debug("Reseting TSE & SGDMAs\n"); 807 tse_eth_reset(dev); 808 809 /* start the phy */ 810 debug("Configuring PHY\n"); 811 phy_run_commands(priv, priv->phyinfo->startup); 812 813 /* need to create sgdma */ 814 debug("Configuring tx desc\n"); 815 alt_sgdma_construct_descriptor_burst( 816 (volatile struct alt_sgdma_descriptor *)&tx_desc[0], 817 (volatile struct alt_sgdma_descriptor *)&tx_desc[1], 818 (unsigned int *)NULL, /* read addr */ 819 (unsigned int *)0, 820 0, /* length or EOP ,will change for each tx */ 821 0x1, /* gen eop */ 822 0x0, /* read fixed */ 823 0x1, /* write fixed or sop */ 824 0x0, /* read burst */ 825 0x0, /* write burst */ 826 0x0 /* channel */ 827 ); 828 debug("Configuring rx desc\n"); 829 flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); 830 alt_sgdma_construct_descriptor_burst( 831 (volatile struct alt_sgdma_descriptor *)&rx_desc[0], 832 (volatile struct alt_sgdma_descriptor *)&rx_desc[1], 833 (unsigned int)0x0, /* read addr */ 834 (unsigned int *)NetRxPackets[0], 835 0x0, /* length or EOP */ 836 0x0, /* gen eop */ 837 0x0, /* read fixed */ 838 0x0, /* write fixed or sop */ 839 0x0, /* read burst */ 840 0x0, /* write burst */ 841 0x0 /* channel */ 842 ); 843 /* start rx async transfer */ 844 debug("Starting rx sgdma\n"); 845 alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur); 846 847 /* start TSE */ 848 debug("Configuring TSE Mac\n"); 849 /* Initialize MAC registers */ 850 mac_dev->max_frame_length = PKTSIZE_ALIGN; 851 mac_dev->rx_almost_empty_threshold = 8; 852 mac_dev->rx_almost_full_threshold = 8; 853 mac_dev->tx_almost_empty_threshold = 8; 854 mac_dev->tx_almost_full_threshold = 3; 855 mac_dev->tx_sel_empty_threshold = 856 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; 857 mac_dev->tx_sel_full_threshold = 0; 858 mac_dev->rx_sel_empty_threshold = 859 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; 860 mac_dev->rx_sel_full_threshold = 0; 861 862 /* NO Shift */ 863 mac_dev->rx_cmd_stat.bits.rx_shift16 = 0; 864 mac_dev->tx_cmd_stat.bits.tx_shift16 = 0; 865 866 /* enable MAC */ 867 dat = 0; 868 dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; 869 870 mac_dev->command_config.image = dat; 871 872 /* configure the TSE core */ 873 /* -- output clocks, */ 874 /* -- and later config stuff for SGMII */ 875 if (priv->link) { 876 debug("Adjusting TSE to link speed\n"); 877 tse_adjust_link(priv); 878 } 879 880 return priv->link ? 0 : -1; 881 } 882 883 /* TSE init code */ 884 int altera_tse_initialize(u8 dev_num, int mac_base, 885 int sgdma_rx_base, int sgdma_tx_base) 886 { 887 struct altera_tse_priv *priv; 888 struct eth_device *dev; 889 struct alt_sgdma_descriptor *rx_desc; 890 struct alt_sgdma_descriptor *tx_desc; 891 unsigned long dma_handle; 892 893 dev = (struct eth_device *)malloc(sizeof *dev); 894 895 if (NULL == dev) 896 return 0; 897 898 memset(dev, 0, sizeof *dev); 899 900 priv = malloc(sizeof(*priv)); 901 902 if (!priv) { 903 free(dev); 904 return 0; 905 } 906 tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), 907 &dma_handle); 908 rx_desc = tx_desc + 2; 909 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); 910 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc); 911 912 if (!tx_desc) { 913 free(priv); 914 free(dev); 915 return 0; 916 } 917 memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); 918 memset(tx_desc, 0, (sizeof *tx_desc) * 2); 919 920 /* initialize tse priv */ 921 priv->mac_dev = (volatile struct alt_tse_mac *)mac_base; 922 priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base; 923 priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base; 924 priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR; 925 priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS; 926 priv->rx_desc = rx_desc; 927 priv->tx_desc = tx_desc; 928 929 /* init eth structure */ 930 dev->priv = priv; 931 dev->init = tse_eth_init; 932 dev->halt = tse_eth_halt; 933 dev->send = tse_eth_send; 934 dev->recv = tse_eth_rx; 935 dev->write_hwaddr = tse_set_mac_address; 936 sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num); 937 938 eth_register(dev); 939 940 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) 941 miiphy_register(dev->name, altera_tse_miiphy_read, 942 altera_tse_miiphy_write); 943 #endif 944 945 init_phy(dev); 946 947 return 1; 948 } 949