1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <flash.h> 26 #include <linux/err.h> 27 #include <linux/mtd/st_smi.h> 28 29 #include <asm/io.h> 30 #include <asm/arch/hardware.h> 31 32 #if !defined(CONFIG_SYS_NO_FLASH) 33 34 static struct smi_regs *const smicntl = 35 (struct smi_regs * const)CONFIG_SYS_SMI_BASE; 36 static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = 37 CONFIG_SYS_FLASH_ADDR_BASE; 38 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; 39 40 #define ST_M25Pxx_ID 0x00002020 41 42 static struct flash_dev flash_ids[] = { 43 {0x10, 0x10000, 2}, /* 64K Byte */ 44 {0x11, 0x20000, 4}, /* 128K Byte */ 45 {0x12, 0x40000, 4}, /* 256K Byte */ 46 {0x13, 0x80000, 8}, /* 512K Byte */ 47 {0x14, 0x100000, 16}, /* 1M Byte */ 48 {0x15, 0x200000, 32}, /* 2M Byte */ 49 {0x16, 0x400000, 64}, /* 4M Byte */ 50 {0x17, 0x800000, 128}, /* 8M Byte */ 51 {0x18, 0x1000000, 64}, /* 16M Byte */ 52 {0x00,} 53 }; 54 55 /* 56 * smi_wait_xfer_finish - Wait until TFF is set in status register 57 * @timeout: timeout in milliseconds 58 * 59 * Wait until TFF is set in status register 60 */ 61 static int smi_wait_xfer_finish(int timeout) 62 { 63 do { 64 if (readl(&smicntl->smi_sr) & TFF) 65 return 0; 66 udelay(1000); 67 } while (timeout--); 68 69 return -1; 70 } 71 72 /* 73 * smi_read_id - Read flash id 74 * @info: flash_info structure pointer 75 * @banknum: bank number 76 * 77 * Read the flash id present at bank #banknum 78 */ 79 static unsigned int smi_read_id(flash_info_t *info, int banknum) 80 { 81 unsigned int value; 82 83 writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); 84 writel(READ_ID, &smicntl->smi_tr); 85 writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, 86 &smicntl->smi_cr2); 87 88 if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) 89 return -EIO; 90 91 value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); 92 93 writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); 94 writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); 95 96 return value; 97 } 98 99 /* 100 * flash_get_size - Detect the SMI flash by reading the ID. 101 * @base: Base address of the flash area bank #banknum 102 * @banknum: Bank number 103 * 104 * Detect the SMI flash by reading the ID. Initializes the flash_info structure 105 * with size, sector count etc. 106 */ 107 static ulong flash_get_size(ulong base, int banknum) 108 { 109 flash_info_t *info = &flash_info[banknum]; 110 struct flash_dev *dev; 111 int value; 112 unsigned int density; 113 int i; 114 115 value = smi_read_id(info, banknum); 116 117 if (value < 0) { 118 printf("Flash id could not be read\n"); 119 return 0; 120 } 121 122 density = (value >> 16) & 0xff; 123 124 for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; 125 i++, dev = &flash_ids[i]) { 126 if (dev->density == density) { 127 info->size = dev->size; 128 info->sector_count = dev->sector_count; 129 break; 130 } 131 } 132 133 if (dev->density == 0x0) 134 return 0; 135 136 info->flash_id = value & 0xffff; 137 info->start[0] = base; 138 139 return info->size; 140 } 141 142 /* 143 * smi_read_sr - Read status register of SMI 144 * @bank: bank number 145 * 146 * This routine will get the status register of the flash chip present at the 147 * given bank 148 */ 149 static int smi_read_sr(int bank) 150 { 151 u32 ctrlreg1, val; 152 153 /* store the CTRL REG1 state */ 154 ctrlreg1 = readl(&smicntl->smi_cr1); 155 156 /* Program SMI in HW Mode */ 157 writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), 158 &smicntl->smi_cr1); 159 160 /* Performing a RSR instruction in HW mode */ 161 writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); 162 163 if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) 164 return -1; 165 166 val = readl(&smicntl->smi_sr); 167 168 /* Restore the CTRL REG1 state */ 169 writel(ctrlreg1, &smicntl->smi_cr1); 170 171 return val; 172 } 173 174 /* 175 * smi_wait_till_ready - Wait till last operation is over. 176 * @bank: bank number shifted. 177 * @timeout: timeout in milliseconds. 178 * 179 * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) 180 * The routine checks for #timeout loops, each at interval of 1 milli-second. 181 * If successful the routine returns 0. 182 */ 183 static int smi_wait_till_ready(int bank, int timeout) 184 { 185 int sr; 186 187 /* One chip guarantees max 5 msec wait here after page writes, 188 but potentially three seconds (!) after page erase. */ 189 do { 190 sr = smi_read_sr(bank); 191 if ((sr >= 0) && (!(sr & WIP_BIT))) 192 return 0; 193 194 /* Try again after 1m-sec */ 195 udelay(1000); 196 } while (timeout--); 197 198 printf("SMI controller is still in wait, timeout=%d\n", timeout); 199 return -EIO; 200 } 201 202 /* 203 * smi_write_enable - Enable the flash to do write operation 204 * @bank: bank number 205 * 206 * Set write enable latch with Write Enable command. 207 * Returns negative if error occurred. 208 */ 209 static int smi_write_enable(int bank) 210 { 211 u32 ctrlreg1; 212 int timeout = WMODE_TOUT; 213 int sr; 214 215 /* Store the CTRL REG1 state */ 216 ctrlreg1 = readl(&smicntl->smi_cr1); 217 218 /* Program SMI in H/W Mode */ 219 writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); 220 221 /* Give the Flash, Write Enable command */ 222 writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); 223 224 if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) 225 return -1; 226 227 /* Restore the CTRL REG1 state */ 228 writel(ctrlreg1, &smicntl->smi_cr1); 229 230 do { 231 sr = smi_read_sr(bank); 232 if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) 233 return 0; 234 235 /* Try again after 1m-sec */ 236 udelay(1000); 237 } while (timeout--); 238 239 return -1; 240 } 241 242 /* 243 * smi_init - SMI initialization routine 244 * 245 * SMI initialization routine. Sets SMI control register1. 246 */ 247 void smi_init(void) 248 { 249 /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ 250 writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, 251 &smicntl->smi_cr1); 252 } 253 254 /* 255 * smi_sector_erase - Erase flash sector 256 * @info: flash_info structure pointer 257 * @sector: sector number 258 * 259 * Set write enable latch with Write Enable command. 260 * Returns negative if error occurred. 261 */ 262 static int smi_sector_erase(flash_info_t *info, unsigned int sector) 263 { 264 int bank; 265 unsigned int sect_add; 266 unsigned int instruction; 267 268 switch (info->start[0]) { 269 case SMIBANK0_BASE: 270 bank = BANK0; 271 break; 272 case SMIBANK1_BASE: 273 bank = BANK1; 274 break; 275 case SMIBANK2_BASE: 276 bank = BANK2; 277 break; 278 case SMIBANK3_BASE: 279 bank = BANK3; 280 break; 281 default: 282 return -1; 283 } 284 285 sect_add = sector * (info->size / info->sector_count); 286 instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; 287 288 writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); 289 290 if (info->flash_id == ST_M25Pxx_ID) { 291 /* Wait until finished previous write command. */ 292 if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) 293 return -EBUSY; 294 295 /* Send write enable, before erase commands. */ 296 if (smi_write_enable(bank)) 297 return -EIO; 298 299 /* Put SMI in SW mode */ 300 writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); 301 302 /* Send Sector Erase command in SW Mode */ 303 writel(instruction, &smicntl->smi_tr); 304 writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, 305 &smicntl->smi_cr2); 306 if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) 307 return -EIO; 308 309 if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) 310 return -EBUSY; 311 312 /* Put SMI in HW mode */ 313 writel(readl(&smicntl->smi_cr1) & ~SW_MODE, 314 &smicntl->smi_cr1); 315 316 return 0; 317 } else { 318 /* Put SMI in HW mode */ 319 writel(readl(&smicntl->smi_cr1) & ~SW_MODE, 320 &smicntl->smi_cr1); 321 return -EINVAL; 322 } 323 } 324 325 /* 326 * smi_write - Write to SMI flash 327 * @src_addr: source buffer 328 * @dst_addr: destination buffer 329 * @length: length to write in words 330 * @bank: bank base address 331 * 332 * Write to SMI flash 333 */ 334 static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, 335 unsigned int length, ulong bank_addr) 336 { 337 int banknum; 338 339 switch (bank_addr) { 340 case SMIBANK0_BASE: 341 banknum = BANK0; 342 break; 343 case SMIBANK1_BASE: 344 banknum = BANK1; 345 break; 346 case SMIBANK2_BASE: 347 banknum = BANK2; 348 break; 349 case SMIBANK3_BASE: 350 banknum = BANK3; 351 break; 352 default: 353 return -1; 354 } 355 356 if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) 357 return -EBUSY; 358 359 /* Set SMI in Hardware Mode */ 360 writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); 361 362 if (smi_write_enable(banknum)) 363 return -EIO; 364 365 /* Perform the write command */ 366 while (length--) { 367 if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { 368 if (smi_wait_till_ready(banknum, 369 CONFIG_SYS_FLASH_WRITE_TOUT)) 370 return -EBUSY; 371 372 if (smi_write_enable(banknum)) 373 return -EIO; 374 } 375 376 *dst_addr++ = *src_addr++; 377 378 if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) 379 return -EIO; 380 } 381 382 if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) 383 return -EBUSY; 384 385 writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); 386 387 return 0; 388 } 389 390 /* 391 * write_buff - Write to SMI flash 392 * @info: flash info structure 393 * @src: source buffer 394 * @dest_addr: destination buffer 395 * @length: length to write in words 396 * 397 * Write to SMI flash 398 */ 399 int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) 400 { 401 return smi_write((unsigned int *)src, (unsigned int *)dest_addr, 402 (length + 3) / 4, info->start[0]); 403 } 404 405 /* 406 * flash_init - SMI flash initialization 407 * 408 * SMI flash initialization 409 */ 410 unsigned long flash_init(void) 411 { 412 unsigned long size = 0; 413 int i, j; 414 415 smi_init(); 416 417 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { 418 flash_info[i].flash_id = FLASH_UNKNOWN; 419 size += flash_info[i].size = flash_get_size(bank_base[i], i); 420 } 421 422 for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { 423 for (i = 1; i < flash_info[j].sector_count; i++) 424 flash_info[j].start[i] = 425 flash_info[j].start[i - 1] + 426 flash_info->size / flash_info->sector_count; 427 428 } 429 430 return size; 431 } 432 433 /* 434 * flash_print_info - Print SMI flash information 435 * 436 * Print SMI flash information 437 */ 438 void flash_print_info(flash_info_t *info) 439 { 440 int i; 441 if (info->flash_id == FLASH_UNKNOWN) { 442 puts("missing or unknown FLASH type\n"); 443 return; 444 } 445 printf(" Size: %ld MB in %d Sectors\n", 446 info->size >> 20, info->sector_count); 447 448 puts(" Sector Start Addresses:"); 449 for (i = 0; i < info->sector_count; ++i) { 450 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 451 int size; 452 int erased; 453 u32 *flash; 454 455 /* 456 * Check if whole sector is erased 457 */ 458 size = (info->size) / (info->sector_count); 459 flash = (u32 *) info->start[i]; 460 size = size / sizeof(int); 461 462 while ((size--) && (*flash++ == ~0)) 463 ; 464 465 size++; 466 if (size) 467 erased = 0; 468 else 469 erased = 1; 470 471 if ((i % 5) == 0) 472 printf("\n"); 473 474 printf(" %08lX%s%s", 475 info->start[i], 476 erased ? " E" : " ", info->protect[i] ? "RO " : " "); 477 #else 478 if ((i % 5) == 0) 479 printf("\n "); 480 printf(" %08lX%s", 481 info->start[i], info->protect[i] ? " (RO) " : " "); 482 #endif 483 } 484 putc('\n'); 485 return; 486 } 487 488 /* 489 * flash_erase - Erase SMI flash 490 * 491 * Erase SMI flash 492 */ 493 int flash_erase(flash_info_t *info, int s_first, int s_last) 494 { 495 int rcode = 0; 496 int prot = 0; 497 flash_sect_t sect; 498 499 if (info->flash_id != ST_M25Pxx_ID) { 500 puts("Can't erase unknown flash type - aborted\n"); 501 return 1; 502 } 503 504 if ((s_first < 0) || (s_first > s_last)) { 505 puts("- no sectors to erase\n"); 506 return 1; 507 } 508 509 for (sect = s_first; sect <= s_last; ++sect) { 510 if (info->protect[sect]) 511 prot++; 512 } 513 if (prot) { 514 printf("- Warning: %d protected sectors will not be erased!\n", 515 prot); 516 } else { 517 putc('\n'); 518 } 519 520 for (sect = s_first; sect <= s_last; sect++) { 521 if (info->protect[sect] == 0) { 522 if (smi_sector_erase(info, sect)) 523 rcode = 1; 524 else 525 putc('.'); 526 } 527 } 528 puts(" done\n"); 529 return rcode; 530 } 531 #endif 532