1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 7 */ 8 9 #include <common.h> 10 #include <spi.h> 11 #include <spi_flash.h> 12 13 #include "sf_internal.h" 14 15 /* Exclude chip names for SPL to save space */ 16 #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 17 #define INFO_NAME(_name) .name = _name, 18 #else 19 #define INFO_NAME(_name) 20 #endif 21 22 /* Used when the "_ext_id" is two bytes at most */ 23 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 24 INFO_NAME(_name) \ 25 .id = { \ 26 ((_jedec_id) >> 16) & 0xff, \ 27 ((_jedec_id) >> 8) & 0xff, \ 28 (_jedec_id) & 0xff, \ 29 ((_ext_id) >> 8) & 0xff, \ 30 (_ext_id) & 0xff, \ 31 }, \ 32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 33 .sector_size = (_sector_size), \ 34 .n_sectors = (_n_sectors), \ 35 .page_size = 256, \ 36 .flags = (_flags), 37 38 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 39 INFO_NAME(_name) \ 40 .id = { \ 41 ((_jedec_id) >> 16) & 0xff, \ 42 ((_jedec_id) >> 8) & 0xff, \ 43 (_jedec_id) & 0xff, \ 44 ((_ext_id) >> 16) & 0xff, \ 45 ((_ext_id) >> 8) & 0xff, \ 46 (_ext_id) & 0xff, \ 47 }, \ 48 .id_len = 6, \ 49 .sector_size = (_sector_size), \ 50 .n_sectors = (_n_sectors), \ 51 .page_size = 256, \ 52 .flags = (_flags), 53 54 /* NOTE: double check command sets and memory organization when you add 55 * more nor chips. This current list focusses on newer chips, which 56 * have been converging on command sets which including JEDEC ID. 57 * 58 * All newly added entries should describe *hardware* and should use SECT_4K 59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 60 * scenarios excluding small sectors there is config option that can be 61 * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. 62 * For historical (and compatibility) reasons (before we got above config) some 63 * old entries may be missing 4K flag. 64 */ 65 const struct flash_info spi_nor_ids[] = { 66 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 70 71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 78 { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, 79 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 80 #endif 81 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 82 /* EON -- en25xxx */ 83 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, 84 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 85 { INFO("en25qh64", 0x1c7017, 0, 64 * 1024, 128, SECT_4K) }, 86 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K) }, 87 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 88 { INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 89 { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 90 #endif 91 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 92 /* GigaDevice */ 93 { 94 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, 95 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 96 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 97 }, 98 { 99 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, 100 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 101 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 102 }, 103 { 104 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, 105 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 106 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 107 }, 108 { 109 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, 110 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 111 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 112 }, 113 { 114 INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128, 115 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 116 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 117 }, 118 { 119 INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, 120 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 121 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 122 }, 123 { 124 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, 125 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 126 SPI_NOR_HAS_TB) 127 }, 128 { INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512, 129 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 130 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 131 SPI_NOR_HAS_TB) 132 }, 133 { INFO("gd25q512", 0xc84020, 0, 64 * 1024, 1024, 134 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 135 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 136 SPI_NOR_HAS_TB) 137 }, 138 { 139 INFO("gd25lq255", 0xc86019, 0, 64 * 1024, 512, 140 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 141 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 142 }, 143 { 144 INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024, 145 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 146 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 147 }, 148 { 149 INFO("gd25b512m", 0xc8471a, 0, 64 * 1024, 1024, 150 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 151 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 152 }, 153 { 154 INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048, 155 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 156 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 157 }, 158 #endif 159 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 160 /* ISSI */ 161 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, 162 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 163 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, 164 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, 165 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, 166 SECT_4K | SPI_NOR_DUAL_READ) }, 167 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, 168 SECT_4K | SPI_NOR_DUAL_READ) }, 169 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, 170 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 171 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, 172 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 173 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, 174 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 175 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, 176 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 177 SPI_NOR_4B_OPCODES) }, 178 #endif 179 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 180 /* Macronix */ 181 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 182 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 183 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, 184 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 185 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 186 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 187 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 188 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 189 { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, 190 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 191 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 192 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 193 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, 194 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 195 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 196 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, 197 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 198 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 199 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 200 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 201 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 202 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, 203 { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 204 #endif 205 206 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 207 /* Micron */ 208 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 209 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 210 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 211 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 212 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 213 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 214 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 215 { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 216 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, 217 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 218 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, 219 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, 220 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 221 USE_FSR) }, 222 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 223 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 224 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 225 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 226 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 227 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 228 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 229 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 230 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 231 #endif 232 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 233 /* Spansion/Cypress -- single (large) sector size only, at least 234 * for the chips listed here (without boot sectors). 235 */ 236 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 237 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 238 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 239 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 240 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 241 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 242 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 243 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 244 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 245 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, 246 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, 247 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 248 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 249 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 250 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, 251 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, 252 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, 253 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, 254 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 255 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, 256 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 257 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 258 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 259 #endif 260 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 261 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 262 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 263 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 264 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 265 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 266 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 267 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 268 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 269 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 270 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, 271 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, 272 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 273 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 274 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 275 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 276 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 277 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 278 #endif 279 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 280 /* ST Microelectronics -- newer production may have feature updates */ 281 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, 282 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, 283 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, 284 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, 285 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, 286 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, 287 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, 288 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, 289 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, 290 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 291 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, 292 #endif 293 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 294 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 295 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, 296 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, 297 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, 298 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 299 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 300 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 301 { 302 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 303 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 304 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 305 }, 306 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 307 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 308 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 309 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 310 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 311 { 312 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, 313 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 314 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 315 }, 316 { 317 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, 318 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 319 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 320 }, 321 { 322 INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, 323 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 324 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 325 }, 326 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 327 { 328 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, 329 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 330 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 331 }, 332 { 333 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, 334 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 335 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 336 }, 337 { 338 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, 339 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 340 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 341 }, 342 { 343 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, 344 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 345 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 346 }, 347 { 348 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, 349 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 350 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 351 }, 352 { 353 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, 354 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 355 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 356 }, 357 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 358 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 359 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 360 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 361 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, 362 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 363 SPI_NOR_HAS_TB) 364 }, 365 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 366 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 367 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 368 #endif 369 #ifdef CONFIG_SPI_FLASH_XMC 370 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 371 { INFO("XM25QH32A", 0x207016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 372 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 373 { INFO("XM25QH64B", 0x206017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 374 { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 375 { INFO("XM25QU64C", 0x204117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 376 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 377 { INFO("XM25QH128B", 0x206018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 378 { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 379 { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 380 { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 381 #endif 382 #ifdef CONFIG_SPI_FLASH_XTX 383 /* XTX Technology (Shenzhen) Limited */ 384 { INFO("xt25f64f", 0x0b4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 385 { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 386 { INFO("xt25f256b", 0x0b4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 387 { INFO("xt25q64d", 0x0b6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 388 { INFO("xt25q128d", 0x0b6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 389 #endif 390 #ifdef CONFIG_SPI_FLASH_PUYA 391 /* PUYA Semiconductor (Shanghai) Co., Ltd. */ 392 { INFO("P25Q64H", 0x856017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 393 { INFO("P25Q128H", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 394 { INFO("PY25Q64HA", 0x852017, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 395 { INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 396 { INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 397 #endif 398 #ifdef CONFIG_SPI_FLASH_FMSH 399 /* FUDAN MICRO (Shanghai) Co., Ltd. */ 400 { INFO("FM25Q128A", 0xA14018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 401 { INFO("FM25Q64", 0xA14017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 402 #endif 403 #ifdef CONFIG_SPI_FLASH_DOSILICON 404 /* Dosilicon Co., Ltd. */ 405 { INFO("FM25Q64A", 0xf83217, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 406 { INFO("FM25M4AA", 0xf84218, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 407 { INFO("FM25M64C", 0xf84317, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 408 #endif 409 #ifdef CONFIG_SPI_FLASH_BOYA 410 /* Boya Microelectronics Co., Ltd. */ 411 { INFO("BY25Q256FSEIG", 0x684919, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 412 #endif 413 #ifdef CONFIG_SPI_FLASH_NORMEM 414 /* NORMEM Microelectronics Co., Ltd. */ 415 { INFO("NM25Q128EVB", 0x522118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 416 #endif 417 { }, 418 }; 419