1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 7 */ 8 9 #include <common.h> 10 #include <spi.h> 11 #include <spi_flash.h> 12 13 #include "sf_internal.h" 14 15 /* Exclude chip names for SPL to save space */ 16 #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 17 #define INFO_NAME(_name) .name = _name, 18 #else 19 #define INFO_NAME(_name) 20 #endif 21 22 /* Used when the "_ext_id" is two bytes at most */ 23 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 24 INFO_NAME(_name) \ 25 .id = { \ 26 ((_jedec_id) >> 16) & 0xff, \ 27 ((_jedec_id) >> 8) & 0xff, \ 28 (_jedec_id) & 0xff, \ 29 ((_ext_id) >> 8) & 0xff, \ 30 (_ext_id) & 0xff, \ 31 }, \ 32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 33 .sector_size = (_sector_size), \ 34 .n_sectors = (_n_sectors), \ 35 .page_size = 256, \ 36 .flags = (_flags), 37 38 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 39 INFO_NAME(_name) \ 40 .id = { \ 41 ((_jedec_id) >> 16) & 0xff, \ 42 ((_jedec_id) >> 8) & 0xff, \ 43 (_jedec_id) & 0xff, \ 44 ((_ext_id) >> 16) & 0xff, \ 45 ((_ext_id) >> 8) & 0xff, \ 46 (_ext_id) & 0xff, \ 47 }, \ 48 .id_len = 6, \ 49 .sector_size = (_sector_size), \ 50 .n_sectors = (_n_sectors), \ 51 .page_size = 256, \ 52 .flags = (_flags), 53 54 /* NOTE: double check command sets and memory organization when you add 55 * more nor chips. This current list focusses on newer chips, which 56 * have been converging on command sets which including JEDEC ID. 57 * 58 * All newly added entries should describe *hardware* and should use SECT_4K 59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 60 * scenarios excluding small sectors there is config option that can be 61 * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. 62 * For historical (and compatibility) reasons (before we got above config) some 63 * old entries may be missing 4K flag. 64 */ 65 const struct flash_info spi_nor_ids[] = { 66 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 70 71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 78 { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, 79 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 80 #endif 81 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 82 /* EON -- en25xxx */ 83 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, 84 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 85 { INFO("en25qh64", 0x1c7017, 0, 64 * 1024, 128, SECT_4K) }, 86 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K) }, 87 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 88 { INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 89 { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 90 { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 91 #endif 92 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 93 /* GigaDevice */ 94 { 95 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, 96 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 97 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 98 }, 99 { 100 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, 101 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 102 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 103 }, 104 { 105 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, 106 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 107 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 108 }, 109 { 110 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, 111 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 112 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 113 }, 114 { 115 INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128, 116 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 117 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 118 }, 119 { 120 INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, 121 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 122 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 123 }, 124 { 125 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, 126 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 127 SPI_NOR_HAS_TB) 128 }, 129 { INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512, 130 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 131 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 132 SPI_NOR_HAS_TB) 133 }, 134 { INFO("gd25q512", 0xc84020, 0, 64 * 1024, 1024, 135 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 136 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | 137 SPI_NOR_HAS_TB) 138 }, 139 { 140 INFO("gd25lq255", 0xc86019, 0, 64 * 1024, 512, 141 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 142 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 143 }, 144 { 145 INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024, 146 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 147 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 148 }, 149 { 150 INFO("gd55lb01ge", 0xc8671b, 0, 64 * 1024, 2048, 151 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 152 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 153 }, 154 { 155 INFO("gd25b512m", 0xc8471a, 0, 64 * 1024, 1024, 156 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 157 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 158 }, 159 { 160 INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048, 161 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 162 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) 163 }, 164 #endif 165 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 166 /* ISSI */ 167 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, 168 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 169 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, 170 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, 171 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, 172 SECT_4K | SPI_NOR_DUAL_READ) }, 173 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, 174 SECT_4K | SPI_NOR_DUAL_READ) }, 175 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, 176 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 177 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, 178 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 179 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, 180 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 181 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, 182 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 183 SPI_NOR_4B_OPCODES) }, 184 #endif 185 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 186 /* Macronix */ 187 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 188 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 189 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, 190 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 191 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 192 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 193 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 194 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 195 { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, 196 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 197 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 198 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 199 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, 200 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 201 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 202 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, 203 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 204 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 205 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 206 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 207 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 208 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, 209 { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 210 #endif 211 212 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 213 /* Micron */ 214 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 215 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 216 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 217 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 218 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 219 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 220 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 221 { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 222 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, 223 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 224 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, 225 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, 226 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 227 USE_FSR) }, 228 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 229 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 230 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 231 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 232 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 233 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 234 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 235 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 236 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 237 #endif 238 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 239 /* Spansion/Cypress -- single (large) sector size only, at least 240 * for the chips listed here (without boot sectors). 241 */ 242 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 243 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 244 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 245 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 246 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 247 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 248 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 249 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 250 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 251 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, 252 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, 253 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 254 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 255 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 256 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, 257 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, 258 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, 259 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, 260 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 261 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, 262 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 263 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 264 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 265 #endif 266 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 267 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 268 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 269 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 270 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 271 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 272 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 273 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 274 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 275 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 276 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, 277 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, 278 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 279 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 280 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 281 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 282 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 283 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 284 #endif 285 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 286 /* ST Microelectronics -- newer production may have feature updates */ 287 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, 288 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, 289 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, 290 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, 291 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, 292 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, 293 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, 294 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, 295 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, 296 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 297 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, 298 #endif 299 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 300 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 301 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, 302 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, 303 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, 304 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 305 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 306 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 307 { 308 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 309 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 310 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 311 }, 312 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 313 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 314 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 315 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 316 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 317 { 318 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, 319 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 320 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 321 }, 322 { 323 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, 324 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 325 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 326 }, 327 { 328 INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, 329 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 330 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 331 }, 332 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 333 { 334 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, 335 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 336 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 337 }, 338 { 339 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, 340 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 341 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 342 }, 343 { 344 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, 345 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 346 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 347 }, 348 { 349 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, 350 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 351 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 352 }, 353 { 354 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, 355 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 356 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 357 }, 358 { 359 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, 360 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 361 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 362 }, 363 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 364 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 365 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 366 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 367 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, 368 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 369 SPI_NOR_HAS_TB) 370 }, 371 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 372 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 373 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 374 #endif 375 #ifdef CONFIG_SPI_FLASH_XMC 376 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 377 { INFO("XM25QH32A", 0x207016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 378 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 379 { INFO("XM25QH64B", 0x206017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 380 { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 381 { INFO("XM25QU64C", 0x204117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 382 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 383 { INFO("XM25QH128B", 0x206018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 384 { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 385 { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 386 { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 387 #endif 388 #ifdef CONFIG_SPI_FLASH_XTX 389 /* XTX Technology (Shenzhen) Limited */ 390 { INFO("xt25f64f", 0x0b4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 391 { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 392 { INFO("xt25f256b", 0x0b4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 393 { INFO("xt25q64d", 0x0b6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 394 { INFO("xt25q128d", 0x0b6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 395 #endif 396 #ifdef CONFIG_SPI_FLASH_PUYA 397 /* PUYA Semiconductor (Shanghai) Co., Ltd. */ 398 { INFO("P25Q64H", 0x856017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 399 { INFO("P25Q128H", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 400 { INFO("PY25Q64HA", 0x852017, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 401 { INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 402 { INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 403 #endif 404 #ifdef CONFIG_SPI_FLASH_FMSH 405 /* FUDAN MICRO (Shanghai) Co., Ltd. */ 406 { INFO("FM25Q128A", 0xA14018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 407 { INFO("FM25Q64", 0xA14017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 408 { INFO("FM25Q256I3", 0xA14019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 409 #endif 410 #ifdef CONFIG_SPI_FLASH_DOSILICON 411 /* Dosilicon Co., Ltd. */ 412 { INFO("FM25Q64A", 0xf83217, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 413 { INFO("FM25M4AA", 0xf84218, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 414 { INFO("FM25M64C", 0xf84317, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 415 #endif 416 #ifdef CONFIG_SPI_FLASH_BOYA 417 /* Boya Microelectronics Co., Ltd. */ 418 { INFO("BY25Q256FSEIG", 0x684919, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 419 #endif 420 #ifdef CONFIG_SPI_FLASH_NORMEM 421 /* NORMEM Microelectronics Co., Ltd. */ 422 { INFO("NM25Q128EVB", 0x522118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 423 #endif 424 { }, 425 }; 426