1 /* 2 * Atmel DataFlash probing 3 * 4 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc. 5 * Haikun Wang (haikun.wang@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <fdtdec.h> 14 #include <spi.h> 15 #include <spi_flash.h> 16 #include <div64.h> 17 #include <linux/err.h> 18 #include <linux/math64.h> 19 20 #include "sf_internal.h" 21 22 #define CMD_READ_ID 0x9f 23 /* reads can bypass the buffers */ 24 #define OP_READ_CONTINUOUS 0xE8 25 #define OP_READ_PAGE 0xD2 26 27 /* group B requests can run even while status reports "busy" */ 28 #define OP_READ_STATUS 0xD7 /* group B */ 29 30 /* move data between host and buffer */ 31 #define OP_READ_BUFFER1 0xD4 /* group B */ 32 #define OP_READ_BUFFER2 0xD6 /* group B */ 33 #define OP_WRITE_BUFFER1 0x84 /* group B */ 34 #define OP_WRITE_BUFFER2 0x87 /* group B */ 35 36 /* erasing flash */ 37 #define OP_ERASE_PAGE 0x81 38 #define OP_ERASE_BLOCK 0x50 39 40 /* move data between buffer and flash */ 41 #define OP_TRANSFER_BUF1 0x53 42 #define OP_TRANSFER_BUF2 0x55 43 #define OP_MREAD_BUFFER1 0xD4 44 #define OP_MREAD_BUFFER2 0xD6 45 #define OP_MWERASE_BUFFER1 0x83 46 #define OP_MWERASE_BUFFER2 0x86 47 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */ 48 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */ 49 50 /* write to buffer, then write-erase to flash */ 51 #define OP_PROGRAM_VIA_BUF1 0x82 52 #define OP_PROGRAM_VIA_BUF2 0x85 53 54 /* compare buffer to flash */ 55 #define OP_COMPARE_BUF1 0x60 56 #define OP_COMPARE_BUF2 0x61 57 58 /* read flash to buffer, then write-erase to flash */ 59 #define OP_REWRITE_VIA_BUF1 0x58 60 #define OP_REWRITE_VIA_BUF2 0x59 61 62 /* 63 * newer chips report JEDEC manufacturer and device IDs; chip 64 * serial number and OTP bits; and per-sector writeprotect. 65 */ 66 #define OP_READ_ID 0x9F 67 #define OP_READ_SECURITY 0x77 68 #define OP_WRITE_SECURITY_REVC 0x9A 69 #define OP_WRITE_SECURITY 0x9B /* revision D */ 70 71 struct dataflash { 72 uint8_t command[16]; 73 unsigned short page_offset; /* offset in flash address */ 74 }; 75 76 /* Return the status of the DataFlash device */ 77 static inline int dataflash_status(struct spi_slave *spi) 78 { 79 int ret; 80 u8 status; 81 /* 82 * NOTE: at45db321c over 25 MHz wants to write 83 * a dummy byte after the opcode... 84 */ 85 ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1); 86 return ret ? -EIO : status; 87 } 88 89 /* 90 * Poll the DataFlash device until it is READY. 91 * This usually takes 5-20 msec or so; more for sector erase. 92 * ready: return > 0 93 */ 94 static int dataflash_waitready(struct spi_slave *spi) 95 { 96 int status; 97 int timeout = 2 * CONFIG_SYS_HZ; 98 int timebase; 99 100 timebase = get_timer(0); 101 do { 102 status = dataflash_status(spi); 103 if (status < 0) 104 status = 0; 105 106 if (status & (1 << 7)) /* RDY/nBSY */ 107 return status; 108 109 mdelay(3); 110 } while (get_timer(timebase) < timeout); 111 112 return -ETIME; 113 } 114 115 /* Erase pages of flash */ 116 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len) 117 { 118 struct dataflash *dataflash; 119 struct spi_flash *spi_flash; 120 struct spi_slave *spi; 121 unsigned blocksize; 122 uint8_t *command; 123 uint32_t rem; 124 int status; 125 126 dataflash = dev_get_priv(dev); 127 spi_flash = dev_get_uclass_priv(dev); 128 spi = spi_flash->spi; 129 130 blocksize = spi_flash->page_size << 3; 131 132 memset(dataflash->command, 0 , sizeof(dataflash->command)); 133 command = dataflash->command; 134 135 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len); 136 137 div_u64_rem(len, spi_flash->page_size, &rem); 138 if (rem) { 139 printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n", 140 dev->name, len, spi_flash->page_size); 141 return -EINVAL; 142 } 143 div_u64_rem(offset, spi_flash->page_size, &rem); 144 if (rem) { 145 printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n", 146 dev->name, offset, spi_flash->page_size); 147 return -EINVAL; 148 } 149 150 status = spi_claim_bus(spi); 151 if (status) { 152 debug("dataflash: unable to claim SPI bus\n"); 153 return status; 154 } 155 156 while (len > 0) { 157 unsigned int pageaddr; 158 int do_block; 159 /* 160 * Calculate flash page address; use block erase (for speed) if 161 * we're at a block boundary and need to erase the whole block. 162 */ 163 pageaddr = div_u64(offset, spi_flash->page_size); 164 do_block = (pageaddr & 0x7) == 0 && len >= blocksize; 165 pageaddr = pageaddr << dataflash->page_offset; 166 167 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE; 168 command[1] = (uint8_t)(pageaddr >> 16); 169 command[2] = (uint8_t)(pageaddr >> 8); 170 command[3] = 0; 171 172 debug("%s ERASE %s: (%x) %x %x %x [%d]\n", 173 dev->name, do_block ? "block" : "page", 174 command[0], command[1], command[2], command[3], 175 pageaddr); 176 177 status = spi_flash_cmd_write(spi, command, 4, NULL, 0); 178 if (status < 0) { 179 debug("%s: erase send command error!\n", dev->name); 180 return -EIO; 181 } 182 183 status = dataflash_waitready(spi); 184 if (status < 0) { 185 debug("%s: erase waitready error!\n", dev->name); 186 return status; 187 } 188 189 if (do_block) { 190 offset += blocksize; 191 len -= blocksize; 192 } else { 193 offset += spi_flash->page_size; 194 len -= spi_flash->page_size; 195 } 196 } 197 198 spi_release_bus(spi); 199 200 return 0; 201 } 202 203 /* 204 * Read from the DataFlash device. 205 * offset : Start offset in flash device 206 * len : Amount to read 207 * buf : Buffer containing the data 208 */ 209 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len, 210 void *buf) 211 { 212 struct dataflash *dataflash; 213 struct spi_flash *spi_flash; 214 struct spi_slave *spi; 215 unsigned int addr; 216 uint8_t *command; 217 int status; 218 219 dataflash = dev_get_priv(dev); 220 spi_flash = dev_get_uclass_priv(dev); 221 spi = spi_flash->spi; 222 223 memset(dataflash->command, 0 , sizeof(dataflash->command)); 224 command = dataflash->command; 225 226 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len); 227 debug("READ: (%x) %x %x %x\n", 228 command[0], command[1], command[2], command[3]); 229 230 /* Calculate flash page/byte address */ 231 addr = (((unsigned)offset / spi_flash->page_size) 232 << dataflash->page_offset) 233 + ((unsigned)offset % spi_flash->page_size); 234 235 status = spi_claim_bus(spi); 236 if (status) { 237 debug("dataflash: unable to claim SPI bus\n"); 238 return status; 239 } 240 241 /* 242 * Continuous read, max clock = f(car) which may be less than 243 * the peak rate available. Some chips support commands with 244 * fewer "don't care" bytes. Both buffers stay unchanged. 245 */ 246 command[0] = OP_READ_CONTINUOUS; 247 command[1] = (uint8_t)(addr >> 16); 248 command[2] = (uint8_t)(addr >> 8); 249 command[3] = (uint8_t)(addr >> 0); 250 251 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */ 252 status = spi_flash_cmd_read(spi, command, 8, buf, len); 253 254 spi_release_bus(spi); 255 256 return status; 257 } 258 259 /* 260 * Write to the DataFlash device. 261 * offset : Start offset in flash device 262 * len : Amount to write 263 * buf : Buffer containing the data 264 */ 265 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len, 266 const void *buf) 267 { 268 struct dataflash *dataflash; 269 struct spi_flash *spi_flash; 270 struct spi_slave *spi; 271 uint8_t *command; 272 unsigned int pageaddr, addr, to, writelen; 273 size_t remaining = len; 274 u_char *writebuf = (u_char *)buf; 275 int status = -EINVAL; 276 277 dataflash = dev_get_priv(dev); 278 spi_flash = dev_get_uclass_priv(dev); 279 spi = spi_flash->spi; 280 281 memset(dataflash->command, 0 , sizeof(dataflash->command)); 282 command = dataflash->command; 283 284 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len)); 285 286 pageaddr = ((unsigned)offset / spi_flash->page_size); 287 to = ((unsigned)offset % spi_flash->page_size); 288 if (to + len > spi_flash->page_size) 289 writelen = spi_flash->page_size - to; 290 else 291 writelen = len; 292 293 status = spi_claim_bus(spi); 294 if (status) { 295 debug("dataflash: unable to claim SPI bus\n"); 296 return status; 297 } 298 299 while (remaining > 0) { 300 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen); 301 302 /* 303 * REVISIT: 304 * (a) each page in a sector must be rewritten at least 305 * once every 10K sibling erase/program operations. 306 * (b) for pages that are already erased, we could 307 * use WRITE+MWRITE not PROGRAM for ~30% speedup. 308 * (c) WRITE to buffer could be done while waiting for 309 * a previous MWRITE/MWERASE to complete ... 310 * (d) error handling here seems to be mostly missing. 311 * 312 * Two persistent bits per page, plus a per-sector counter, 313 * could support (a) and (b) ... we might consider using 314 * the second half of sector zero, which is just one block, 315 * to track that state. (On AT91, that sector should also 316 * support boot-from-DataFlash.) 317 */ 318 319 addr = pageaddr << dataflash->page_offset; 320 321 /* (1) Maybe transfer partial page to Buffer1 */ 322 if (writelen != spi_flash->page_size) { 323 command[0] = OP_TRANSFER_BUF1; 324 command[1] = (addr & 0x00FF0000) >> 16; 325 command[2] = (addr & 0x0000FF00) >> 8; 326 command[3] = 0; 327 328 debug("TRANSFER: (%x) %x %x %x\n", 329 command[0], command[1], command[2], command[3]); 330 331 status = spi_flash_cmd_write(spi, command, 4, NULL, 0); 332 if (status < 0) { 333 debug("%s: write(<pagesize) command error!\n", 334 dev->name); 335 return -EIO; 336 } 337 338 status = dataflash_waitready(spi); 339 if (status < 0) { 340 debug("%s: write(<pagesize) waitready error!\n", 341 dev->name); 342 return status; 343 } 344 } 345 346 /* (2) Program full page via Buffer1 */ 347 addr += to; 348 command[0] = OP_PROGRAM_VIA_BUF1; 349 command[1] = (addr & 0x00FF0000) >> 16; 350 command[2] = (addr & 0x0000FF00) >> 8; 351 command[3] = (addr & 0x000000FF); 352 353 debug("PROGRAM: (%x) %x %x %x\n", 354 command[0], command[1], command[2], command[3]); 355 356 status = spi_flash_cmd_write(spi, command, 357 4, writebuf, writelen); 358 if (status < 0) { 359 debug("%s: write send command error!\n", dev->name); 360 return -EIO; 361 } 362 363 status = dataflash_waitready(spi); 364 if (status < 0) { 365 debug("%s: write waitready error!\n", dev->name); 366 return status; 367 } 368 369 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY 370 /* (3) Compare to Buffer1 */ 371 addr = pageaddr << dataflash->page_offset; 372 command[0] = OP_COMPARE_BUF1; 373 command[1] = (addr & 0x00FF0000) >> 16; 374 command[2] = (addr & 0x0000FF00) >> 8; 375 command[3] = 0; 376 377 debug("COMPARE: (%x) %x %x %x\n", 378 command[0], command[1], command[2], command[3]); 379 380 status = spi_flash_cmd_write(spi, command, 381 4, writebuf, writelen); 382 if (status < 0) { 383 debug("%s: write(compare) send command error!\n", 384 dev->name); 385 return -EIO; 386 } 387 388 status = dataflash_waitready(spi); 389 390 /* Check result of the compare operation */ 391 if (status & (1 << 6)) { 392 printf("dataflash: write compare page %u, err %d\n", 393 pageaddr, status); 394 remaining = 0; 395 status = -EIO; 396 break; 397 } else { 398 status = 0; 399 } 400 401 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */ 402 remaining = remaining - writelen; 403 pageaddr++; 404 to = 0; 405 writebuf += writelen; 406 407 if (remaining > spi_flash->page_size) 408 writelen = spi_flash->page_size; 409 else 410 writelen = remaining; 411 } 412 413 spi_release_bus(spi); 414 415 return 0; 416 } 417 418 static int add_dataflash(struct udevice *dev, char *name, int nr_pages, 419 int pagesize, int pageoffset, char revision) 420 { 421 struct spi_flash *spi_flash; 422 struct dataflash *dataflash; 423 424 dataflash = dev_get_priv(dev); 425 spi_flash = dev_get_uclass_priv(dev); 426 427 dataflash->page_offset = pageoffset; 428 429 spi_flash->name = name; 430 spi_flash->page_size = pagesize; 431 spi_flash->size = nr_pages * pagesize; 432 spi_flash->erase_size = pagesize; 433 434 #ifndef CONFIG_SPL_BUILD 435 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name); 436 print_size(spi_flash->page_size, ", erase size "); 437 print_size(spi_flash->erase_size, ", total "); 438 print_size(spi_flash->size, ""); 439 printf(", revision %c", revision); 440 puts("\n"); 441 #endif 442 443 return 0; 444 } 445 446 struct data_flash_info { 447 char *name; 448 449 /* 450 * JEDEC id has a high byte of zero plus three data bytes: 451 * the manufacturer id, then a two byte device id. 452 */ 453 uint32_t jedec_id; 454 455 /* The size listed here is what works with OP_ERASE_PAGE. */ 456 unsigned nr_pages; 457 uint16_t pagesize; 458 uint16_t pageoffset; 459 460 uint16_t flags; 461 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */ 462 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */ 463 }; 464 465 static struct data_flash_info dataflash_data[] = { 466 /* 467 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries, 468 * one with IS_POW2PS and the other without. The entry with the 469 * non-2^N byte page size can't name exact chip revisions without 470 * losing backwards compatibility for cmdlinepart. 471 * 472 * Those two entries have different name spelling format in order to 473 * show their difference obviously. 474 * The upper case refer to the chip isn't in normal 2^N bytes page-size 475 * mode. 476 * The lower case refer to the chip is in normal 2^N bytes page-size 477 * mode. 478 * 479 * These newer chips also support 128-byte security registers (with 480 * 64 bytes one-time-programmable) and software write-protection. 481 */ 482 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS}, 483 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS}, 484 485 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS}, 486 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS}, 487 488 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS}, 489 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS}, 490 491 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS}, 492 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS}, 493 494 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS}, 495 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS}, 496 497 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */ 498 499 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS}, 500 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS}, 501 502 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS}, 503 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS}, 504 }; 505 506 static struct data_flash_info *jedec_probe(struct spi_slave *spi) 507 { 508 int tmp; 509 uint8_t id[5]; 510 uint32_t jedec; 511 struct data_flash_info *info; 512 int status; 513 514 /* 515 * JEDEC also defines an optional "extended device information" 516 * string for after vendor-specific data, after the three bytes 517 * we use here. Supporting some chips might require using it. 518 * 519 * If the vendor ID isn't Atmel's (0x1f), assume this call failed. 520 * That's not an error; only rev C and newer chips handle it, and 521 * only Atmel sells these chips. 522 */ 523 tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id)); 524 if (tmp < 0) { 525 printf("dataflash: error %d reading JEDEC ID\n", tmp); 526 return ERR_PTR(tmp); 527 } 528 if (id[0] != 0x1f) 529 return NULL; 530 531 jedec = id[0]; 532 jedec = jedec << 8; 533 jedec |= id[1]; 534 jedec = jedec << 8; 535 jedec |= id[2]; 536 537 for (tmp = 0, info = dataflash_data; 538 tmp < ARRAY_SIZE(dataflash_data); 539 tmp++, info++) { 540 if (info->jedec_id == jedec) { 541 if (info->flags & SUP_POW2PS) { 542 status = dataflash_status(spi); 543 if (status < 0) { 544 debug("dataflash: status error %d\n", 545 status); 546 return NULL; 547 } 548 if (status & 0x1) { 549 if (info->flags & IS_POW2PS) 550 return info; 551 } else { 552 if (!(info->flags & IS_POW2PS)) 553 return info; 554 } 555 } else { 556 return info; 557 } 558 } 559 } 560 561 /* 562 * Treat other chips as errors ... we won't know the right page 563 * size (it might be binary) even when we can tell which density 564 * class is involved (legacy chip id scheme). 565 */ 566 printf("dataflash: JEDEC id %06x not handled\n", jedec); 567 return ERR_PTR(-ENODEV); 568 } 569 570 /* 571 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips 572 * or else the ID code embedded in the status bits: 573 * 574 * Device Density ID code #Pages PageSize Offset 575 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 576 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9 577 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 578 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 579 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 580 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 581 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11 582 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 583 */ 584 static int spi_dataflash_probe(struct udevice *dev) 585 { 586 struct spi_slave *spi = dev_get_parent_priv(dev); 587 struct spi_flash *spi_flash; 588 struct data_flash_info *info; 589 int status; 590 591 spi_flash = dev_get_uclass_priv(dev); 592 spi_flash->spi = spi; 593 spi_flash->dev = dev; 594 595 status = spi_claim_bus(spi); 596 if (status) 597 return status; 598 599 /* 600 * Try to detect dataflash by JEDEC ID. 601 * If it succeeds we know we have either a C or D part. 602 * D will support power of 2 pagesize option. 603 * Both support the security register, though with different 604 * write procedures. 605 */ 606 info = jedec_probe(spi); 607 if (IS_ERR(info)) 608 goto err_jedec_probe; 609 if (info != NULL) { 610 status = add_dataflash(dev, info->name, info->nr_pages, 611 info->pagesize, info->pageoffset, 612 (info->flags & SUP_POW2PS) ? 'd' : 'c'); 613 if (status < 0) 614 goto err_status; 615 } 616 617 /* 618 * Older chips support only legacy commands, identifing 619 * capacity using bits in the status byte. 620 */ 621 status = dataflash_status(spi); 622 if (status <= 0 || status == 0xff) { 623 printf("dataflash: read status error %d\n", status); 624 if (status == 0 || status == 0xff) 625 status = -ENODEV; 626 goto err_jedec_probe; 627 } 628 629 /* 630 * if there's a device there, assume it's dataflash. 631 * board setup should have set spi->max_speed_max to 632 * match f(car) for continuous reads, mode 0 or 3. 633 */ 634 switch (status & 0x3c) { 635 case 0x0c: /* 0 0 1 1 x x */ 636 status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0); 637 break; 638 case 0x14: /* 0 1 0 1 x x */ 639 status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0); 640 break; 641 case 0x1c: /* 0 1 1 1 x x */ 642 status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0); 643 break; 644 case 0x24: /* 1 0 0 1 x x */ 645 status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0); 646 break; 647 case 0x2c: /* 1 0 1 1 x x */ 648 status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0); 649 break; 650 case 0x34: /* 1 1 0 1 x x */ 651 status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0); 652 break; 653 case 0x38: /* 1 1 1 x x x */ 654 case 0x3c: 655 status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0); 656 break; 657 /* obsolete AT45DB1282 not (yet?) supported */ 658 default: 659 printf("dataflash: unsupported device (%x)\n", status & 0x3c); 660 status = -ENODEV; 661 goto err_status; 662 } 663 664 return status; 665 666 err_status: 667 spi_free_slave(spi); 668 err_jedec_probe: 669 spi_release_bus(spi); 670 return status; 671 } 672 673 static const struct dm_spi_flash_ops spi_dataflash_ops = { 674 .read = spi_dataflash_read, 675 .write = spi_dataflash_write, 676 .erase = spi_dataflash_erase, 677 }; 678 679 static const struct udevice_id spi_dataflash_ids[] = { 680 { .compatible = "atmel,at45", }, 681 { .compatible = "atmel,dataflash", }, 682 { } 683 }; 684 685 U_BOOT_DRIVER(spi_dataflash) = { 686 .name = "spi_dataflash", 687 .id = UCLASS_SPI_FLASH, 688 .of_match = spi_dataflash_ids, 689 .probe = spi_dataflash_probe, 690 .priv_auto_alloc_size = sizeof(struct dataflash), 691 .ops = &spi_dataflash_ops, 692 }; 693