1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #define pr_fmt(fmt) "spi-nand: " fmt 11 12 #ifndef __UBOOT__ 13 #include <linux/device.h> 14 #include <linux/jiffies.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/mtd/spinand.h> 18 #include <linux/of.h> 19 #include <linux/slab.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi-mem.h> 22 #else 23 #include <common.h> 24 #include <errno.h> 25 #include <spi.h> 26 #include <spi-mem.h> 27 #include <linux/mtd/spinand.h> 28 #endif 29 30 /* SPI NAND index visible in MTD names */ 31 static int spi_nand_idx; 32 33 static void spinand_cache_op_adjust_colum(struct spinand_device *spinand, 34 const struct nand_page_io_req *req, 35 u16 *column) 36 { 37 struct nand_device *nand = spinand_to_nand(spinand); 38 unsigned int shift; 39 40 if (nand->memorg.planes_per_lun < 2) 41 return; 42 43 /* The plane number is passed in MSB just above the column address */ 44 shift = fls(nand->memorg.pagesize); 45 *column |= req->pos.plane << shift; 46 } 47 48 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) 49 { 50 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, 51 spinand->scratchbuf); 52 int ret; 53 54 ret = spi_mem_exec_op(spinand->slave, &op); 55 if (ret) 56 return ret; 57 58 *val = *spinand->scratchbuf; 59 return 0; 60 } 61 62 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) 63 { 64 struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, 65 spinand->scratchbuf); 66 67 *spinand->scratchbuf = val; 68 return spi_mem_exec_op(spinand->slave, &op); 69 } 70 71 static int spinand_read_status(struct spinand_device *spinand, u8 *status) 72 { 73 return spinand_read_reg_op(spinand, REG_STATUS, status); 74 } 75 76 static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg) 77 { 78 struct nand_device *nand = spinand_to_nand(spinand); 79 80 if (WARN_ON(spinand->cur_target < 0 || 81 spinand->cur_target >= nand->memorg.ntargets)) 82 return -EINVAL; 83 84 *cfg = spinand->cfg_cache[spinand->cur_target]; 85 return 0; 86 } 87 88 static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg) 89 { 90 struct nand_device *nand = spinand_to_nand(spinand); 91 int ret; 92 93 if (WARN_ON(spinand->cur_target < 0 || 94 spinand->cur_target >= nand->memorg.ntargets)) 95 return -EINVAL; 96 97 if (spinand->cfg_cache[spinand->cur_target] == cfg) 98 return 0; 99 100 ret = spinand_write_reg_op(spinand, REG_CFG, cfg); 101 if (ret) 102 return ret; 103 104 spinand->cfg_cache[spinand->cur_target] = cfg; 105 return 0; 106 } 107 108 /** 109 * spinand_upd_cfg() - Update the configuration register 110 * @spinand: the spinand device 111 * @mask: the mask encoding the bits to update in the config reg 112 * @val: the new value to apply 113 * 114 * Update the configuration register. 115 * 116 * Return: 0 on success, a negative error code otherwise. 117 */ 118 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val) 119 { 120 int ret; 121 u8 cfg; 122 123 ret = spinand_get_cfg(spinand, &cfg); 124 if (ret) 125 return ret; 126 127 cfg &= ~mask; 128 cfg |= val; 129 130 return spinand_set_cfg(spinand, cfg); 131 } 132 133 /** 134 * spinand_select_target() - Select a specific NAND target/die 135 * @spinand: the spinand device 136 * @target: the target/die to select 137 * 138 * Select a new target/die. If chip only has one die, this function is a NOOP. 139 * 140 * Return: 0 on success, a negative error code otherwise. 141 */ 142 int spinand_select_target(struct spinand_device *spinand, unsigned int target) 143 { 144 struct nand_device *nand = spinand_to_nand(spinand); 145 int ret; 146 147 if (WARN_ON(target >= nand->memorg.ntargets)) 148 return -EINVAL; 149 150 if (spinand->cur_target == target) 151 return 0; 152 153 if (nand->memorg.ntargets == 1) { 154 spinand->cur_target = target; 155 return 0; 156 } 157 158 ret = spinand->select_target(spinand, target); 159 if (ret) 160 return ret; 161 162 spinand->cur_target = target; 163 return 0; 164 } 165 166 static int spinand_init_cfg_cache(struct spinand_device *spinand) 167 { 168 struct nand_device *nand = spinand_to_nand(spinand); 169 struct udevice *dev = spinand->slave->dev; 170 unsigned int target; 171 int ret; 172 173 spinand->cfg_cache = devm_kzalloc(dev, 174 sizeof(*spinand->cfg_cache) * 175 nand->memorg.ntargets, 176 GFP_KERNEL); 177 if (!spinand->cfg_cache) 178 return -ENOMEM; 179 180 for (target = 0; target < nand->memorg.ntargets; target++) { 181 ret = spinand_select_target(spinand, target); 182 if (ret) 183 return ret; 184 185 /* 186 * We use spinand_read_reg_op() instead of spinand_get_cfg() 187 * here to bypass the config cache. 188 */ 189 ret = spinand_read_reg_op(spinand, REG_CFG, 190 &spinand->cfg_cache[target]); 191 if (ret) 192 return ret; 193 } 194 195 return 0; 196 } 197 198 static int spinand_init_quad_enable(struct spinand_device *spinand) 199 { 200 bool enable = false; 201 202 if (!(spinand->flags & SPINAND_HAS_QE_BIT)) 203 return 0; 204 205 if (spinand->op_templates.read_cache->data.buswidth == 4 || 206 spinand->op_templates.write_cache->data.buswidth == 4 || 207 spinand->op_templates.update_cache->data.buswidth == 4) 208 enable = true; 209 210 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, 211 enable ? CFG_QUAD_ENABLE : 0); 212 } 213 214 static int spinand_ecc_enable(struct spinand_device *spinand, 215 bool enable) 216 { 217 return spinand_upd_cfg(spinand, CFG_ECC_ENABLE, 218 enable ? CFG_ECC_ENABLE : 0); 219 } 220 221 static int spinand_write_enable_op(struct spinand_device *spinand) 222 { 223 struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true); 224 225 return spi_mem_exec_op(spinand->slave, &op); 226 } 227 228 static int spinand_load_page_op(struct spinand_device *spinand, 229 const struct nand_page_io_req *req) 230 { 231 struct nand_device *nand = spinand_to_nand(spinand); 232 unsigned int row = nanddev_pos_to_row(nand, &req->pos); 233 struct spi_mem_op op = SPINAND_PAGE_READ_OP(row); 234 235 return spi_mem_exec_op(spinand->slave, &op); 236 } 237 238 static int spinand_read_from_cache_op(struct spinand_device *spinand, 239 const struct nand_page_io_req *req) 240 { 241 struct spi_mem_op op = *spinand->op_templates.read_cache; 242 struct nand_device *nand = spinand_to_nand(spinand); 243 struct mtd_info *mtd = nanddev_to_mtd(nand); 244 struct nand_page_io_req adjreq = *req; 245 unsigned int nbytes = 0; 246 void *buf = NULL; 247 u16 column = 0; 248 int ret; 249 250 if (req->datalen) { 251 adjreq.datalen = nanddev_page_size(nand); 252 adjreq.dataoffs = 0; 253 adjreq.databuf.in = spinand->databuf; 254 buf = spinand->databuf; 255 nbytes = adjreq.datalen; 256 } 257 258 if (req->ooblen) { 259 adjreq.ooblen = nanddev_per_page_oobsize(nand); 260 adjreq.ooboffs = 0; 261 adjreq.oobbuf.in = spinand->oobbuf; 262 nbytes += nanddev_per_page_oobsize(nand); 263 if (!buf) { 264 buf = spinand->oobbuf; 265 column = nanddev_page_size(nand); 266 } 267 } 268 269 spinand_cache_op_adjust_colum(spinand, &adjreq, &column); 270 op.addr.val = column; 271 272 /* 273 * Some controllers are limited in term of max RX data size. In this 274 * case, just repeat the READ_CACHE operation after updating the 275 * column. 276 */ 277 while (nbytes) { 278 op.data.buf.in = buf; 279 op.data.nbytes = nbytes; 280 ret = spi_mem_adjust_op_size(spinand->slave, &op); 281 if (ret) 282 return ret; 283 284 ret = spi_mem_exec_op(spinand->slave, &op); 285 if (ret) 286 return ret; 287 288 buf += op.data.nbytes; 289 nbytes -= op.data.nbytes; 290 op.addr.val += op.data.nbytes; 291 } 292 293 if (req->datalen) 294 memcpy(req->databuf.in, spinand->databuf + req->dataoffs, 295 req->datalen); 296 297 if (req->ooblen) { 298 if (req->mode == MTD_OPS_AUTO_OOB) 299 mtd_ooblayout_get_databytes(mtd, req->oobbuf.in, 300 spinand->oobbuf, 301 req->ooboffs, 302 req->ooblen); 303 else 304 memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs, 305 req->ooblen); 306 } 307 308 return 0; 309 } 310 311 static int spinand_write_to_cache_op(struct spinand_device *spinand, 312 const struct nand_page_io_req *req) 313 { 314 struct spi_mem_op op = *spinand->op_templates.write_cache; 315 struct nand_device *nand = spinand_to_nand(spinand); 316 struct mtd_info *mtd = nanddev_to_mtd(nand); 317 struct nand_page_io_req adjreq = *req; 318 unsigned int nbytes = 0; 319 void *buf = NULL; 320 u16 column = 0; 321 int ret; 322 323 memset(spinand->databuf, 0xff, 324 nanddev_page_size(nand) + 325 nanddev_per_page_oobsize(nand)); 326 327 if (req->datalen) { 328 memcpy(spinand->databuf + req->dataoffs, req->databuf.out, 329 req->datalen); 330 adjreq.dataoffs = 0; 331 adjreq.datalen = nanddev_page_size(nand); 332 adjreq.databuf.out = spinand->databuf; 333 nbytes = adjreq.datalen; 334 buf = spinand->databuf; 335 } 336 337 if (req->ooblen) { 338 if (req->mode == MTD_OPS_AUTO_OOB) 339 mtd_ooblayout_set_databytes(mtd, req->oobbuf.out, 340 spinand->oobbuf, 341 req->ooboffs, 342 req->ooblen); 343 else 344 memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out, 345 req->ooblen); 346 347 adjreq.ooblen = nanddev_per_page_oobsize(nand); 348 adjreq.ooboffs = 0; 349 nbytes += nanddev_per_page_oobsize(nand); 350 if (!buf) { 351 buf = spinand->oobbuf; 352 column = nanddev_page_size(nand); 353 } 354 } 355 356 spinand_cache_op_adjust_colum(spinand, &adjreq, &column); 357 358 op = *spinand->op_templates.write_cache; 359 op.addr.val = column; 360 361 /* 362 * Some controllers are limited in term of max TX data size. In this 363 * case, split the operation into one LOAD CACHE and one or more 364 * LOAD RANDOM CACHE. 365 */ 366 while (nbytes) { 367 op.data.buf.out = buf; 368 op.data.nbytes = nbytes; 369 370 ret = spi_mem_adjust_op_size(spinand->slave, &op); 371 if (ret) 372 return ret; 373 374 ret = spi_mem_exec_op(spinand->slave, &op); 375 if (ret) 376 return ret; 377 378 buf += op.data.nbytes; 379 nbytes -= op.data.nbytes; 380 op.addr.val += op.data.nbytes; 381 382 /* 383 * We need to use the RANDOM LOAD CACHE operation if there's 384 * more than one iteration, because the LOAD operation resets 385 * the cache to 0xff. 386 */ 387 if (nbytes) { 388 column = op.addr.val; 389 op = *spinand->op_templates.update_cache; 390 op.addr.val = column; 391 } 392 } 393 394 return 0; 395 } 396 397 static int spinand_program_op(struct spinand_device *spinand, 398 const struct nand_page_io_req *req) 399 { 400 struct nand_device *nand = spinand_to_nand(spinand); 401 unsigned int row = nanddev_pos_to_row(nand, &req->pos); 402 struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row); 403 404 return spi_mem_exec_op(spinand->slave, &op); 405 } 406 407 static int spinand_erase_op(struct spinand_device *spinand, 408 const struct nand_pos *pos) 409 { 410 struct nand_device *nand = &spinand->base; 411 unsigned int row = nanddev_pos_to_row(nand, pos); 412 struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row); 413 414 return spi_mem_exec_op(spinand->slave, &op); 415 } 416 417 static int spinand_wait(struct spinand_device *spinand, u8 *s) 418 { 419 unsigned long start, stop; 420 u8 status; 421 int ret; 422 423 start = get_timer(0); 424 stop = 400; 425 do { 426 ret = spinand_read_status(spinand, &status); 427 if (ret) 428 return ret; 429 430 if (!(status & STATUS_BUSY)) 431 goto out; 432 } while (get_timer(start) < stop); 433 434 /* 435 * Extra read, just in case the STATUS_READY bit has changed 436 * since our last check 437 */ 438 ret = spinand_read_status(spinand, &status); 439 if (ret) 440 return ret; 441 442 out: 443 if (s) 444 *s = status; 445 446 return status & STATUS_BUSY ? -ETIMEDOUT : 0; 447 } 448 449 static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) 450 { 451 struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, 452 SPINAND_MAX_ID_LEN); 453 int ret; 454 455 ret = spi_mem_exec_op(spinand->slave, &op); 456 if (!ret) 457 memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN); 458 459 return ret; 460 } 461 462 static int spinand_reset_op(struct spinand_device *spinand) 463 { 464 struct spi_mem_op op = SPINAND_RESET_OP; 465 int ret; 466 467 ret = spi_mem_exec_op(spinand->slave, &op); 468 if (ret) 469 return ret; 470 471 return spinand_wait(spinand, NULL); 472 } 473 474 static int spinand_lock_block(struct spinand_device *spinand, u8 lock) 475 { 476 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); 477 } 478 479 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status) 480 { 481 struct nand_device *nand = spinand_to_nand(spinand); 482 483 if (spinand->eccinfo.get_status) 484 return spinand->eccinfo.get_status(spinand, status); 485 486 switch (status & STATUS_ECC_MASK) { 487 case STATUS_ECC_NO_BITFLIPS: 488 return 0; 489 490 case STATUS_ECC_HAS_BITFLIPS: 491 /* 492 * We have no way to know exactly how many bitflips have been 493 * fixed, so let's return the maximum possible value so that 494 * wear-leveling layers move the data immediately. 495 */ 496 return nand->eccreq.strength; 497 498 case STATUS_ECC_UNCOR_ERROR: 499 return -EBADMSG; 500 501 default: 502 break; 503 } 504 505 return -EINVAL; 506 } 507 508 static int spinand_read_page(struct spinand_device *spinand, 509 const struct nand_page_io_req *req, 510 bool ecc_enabled) 511 { 512 u8 status; 513 int ret; 514 515 ret = spinand_load_page_op(spinand, req); 516 if (ret) 517 return ret; 518 519 ret = spinand_wait(spinand, &status); 520 if (ret < 0) 521 return ret; 522 523 ret = spinand_read_from_cache_op(spinand, req); 524 if (ret) 525 return ret; 526 527 if (!ecc_enabled) 528 return 0; 529 530 return spinand_check_ecc_status(spinand, status); 531 } 532 533 static int spinand_write_page(struct spinand_device *spinand, 534 const struct nand_page_io_req *req) 535 { 536 u8 status; 537 int ret; 538 539 ret = spinand_write_enable_op(spinand); 540 if (ret) 541 return ret; 542 543 ret = spinand_write_to_cache_op(spinand, req); 544 if (ret) 545 return ret; 546 547 ret = spinand_program_op(spinand, req); 548 if (ret) 549 return ret; 550 551 ret = spinand_wait(spinand, &status); 552 if (!ret && (status & STATUS_PROG_FAILED)) 553 ret = -EIO; 554 555 return ret; 556 } 557 558 static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, 559 struct mtd_oob_ops *ops) 560 { 561 struct spinand_device *spinand = mtd_to_spinand(mtd); 562 struct nand_device *nand = mtd_to_nanddev(mtd); 563 unsigned int max_bitflips = 0; 564 struct nand_io_iter iter; 565 bool enable_ecc = false; 566 bool ecc_failed = false; 567 int ret = 0; 568 569 if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout) 570 enable_ecc = true; 571 572 #ifndef __UBOOT__ 573 mutex_lock(&spinand->lock); 574 #endif 575 576 nanddev_io_for_each_page(nand, from, ops, &iter) { 577 ret = spinand_select_target(spinand, iter.req.pos.target); 578 if (ret) 579 break; 580 581 ret = spinand_ecc_enable(spinand, enable_ecc); 582 if (ret) 583 break; 584 585 ret = spinand_read_page(spinand, &iter.req, enable_ecc); 586 if (ret < 0 && ret != -EBADMSG) 587 break; 588 589 if (ret == -EBADMSG) { 590 ecc_failed = true; 591 mtd->ecc_stats.failed++; 592 ret = 0; 593 } else { 594 mtd->ecc_stats.corrected += ret; 595 max_bitflips = max_t(unsigned int, max_bitflips, ret); 596 } 597 598 ops->retlen += iter.req.datalen; 599 ops->oobretlen += iter.req.ooblen; 600 } 601 602 #ifndef __UBOOT__ 603 mutex_unlock(&spinand->lock); 604 #endif 605 if (ecc_failed && !ret) 606 ret = -EBADMSG; 607 608 return ret ? ret : max_bitflips; 609 } 610 611 static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, 612 struct mtd_oob_ops *ops) 613 { 614 struct spinand_device *spinand = mtd_to_spinand(mtd); 615 struct nand_device *nand = mtd_to_nanddev(mtd); 616 struct nand_io_iter iter; 617 bool enable_ecc = false; 618 int ret = 0; 619 620 if (ops->mode != MTD_OPS_RAW && mtd->ooblayout) 621 enable_ecc = true; 622 623 #ifndef __UBOOT__ 624 mutex_lock(&spinand->lock); 625 #endif 626 627 nanddev_io_for_each_page(nand, to, ops, &iter) { 628 ret = spinand_select_target(spinand, iter.req.pos.target); 629 if (ret) 630 break; 631 632 ret = spinand_ecc_enable(spinand, enable_ecc); 633 if (ret) 634 break; 635 636 ret = spinand_write_page(spinand, &iter.req); 637 if (ret) 638 break; 639 640 ops->retlen += iter.req.datalen; 641 ops->oobretlen += iter.req.ooblen; 642 } 643 644 #ifndef __UBOOT__ 645 mutex_unlock(&spinand->lock); 646 #endif 647 648 return ret; 649 } 650 651 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) 652 { 653 struct spinand_device *spinand = nand_to_spinand(nand); 654 u8 marker[2] = { }; 655 struct nand_page_io_req req = { 656 .pos = *pos, 657 .ooblen = sizeof(marker), 658 .ooboffs = 0, 659 .oobbuf.in = marker, 660 .mode = MTD_OPS_RAW, 661 }; 662 663 spinand_select_target(spinand, pos->target); 664 spinand_read_page(spinand, &req, false); 665 if (marker[0] != 0xff || marker[1] != 0xff) 666 return true; 667 668 return false; 669 } 670 671 static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) 672 { 673 struct nand_device *nand = mtd_to_nanddev(mtd); 674 #ifndef __UBOOT__ 675 struct spinand_device *spinand = nand_to_spinand(nand); 676 #endif 677 struct nand_pos pos; 678 int ret; 679 680 nanddev_offs_to_pos(nand, offs, &pos); 681 #ifndef __UBOOT__ 682 mutex_lock(&spinand->lock); 683 #endif 684 ret = nanddev_isbad(nand, &pos); 685 #ifndef __UBOOT__ 686 mutex_unlock(&spinand->lock); 687 #endif 688 return ret; 689 } 690 691 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) 692 { 693 struct spinand_device *spinand = nand_to_spinand(nand); 694 u8 marker[2] = { 0, 0 }; 695 struct nand_page_io_req req = { 696 .pos = *pos, 697 .ooboffs = 0, 698 .ooblen = sizeof(marker), 699 .oobbuf.out = marker, 700 .mode = MTD_OPS_RAW, 701 }; 702 int ret; 703 704 ret = spinand_select_target(spinand, pos->target); 705 if (ret) 706 return ret; 707 708 return spinand_write_page(spinand, &req); 709 } 710 711 static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs) 712 { 713 struct nand_device *nand = mtd_to_nanddev(mtd); 714 #ifndef __UBOOT__ 715 struct spinand_device *spinand = nand_to_spinand(nand); 716 #endif 717 struct nand_pos pos; 718 int ret; 719 720 nanddev_offs_to_pos(nand, offs, &pos); 721 #ifndef __UBOOT__ 722 mutex_lock(&spinand->lock); 723 #endif 724 ret = nanddev_markbad(nand, &pos); 725 #ifndef __UBOOT__ 726 mutex_unlock(&spinand->lock); 727 #endif 728 return ret; 729 } 730 731 static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos) 732 { 733 struct spinand_device *spinand = nand_to_spinand(nand); 734 u8 status; 735 int ret; 736 737 ret = spinand_select_target(spinand, pos->target); 738 if (ret) 739 return ret; 740 741 ret = spinand_write_enable_op(spinand); 742 if (ret) 743 return ret; 744 745 ret = spinand_erase_op(spinand, pos); 746 if (ret) 747 return ret; 748 749 ret = spinand_wait(spinand, &status); 750 if (!ret && (status & STATUS_ERASE_FAILED)) 751 ret = -EIO; 752 753 return ret; 754 } 755 756 static int spinand_mtd_erase(struct mtd_info *mtd, 757 struct erase_info *einfo) 758 { 759 #ifndef __UBOOT__ 760 struct spinand_device *spinand = mtd_to_spinand(mtd); 761 #endif 762 int ret; 763 764 #ifndef __UBOOT__ 765 mutex_lock(&spinand->lock); 766 #endif 767 ret = nanddev_mtd_erase(mtd, einfo); 768 #ifndef __UBOOT__ 769 mutex_unlock(&spinand->lock); 770 #endif 771 772 return ret; 773 } 774 775 static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs) 776 { 777 #ifndef __UBOOT__ 778 struct spinand_device *spinand = mtd_to_spinand(mtd); 779 #endif 780 struct nand_device *nand = mtd_to_nanddev(mtd); 781 struct nand_pos pos; 782 int ret; 783 784 nanddev_offs_to_pos(nand, offs, &pos); 785 #ifndef __UBOOT__ 786 mutex_lock(&spinand->lock); 787 #endif 788 ret = nanddev_isreserved(nand, &pos); 789 #ifndef __UBOOT__ 790 mutex_unlock(&spinand->lock); 791 #endif 792 793 return ret; 794 } 795 796 const struct spi_mem_op * 797 spinand_find_supported_op(struct spinand_device *spinand, 798 const struct spi_mem_op *ops, 799 unsigned int nops) 800 { 801 unsigned int i; 802 803 for (i = 0; i < nops; i++) { 804 if (spi_mem_supports_op(spinand->slave, &ops[i])) 805 return &ops[i]; 806 } 807 808 return NULL; 809 } 810 811 static const struct nand_ops spinand_ops = { 812 .erase = spinand_erase, 813 .markbad = spinand_markbad, 814 .isbad = spinand_isbad, 815 }; 816 817 static const struct spinand_manufacturer *spinand_manufacturers[] = { 818 #ifdef CONFIG_SPI_NAND_GIGADEVICE 819 &gigadevice_spinand_manufacturer, 820 #endif 821 #ifdef CONFIG_SPI_NAND_MACRONIX 822 ¯onix_spinand_manufacturer, 823 #endif 824 #ifdef CONFIG_SPI_NAND_MICRON 825 µn_spinand_manufacturer, 826 #endif 827 #ifdef CONFIG_SPI_NAND_TOSHIBA 828 &toshiba_spinand_manufacturer, 829 #endif 830 #ifdef CONFIG_SPI_NAND_WINBOND 831 &winbond_spinand_manufacturer, 832 #endif 833 #ifdef CONFIG_SPI_NAND_DOSILICON 834 &dosilicon_spinand_manufacturer, 835 #endif 836 #ifdef CONFIG_SPI_NAND_ESMT 837 &esmt_spinand_manufacturer, 838 #endif 839 #ifdef CONFIG_SPI_NAND_XTX 840 &xtx_spinand_manufacturer, 841 #endif 842 #ifdef CONFIG_SPI_NAND_HYF 843 &hyf_spinand_manufacturer, 844 #endif 845 #ifdef CONFIG_SPI_NAND_FMSH 846 &fmsh_spinand_manufacturer, 847 #endif 848 #ifdef CONFIG_SPI_NAND_FORESEE 849 &foresee_spinand_manufacturer, 850 #endif 851 #ifdef CONFIG_SPI_NAND_BIWIN 852 &biwin_spinand_manufacturer, 853 #endif 854 #ifdef CONFIG_SPI_NAND_ETRON 855 &etron_spinand_manufacturer, 856 #endif 857 #ifdef CONFIG_SPI_NAND_JSC 858 &jsc_spinand_manufacturer, 859 #endif 860 }; 861 862 static int spinand_manufacturer_detect(struct spinand_device *spinand) 863 { 864 unsigned int i; 865 int ret; 866 867 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { 868 ret = spinand_manufacturers[i]->ops->detect(spinand); 869 if (ret > 0) { 870 spinand->manufacturer = spinand_manufacturers[i]; 871 return 0; 872 } else if (ret < 0) { 873 return ret; 874 } 875 } 876 877 return -ENOTSUPP; 878 } 879 880 static int spinand_manufacturer_init(struct spinand_device *spinand) 881 { 882 if (spinand->manufacturer->ops->init) 883 return spinand->manufacturer->ops->init(spinand); 884 885 return 0; 886 } 887 888 static void spinand_manufacturer_cleanup(struct spinand_device *spinand) 889 { 890 /* Release manufacturer private data */ 891 if (spinand->manufacturer->ops->cleanup) 892 return spinand->manufacturer->ops->cleanup(spinand); 893 } 894 895 static const struct spi_mem_op * 896 spinand_select_op_variant(struct spinand_device *spinand, 897 const struct spinand_op_variants *variants) 898 { 899 struct nand_device *nand = spinand_to_nand(spinand); 900 unsigned int i; 901 902 for (i = 0; i < variants->nops; i++) { 903 struct spi_mem_op op = variants->ops[i]; 904 unsigned int nbytes; 905 int ret; 906 907 nbytes = nanddev_per_page_oobsize(nand) + 908 nanddev_page_size(nand); 909 910 while (nbytes) { 911 op.data.nbytes = nbytes; 912 ret = spi_mem_adjust_op_size(spinand->slave, &op); 913 if (ret) 914 break; 915 916 if (!spi_mem_supports_op(spinand->slave, &op)) 917 break; 918 919 nbytes -= op.data.nbytes; 920 } 921 922 if (!nbytes) 923 return &variants->ops[i]; 924 } 925 926 return NULL; 927 } 928 929 /** 930 * spinand_match_and_init() - Try to find a match between a device ID and an 931 * entry in a spinand_info table 932 * @spinand: SPI NAND object 933 * @table: SPI NAND device description table 934 * @table_size: size of the device description table 935 * 936 * Should be used by SPI NAND manufacturer drivers when they want to find a 937 * match between a device ID retrieved through the READ_ID command and an 938 * entry in the SPI NAND description table. If a match is found, the spinand 939 * object will be initialized with information provided by the matching 940 * spinand_info entry. 941 * 942 * Return: 0 on success, a negative error code otherwise. 943 */ 944 int spinand_match_and_init(struct spinand_device *spinand, 945 const struct spinand_info *table, 946 unsigned int table_size, u8 devid) 947 { 948 struct nand_device *nand = spinand_to_nand(spinand); 949 unsigned int i; 950 951 for (i = 0; i < table_size; i++) { 952 const struct spinand_info *info = &table[i]; 953 const struct spi_mem_op *op; 954 955 if (devid != info->devid) 956 continue; 957 958 nand->memorg = table[i].memorg; 959 nand->eccreq = table[i].eccreq; 960 spinand->eccinfo = table[i].eccinfo; 961 spinand->flags = table[i].flags; 962 spinand->select_target = table[i].select_target; 963 964 op = spinand_select_op_variant(spinand, 965 info->op_variants.read_cache); 966 if (!op) 967 return -ENOTSUPP; 968 969 spinand->op_templates.read_cache = op; 970 971 op = spinand_select_op_variant(spinand, 972 info->op_variants.write_cache); 973 if (!op) 974 return -ENOTSUPP; 975 976 spinand->op_templates.write_cache = op; 977 978 op = spinand_select_op_variant(spinand, 979 info->op_variants.update_cache); 980 spinand->op_templates.update_cache = op; 981 982 return 0; 983 } 984 985 return -ENOTSUPP; 986 } 987 988 static int spinand_detect(struct spinand_device *spinand) 989 { 990 struct nand_device *nand = spinand_to_nand(spinand); 991 int ret; 992 993 ret = spinand_reset_op(spinand); 994 if (ret) 995 return ret; 996 997 ret = spinand_read_id_op(spinand, spinand->id.data); 998 if (ret) 999 return ret; 1000 1001 spinand->id.len = SPINAND_MAX_ID_LEN; 1002 1003 ret = spinand_manufacturer_detect(spinand); 1004 if (ret) { 1005 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN, 1006 spinand->id.data); 1007 return ret; 1008 } 1009 1010 if (nand->memorg.ntargets > 1 && !spinand->select_target) { 1011 dev_err(dev, 1012 "SPI NANDs with more than one die must implement ->select_target()\n"); 1013 return -EINVAL; 1014 } 1015 1016 dev_info(spinand->slave->dev, 1017 "%s SPI NAND was found.\n", spinand->manufacturer->name); 1018 dev_info(spinand->slave->dev, 1019 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n", 1020 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10, 1021 nanddev_page_size(nand), nanddev_per_page_oobsize(nand)); 1022 1023 return 0; 1024 } 1025 1026 static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section, 1027 struct mtd_oob_region *region) 1028 { 1029 return -ERANGE; 1030 } 1031 1032 static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section, 1033 struct mtd_oob_region *region) 1034 { 1035 if (section) 1036 return -ERANGE; 1037 1038 /* Reserve 2 bytes for the BBM. */ 1039 region->offset = 2; 1040 region->length = 62; 1041 1042 return 0; 1043 } 1044 1045 static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = { 1046 .ecc = spinand_noecc_ooblayout_ecc, 1047 .rfree = spinand_noecc_ooblayout_free, 1048 }; 1049 1050 static int spinand_init(struct spinand_device *spinand) 1051 { 1052 struct mtd_info *mtd = spinand_to_mtd(spinand); 1053 struct nand_device *nand = mtd_to_nanddev(mtd); 1054 int ret, i; 1055 1056 /* 1057 * We need a scratch buffer because the spi_mem interface requires that 1058 * buf passed in spi_mem_op->data.buf be DMA-able. 1059 */ 1060 spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL); 1061 if (!spinand->scratchbuf) 1062 return -ENOMEM; 1063 1064 ret = spinand_detect(spinand); 1065 if (ret) 1066 goto err_free_bufs; 1067 1068 /* 1069 * Use kzalloc() instead of devm_kzalloc() here, because some drivers 1070 * may use this buffer for DMA access. 1071 * Memory allocated by devm_ does not guarantee DMA-safe alignment. 1072 */ 1073 spinand->databuf = kzalloc(nanddev_page_size(nand) + 1074 nanddev_per_page_oobsize(nand), 1075 GFP_KERNEL); 1076 if (!spinand->databuf) { 1077 ret = -ENOMEM; 1078 goto err_free_bufs; 1079 } 1080 1081 spinand->oobbuf = spinand->databuf + nanddev_page_size(nand); 1082 1083 ret = spinand_init_cfg_cache(spinand); 1084 if (ret) 1085 goto err_free_bufs; 1086 1087 ret = spinand_init_quad_enable(spinand); 1088 if (ret) 1089 goto err_free_bufs; 1090 1091 ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); 1092 if (ret) 1093 goto err_free_bufs; 1094 1095 ret = spinand_manufacturer_init(spinand); 1096 if (ret) { 1097 dev_err(dev, 1098 "Failed to initialize the SPI NAND chip (err = %d)\n", 1099 ret); 1100 goto err_free_bufs; 1101 } 1102 1103 /* After power up, all blocks are locked, so unlock them here. */ 1104 for (i = 0; i < nand->memorg.ntargets; i++) { 1105 ret = spinand_select_target(spinand, i); 1106 if (ret) 1107 goto err_free_bufs; 1108 1109 ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); 1110 if (ret) 1111 goto err_free_bufs; 1112 } 1113 1114 nand->bbt.option = NANDDEV_BBT_USE_FLASH; 1115 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); 1116 if (ret) 1117 goto err_manuf_cleanup; 1118 1119 /* 1120 * Right now, we don't support ECC, so let the whole oob 1121 * area is available for user. 1122 */ 1123 mtd->_read_oob = spinand_mtd_read; 1124 mtd->_write_oob = spinand_mtd_write; 1125 mtd->_block_isbad = spinand_mtd_block_isbad; 1126 mtd->_block_markbad = spinand_mtd_block_markbad; 1127 mtd->_block_isreserved = spinand_mtd_block_isreserved; 1128 mtd->_erase = spinand_mtd_erase; 1129 1130 if (spinand->eccinfo.ooblayout) 1131 mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout); 1132 else 1133 mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout); 1134 1135 ret = mtd_ooblayout_count_freebytes(mtd); 1136 if (ret < 0) 1137 goto err_cleanup_nanddev; 1138 1139 mtd->oobavail = ret; 1140 1141 /* Propagate ECC information to mtd_info */ 1142 mtd->ecc_strength = nand->eccreq.strength; 1143 mtd->ecc_step_size = nand->eccreq.step_size; 1144 1145 return 0; 1146 1147 err_cleanup_nanddev: 1148 nanddev_cleanup(nand); 1149 1150 err_manuf_cleanup: 1151 spinand_manufacturer_cleanup(spinand); 1152 1153 err_free_bufs: 1154 kfree(spinand->databuf); 1155 kfree(spinand->scratchbuf); 1156 return ret; 1157 } 1158 1159 static void spinand_cleanup(struct spinand_device *spinand) 1160 { 1161 struct nand_device *nand = spinand_to_nand(spinand); 1162 1163 nanddev_cleanup(nand); 1164 spinand_manufacturer_cleanup(spinand); 1165 kfree(spinand->databuf); 1166 kfree(spinand->scratchbuf); 1167 } 1168 1169 static int spinand_bind(struct udevice *udev) 1170 { 1171 int ret = 0; 1172 1173 #ifdef CONFIG_MTD_BLK 1174 struct udevice *bdev; 1175 1176 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD, 1177 BLK_MTD_SPI_NAND, 512, 0, &bdev); 1178 if (ret) 1179 printf("Cannot create block device\n"); 1180 #endif 1181 return ret; 1182 } 1183 1184 static int spinand_probe(struct udevice *dev) 1185 { 1186 struct spinand_device *spinand = dev_get_priv(dev); 1187 struct spi_slave *slave = dev_get_parent_priv(dev); 1188 struct mtd_info *mtd = dev_get_uclass_priv(dev); 1189 struct nand_device *nand = spinand_to_nand(spinand); 1190 int ret; 1191 1192 #ifndef __UBOOT__ 1193 spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand), 1194 GFP_KERNEL); 1195 if (!spinand) 1196 return -ENOMEM; 1197 1198 spinand->spimem = mem; 1199 spi_mem_set_drvdata(mem, spinand); 1200 spinand_set_of_node(spinand, mem->spi->dev.of_node); 1201 mutex_init(&spinand->lock); 1202 1203 mtd = spinand_to_mtd(spinand); 1204 mtd->dev.parent = &mem->spi->dev; 1205 #else 1206 nand->mtd = mtd; 1207 mtd->priv = nand; 1208 mtd->dev = dev; 1209 mtd->name = malloc(20); 1210 if (!mtd->name) 1211 return -ENOMEM; 1212 sprintf(mtd->name, "spi-nand%d", spi_nand_idx++); 1213 spinand->slave = slave; 1214 spinand_set_of_node(spinand, dev->node.np); 1215 #endif 1216 1217 ret = spinand_init(spinand); 1218 if (ret) 1219 return ret; 1220 1221 #ifndef __UBOOT__ 1222 ret = mtd_device_register(mtd, NULL, 0); 1223 #else 1224 ret = add_mtd_device(mtd); 1225 #endif 1226 if (ret) 1227 goto err_spinand_cleanup; 1228 1229 return 0; 1230 1231 err_spinand_cleanup: 1232 spinand_cleanup(spinand); 1233 1234 return ret; 1235 } 1236 1237 #ifndef __UBOOT__ 1238 static int spinand_remove(struct udevice *slave) 1239 { 1240 struct spinand_device *spinand; 1241 struct mtd_info *mtd; 1242 int ret; 1243 1244 spinand = spi_mem_get_drvdata(slave); 1245 mtd = spinand_to_mtd(spinand); 1246 free(mtd->name); 1247 1248 ret = mtd_device_unregister(mtd); 1249 if (ret) 1250 return ret; 1251 1252 spinand_cleanup(spinand); 1253 1254 return 0; 1255 } 1256 1257 static const struct spi_device_id spinand_ids[] = { 1258 { .name = "spi-nand" }, 1259 { /* sentinel */ }, 1260 }; 1261 1262 #ifdef CONFIG_OF 1263 static const struct of_device_id spinand_of_ids[] = { 1264 { .compatible = "spi-nand" }, 1265 { /* sentinel */ }, 1266 }; 1267 #endif 1268 1269 static struct spi_mem_driver spinand_drv = { 1270 .spidrv = { 1271 .id_table = spinand_ids, 1272 .driver = { 1273 .name = "spi-nand", 1274 .of_match_table = of_match_ptr(spinand_of_ids), 1275 }, 1276 }, 1277 .probe = spinand_probe, 1278 .remove = spinand_remove, 1279 }; 1280 module_spi_mem_driver(spinand_drv); 1281 1282 MODULE_DESCRIPTION("SPI NAND framework"); 1283 MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>"); 1284 MODULE_LICENSE("GPL v2"); 1285 #endif /* __UBOOT__ */ 1286 1287 static const struct udevice_id spinand_ids[] = { 1288 { .compatible = "spi-nand" }, 1289 { /* sentinel */ }, 1290 }; 1291 1292 U_BOOT_DRIVER(spinand) = { 1293 .name = "spi_nand", 1294 .id = UCLASS_MTD, 1295 .of_match = spinand_ids, 1296 .bind = spinand_bind, 1297 .priv_auto_alloc_size = sizeof(struct spinand_device), 1298 .probe = spinand_probe, 1299 }; 1300