1 /* 2 * (C) Copyright 2016 Xilinx, Inc. 3 * 4 * Xilinx Zynq NAND Flash Controller Driver 5 * This driver is based on plat_nand.c and mxc_nand.c drivers 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <asm/io.h> 13 #include <linux/errno.h> 14 #include <nand.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/rawnand.h> 17 #include <linux/mtd/partitions.h> 18 #include <linux/mtd/nand_ecc.h> 19 #include <asm/arch/hardware.h> 20 #include <asm/arch/sys_proto.h> 21 22 /* The NAND flash driver defines */ 23 #define ZYNQ_NAND_CMD_PHASE 1 24 #define ZYNQ_NAND_DATA_PHASE 2 25 #define ZYNQ_NAND_ECC_SIZE 512 26 #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0) 27 #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0) 28 #define ZYNQ_NAND_ECC_STATUS (1 << 6) 29 #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4) 30 #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6) 31 #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4) 32 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC 33 34 /* Flash memory controller operating parameters */ 35 #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \ 36 (0x1 << 4) | /* Clear interrupt */ \ 37 (0x1 << 6)) /* Disable ECC interrupt */ 38 39 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 40 41 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */ 42 #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ 43 (0x2 << 17) | /* t_ar from nand_cycles */ \ 44 (0x1 << 14) | /* t_clr from nand_cycles */ \ 45 (0x3 << 11) | /* t_wp from nand_cycles */ \ 46 (0x2 << 8) | /* t_rea from nand_cycles */ \ 47 (0x5 << 4) | /* t_wc from nand_cycles */ \ 48 (0x5 << 0)) /* t_rc from nand_cycles */ 49 #endif 50 51 52 #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ 53 (0x2 << 21)) /* UpdateRegs operation */ 54 55 #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \ 56 (0x1 << 4) | /* ECC read at end of page */ \ 57 (0x0 << 5)) /* No Jumping */ 58 59 #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ 60 (0x00 << 8) | /* Read command */ \ 61 (0x30 << 16) | /* Read End command */ \ 62 (0x1 << 24)) /* Read End command calid */ 63 64 #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ 65 (0x05 << 8) | /* Read col change cmd */ \ 66 (0xE0 << 16) | /* Read col change end cmd */ \ 67 (0x1 << 24)) /* Read col change 68 end cmd valid */ 69 /* AXI Address definitions */ 70 #define START_CMD_SHIFT 3 71 #define END_CMD_SHIFT 11 72 #define END_CMD_VALID_SHIFT 20 73 #define ADDR_CYCLES_SHIFT 21 74 #define CLEAR_CS_SHIFT 21 75 #define ECC_LAST_SHIFT 10 76 #define COMMAND_PHASE (0 << 19) 77 #define DATA_PHASE (1 << 19) 78 #define ONDIE_ECC_FEATURE_ADDR 0x90 79 #define ONDIE_ECC_FEATURE_ENABLE 0x08 80 81 #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */ 82 #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */ 83 84 /* ECC block registers bit position and bit mask */ 85 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ 86 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ 87 88 #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F 89 #define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0 90 91 #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 92 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 93 94 enum zynq_nand_bus_width { 95 NAND_BW_UNKNOWN = -1, 96 NAND_BW_8BIT, 97 NAND_BW_16BIT, 98 }; 99 100 #ifndef NAND_CMD_LOCK_TIGHT 101 #define NAND_CMD_LOCK_TIGHT 0x2c 102 #endif 103 104 #ifndef NAND_CMD_LOCK_STATUS 105 #define NAND_CMD_LOCK_STATUS 0x7a 106 #endif 107 108 /* SMC register set */ 109 struct zynq_nand_smc_regs { 110 u32 csr; /* 0x00 */ 111 u32 reserved0[2]; 112 u32 cfr; /* 0x0C */ 113 u32 dcr; /* 0x10 */ 114 u32 scr; /* 0x14 */ 115 u32 sor; /* 0x18 */ 116 u32 reserved1[249]; 117 u32 esr; /* 0x400 */ 118 u32 emcr; /* 0x404 */ 119 u32 emcmd1r; /* 0x408 */ 120 u32 emcmd2r; /* 0x40C */ 121 u32 reserved2[2]; 122 u32 eval0r; /* 0x418 */ 123 }; 124 #define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\ 125 ZYNQ_SMC_BASEADDR) 126 127 /* 128 * struct zynq_nand_info - Defines the NAND flash driver instance 129 * @parts: Pointer to the mtd_partition structure 130 * @nand_base: Virtual address of the NAND flash device 131 * @end_cmd_pending: End command is pending 132 * @end_cmd: End command 133 */ 134 struct zynq_nand_info { 135 void __iomem *nand_base; 136 u8 end_cmd_pending; 137 u8 end_cmd; 138 }; 139 140 /* 141 * struct zynq_nand_command_format - Defines NAND flash command format 142 * @start_cmd: First cycle command (Start command) 143 * @end_cmd: Second cycle command (Last command) 144 * @addr_cycles: Number of address cycles required to send the address 145 * @end_cmd_valid: The second cycle command is valid for cmd or data phase 146 */ 147 struct zynq_nand_command_format { 148 u8 start_cmd; 149 u8 end_cmd; 150 u8 addr_cycles; 151 u8 end_cmd_valid; 152 }; 153 154 /* The NAND flash operations command format */ 155 static const struct zynq_nand_command_format zynq_nand_commands[] = { 156 {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE}, 157 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE}, 158 {NAND_CMD_READID, NAND_CMD_NONE, 1, 0}, 159 {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0}, 160 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE}, 161 {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0}, 162 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE}, 163 {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0}, 164 {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0}, 165 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0}, 166 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0}, 167 {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0}, 168 {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0}, 169 {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0}, 170 {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0}, 171 {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0}, 172 {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0}, 173 /* Add all the flash commands supported by the flash device */ 174 }; 175 176 /* Define default oob placement schemes for large and small page devices */ 177 static struct nand_ecclayout nand_oob_16 = { 178 .eccbytes = 3, 179 .eccpos = {0, 1, 2}, 180 .oobfree = { 181 { .offset = 8, .length = 8 } 182 } 183 }; 184 185 static struct nand_ecclayout nand_oob_64 = { 186 .eccbytes = 12, 187 .eccpos = { 188 52, 53, 54, 55, 56, 57, 189 58, 59, 60, 61, 62, 63}, 190 .oobfree = { 191 { .offset = 2, .length = 50 } 192 } 193 }; 194 195 static struct nand_ecclayout ondie_nand_oob_64 = { 196 .eccbytes = 32, 197 198 .eccpos = { 199 8, 9, 10, 11, 12, 13, 14, 15, 200 24, 25, 26, 27, 28, 29, 30, 31, 201 40, 41, 42, 43, 44, 45, 46, 47, 202 56, 57, 58, 59, 60, 61, 62, 63 203 }, 204 205 .oobfree = { 206 { .offset = 4, .length = 4 }, 207 { .offset = 20, .length = 4 }, 208 { .offset = 36, .length = 4 }, 209 { .offset = 52, .length = 4 } 210 } 211 }; 212 213 /* bbt decriptors for chips with on-die ECC and 214 chips with 64-byte OOB */ 215 static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 216 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 217 218 static struct nand_bbt_descr bbt_main_descr = { 219 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 220 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 221 .offs = 4, 222 .len = 4, 223 .veroffs = 20, 224 .maxblocks = 4, 225 .pattern = bbt_pattern 226 }; 227 228 static struct nand_bbt_descr bbt_mirror_descr = { 229 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 230 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 231 .offs = 4, 232 .len = 4, 233 .veroffs = 20, 234 .maxblocks = 4, 235 .pattern = mirror_pattern 236 }; 237 238 /* 239 * zynq_nand_waitfor_ecc_completion - Wait for ECC completion 240 * 241 * returns: status for command completion, -1 for Timeout 242 */ 243 static int zynq_nand_waitfor_ecc_completion(void) 244 { 245 unsigned long timeout; 246 u32 status; 247 248 /* Wait max 10us */ 249 timeout = 10; 250 status = readl(&zynq_nand_smc_base->esr); 251 while (status & ZYNQ_NAND_ECC_BUSY) { 252 status = readl(&zynq_nand_smc_base->esr); 253 if (timeout == 0) 254 return -1; 255 timeout--; 256 udelay(1); 257 } 258 259 return status; 260 } 261 262 /* 263 * zynq_nand_init_nand_flash - Initialize NAND controller 264 * @option: Device property flags 265 * 266 * This function initializes the NAND flash interface on the NAND controller. 267 * 268 * returns: 0 on success or error value on failure 269 */ 270 static int zynq_nand_init_nand_flash(int option) 271 { 272 u32 status; 273 274 /* disable interrupts */ 275 writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); 276 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 277 /* Initialize the NAND interface by setting cycles and operation mode */ 278 writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); 279 #endif 280 if (option & NAND_BUSWIDTH_16) 281 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor); 282 else 283 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor); 284 285 writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr); 286 287 /* Wait till the ECC operation is complete */ 288 status = zynq_nand_waitfor_ecc_completion(); 289 if (status < 0) { 290 printf("%s: Timeout\n", __func__); 291 return status; 292 } 293 294 /* Set the command1 and command2 register */ 295 writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r); 296 writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r); 297 298 return 0; 299 } 300 301 /* 302 * zynq_nand_calculate_hwecc - Calculate Hardware ECC 303 * @mtd: Pointer to the mtd_info structure 304 * @data: Pointer to the page data 305 * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored 306 * 307 * This function retrieves the Hardware ECC data from the controller and returns 308 * ECC data back to the MTD subsystem. 309 * 310 * returns: 0 on success or error value on failure 311 */ 312 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, 313 u8 *ecc_code) 314 { 315 u32 ecc_value = 0; 316 u8 ecc_reg, ecc_byte; 317 u32 ecc_status; 318 319 /* Wait till the ECC operation is complete */ 320 ecc_status = zynq_nand_waitfor_ecc_completion(); 321 if (ecc_status < 0) { 322 printf("%s: Timeout\n", __func__); 323 return ecc_status; 324 } 325 326 for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) { 327 /* Read ECC value for each block */ 328 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg); 329 330 /* Get the ecc status from ecc read value */ 331 ecc_status = (ecc_value >> 24) & 0xFF; 332 333 /* ECC value valid */ 334 if (ecc_status & ZYNQ_NAND_ECC_STATUS) { 335 for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) { 336 /* Copy ECC bytes to MTD buffer */ 337 *ecc_code = ecc_value & 0xFF; 338 ecc_value = ecc_value >> 8; 339 ecc_code++; 340 } 341 } else { 342 debug("%s: ecc status failed\n", __func__); 343 } 344 } 345 346 return 0; 347 } 348 349 /* 350 * onehot - onehot function 351 * @value: value to check for onehot 352 * 353 * This function checks whether a value is onehot or not. 354 * onehot is if and only if one bit is set. 355 * 356 * FIXME: Try to move this in common.h 357 */ 358 static bool onehot(unsigned short value) 359 { 360 bool onehot; 361 362 onehot = value && !(value & (value - 1)); 363 return onehot; 364 } 365 366 /* 367 * zynq_nand_correct_data - ECC correction function 368 * @mtd: Pointer to the mtd_info structure 369 * @buf: Pointer to the page data 370 * @read_ecc: Pointer to the ECC value read from spare data area 371 * @calc_ecc: Pointer to the calculated ECC value 372 * 373 * This function corrects the ECC single bit errors & detects 2-bit errors. 374 * 375 * returns: 0 if no ECC errors found 376 * 1 if single bit error found and corrected. 377 * -1 if multiple ECC errors found. 378 */ 379 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, 380 unsigned char *read_ecc, unsigned char *calc_ecc) 381 { 382 unsigned char bit_addr; 383 unsigned int byte_addr; 384 unsigned short ecc_odd, ecc_even; 385 unsigned short read_ecc_lower, read_ecc_upper; 386 unsigned short calc_ecc_lower, calc_ecc_upper; 387 388 read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff; 389 read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff; 390 391 calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff; 392 calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff; 393 394 ecc_odd = read_ecc_lower ^ calc_ecc_lower; 395 ecc_even = read_ecc_upper ^ calc_ecc_upper; 396 397 if ((ecc_odd == 0) && (ecc_even == 0)) 398 return 0; /* no error */ 399 400 if (ecc_odd == (~ecc_even & 0xfff)) { 401 /* bits [11:3] of error code is byte offset */ 402 byte_addr = (ecc_odd >> 3) & 0x1ff; 403 /* bits [2:0] of error code is bit offset */ 404 bit_addr = ecc_odd & 0x7; 405 /* Toggling error bit */ 406 buf[byte_addr] ^= (1 << bit_addr); 407 return 1; 408 } 409 410 if (onehot(ecc_odd | ecc_even)) 411 return 1; /* one error in parity */ 412 413 return -1; /* Uncorrectable error */ 414 } 415 416 /* 417 * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function 418 * @mtd: mtd info structure 419 * @chip: nand chip info structure 420 * @page: page number to read 421 * @sndcmd: flag whether to issue read command or not 422 */ 423 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 424 int page) 425 { 426 unsigned long data_phase_addr = 0; 427 int data_width = 4; 428 u8 *p; 429 430 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 431 432 p = chip->oob_poi; 433 chip->read_buf(mtd, p, (mtd->oobsize - data_width)); 434 p += mtd->oobsize - data_width; 435 436 data_phase_addr = (unsigned long)chip->IO_ADDR_R; 437 data_phase_addr |= ZYNQ_NAND_CLEAR_CS; 438 chip->IO_ADDR_R = (void __iomem *)data_phase_addr; 439 chip->read_buf(mtd, p, data_width); 440 441 return 0; 442 } 443 444 /* 445 * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function 446 * @mtd: mtd info structure 447 * @chip: nand chip info structure 448 * @page: page number to write 449 */ 450 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 451 int page) 452 { 453 int status = 0, data_width = 4; 454 const u8 *buf = chip->oob_poi; 455 unsigned long data_phase_addr = 0; 456 457 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 458 459 chip->write_buf(mtd, buf, (mtd->oobsize - data_width)); 460 buf += mtd->oobsize - data_width; 461 462 data_phase_addr = (unsigned long)chip->IO_ADDR_W; 463 data_phase_addr |= ZYNQ_NAND_CLEAR_CS; 464 data_phase_addr |= (1 << END_CMD_VALID_SHIFT); 465 chip->IO_ADDR_W = (void __iomem *)data_phase_addr; 466 chip->write_buf(mtd, buf, data_width); 467 468 /* Send command to program the OOB data */ 469 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 470 status = chip->waitfunc(mtd, chip); 471 472 return status & NAND_STATUS_FAIL ? -EIO : 0; 473 } 474 475 /* 476 * zynq_nand_read_page_raw - [Intern] read raw page data without ecc 477 * @mtd: mtd info structure 478 * @chip: nand chip info structure 479 * @buf: buffer to store read data 480 * @oob_required: must write chip->oob_poi to OOB 481 * @page: page number to read 482 */ 483 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 484 u8 *buf, int oob_required, int page) 485 { 486 unsigned long data_width = 4; 487 unsigned long data_phase_addr = 0; 488 u8 *p; 489 490 chip->read_buf(mtd, buf, mtd->writesize); 491 492 p = chip->oob_poi; 493 chip->read_buf(mtd, p, (mtd->oobsize - data_width)); 494 p += (mtd->oobsize - data_width); 495 496 data_phase_addr = (unsigned long)chip->IO_ADDR_R; 497 data_phase_addr |= ZYNQ_NAND_CLEAR_CS; 498 chip->IO_ADDR_R = (void __iomem *)data_phase_addr; 499 500 chip->read_buf(mtd, p, data_width); 501 return 0; 502 } 503 504 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd, 505 struct nand_chip *chip, u8 *buf, int oob_required, int page) 506 { 507 chip->read_buf(mtd, buf, mtd->writesize); 508 return 0; 509 } 510 511 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd, 512 struct nand_chip *chip, u32 data_offs, 513 u32 readlen, u8 *buf, int page) 514 { 515 if (data_offs != 0) { 516 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1); 517 buf += data_offs; 518 } 519 chip->read_buf(mtd, buf, readlen); 520 521 return 0; 522 } 523 524 /* 525 * zynq_nand_write_page_raw - [Intern] raw page write function 526 * @mtd: mtd info structure 527 * @chip: nand chip info structure 528 * @buf: data buffer 529 * @oob_required: must write chip->oob_poi to OOB 530 */ 531 static int zynq_nand_write_page_raw(struct mtd_info *mtd, 532 struct nand_chip *chip, const u8 *buf, int oob_required, int page) 533 { 534 unsigned long data_width = 4; 535 unsigned long data_phase_addr = 0; 536 u8 *p; 537 538 chip->write_buf(mtd, buf, mtd->writesize); 539 540 p = chip->oob_poi; 541 chip->write_buf(mtd, p, (mtd->oobsize - data_width)); 542 p += (mtd->oobsize - data_width); 543 544 data_phase_addr = (unsigned long)chip->IO_ADDR_W; 545 data_phase_addr |= ZYNQ_NAND_CLEAR_CS; 546 data_phase_addr |= (1 << END_CMD_VALID_SHIFT); 547 chip->IO_ADDR_W = (void __iomem *)data_phase_addr; 548 549 chip->write_buf(mtd, p, data_width); 550 551 return 0; 552 } 553 554 /* 555 * nand_write_page_hwecc - Hardware ECC based page write function 556 * @mtd: Pointer to the mtd info structure 557 * @chip: Pointer to the NAND chip info structure 558 * @buf: Pointer to the data buffer 559 * @oob_required: must write chip->oob_poi to OOB 560 * 561 * This functions writes data and hardware generated ECC values in to the page. 562 */ 563 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd, 564 struct nand_chip *chip, const u8 *buf, int oob_required, int page) 565 { 566 int i, eccsteps, eccsize = chip->ecc.size; 567 u8 *ecc_calc = chip->buffers->ecccalc; 568 const u8 *p = buf; 569 u32 *eccpos = chip->ecc.layout->eccpos; 570 unsigned long data_phase_addr = 0; 571 unsigned long data_width = 4; 572 u8 *oob_ptr; 573 574 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) { 575 chip->write_buf(mtd, p, eccsize); 576 p += eccsize; 577 } 578 chip->write_buf(mtd, p, (eccsize - data_width)); 579 p += eccsize - data_width; 580 581 /* Set ECC Last bit to 1 */ 582 data_phase_addr = (unsigned long) chip->IO_ADDR_W; 583 data_phase_addr |= ZYNQ_NAND_ECC_LAST; 584 chip->IO_ADDR_W = (void __iomem *)data_phase_addr; 585 chip->write_buf(mtd, p, data_width); 586 587 /* Wait for ECC to be calculated and read the error values */ 588 p = buf; 589 chip->ecc.calculate(mtd, p, &ecc_calc[0]); 590 591 for (i = 0; i < chip->ecc.total; i++) 592 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]); 593 594 /* Clear ECC last bit */ 595 data_phase_addr = (unsigned long)chip->IO_ADDR_W; 596 data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; 597 chip->IO_ADDR_W = (void __iomem *)data_phase_addr; 598 599 /* Write the spare area with ECC bytes */ 600 oob_ptr = chip->oob_poi; 601 chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); 602 603 data_phase_addr = (unsigned long)chip->IO_ADDR_W; 604 data_phase_addr |= ZYNQ_NAND_CLEAR_CS; 605 data_phase_addr |= (1 << END_CMD_VALID_SHIFT); 606 chip->IO_ADDR_W = (void __iomem *)data_phase_addr; 607 oob_ptr += (mtd->oobsize - data_width); 608 chip->write_buf(mtd, oob_ptr, data_width); 609 610 return 0; 611 } 612 613 /* 614 * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page 615 * write function 616 * @mtd: mtd info structure 617 * @chip: nand chip info structure 618 * @buf: data buffer 619 * @oob_required: must write chip->oob_poi to OOB 620 */ 621 static int zynq_nand_write_page_swecc(struct mtd_info *mtd, 622 struct nand_chip *chip, const u8 *buf, int oob_required, int page) 623 { 624 int i, eccsize = chip->ecc.size; 625 int eccbytes = chip->ecc.bytes; 626 int eccsteps = chip->ecc.steps; 627 u8 *ecc_calc = chip->buffers->ecccalc; 628 const u8 *p = buf; 629 u32 *eccpos = chip->ecc.layout->eccpos; 630 631 /* Software ecc calculation */ 632 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 633 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 634 635 for (i = 0; i < chip->ecc.total; i++) 636 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 637 638 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); 639 } 640 641 /* 642 * nand_read_page_hwecc - Hardware ECC based page read function 643 * @mtd: Pointer to the mtd info structure 644 * @chip: Pointer to the NAND chip info structure 645 * @buf: Pointer to the buffer to store read data 646 * @oob_required: must write chip->oob_poi to OOB 647 * @page: page number to read 648 * 649 * This functions reads data and checks the data integrity by comparing hardware 650 * generated ECC values and read ECC values from spare area. 651 * 652 * returns: 0 always and updates ECC operation status in to MTD structure 653 */ 654 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd, 655 struct nand_chip *chip, u8 *buf, int oob_required, int page) 656 { 657 int i, stat, eccsteps, eccsize = chip->ecc.size; 658 int eccbytes = chip->ecc.bytes; 659 u8 *p = buf; 660 u8 *ecc_calc = chip->buffers->ecccalc; 661 u8 *ecc_code = chip->buffers->ecccode; 662 u32 *eccpos = chip->ecc.layout->eccpos; 663 unsigned long data_phase_addr = 0; 664 unsigned long data_width = 4; 665 u8 *oob_ptr; 666 667 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) { 668 chip->read_buf(mtd, p, eccsize); 669 p += eccsize; 670 } 671 chip->read_buf(mtd, p, (eccsize - data_width)); 672 p += eccsize - data_width; 673 674 /* Set ECC Last bit to 1 */ 675 data_phase_addr = (unsigned long)chip->IO_ADDR_R; 676 data_phase_addr |= ZYNQ_NAND_ECC_LAST; 677 chip->IO_ADDR_R = (void __iomem *)data_phase_addr; 678 chip->read_buf(mtd, p, data_width); 679 680 /* Read the calculated ECC value */ 681 p = buf; 682 chip->ecc.calculate(mtd, p, &ecc_calc[0]); 683 684 /* Clear ECC last bit */ 685 data_phase_addr = (unsigned long)chip->IO_ADDR_R; 686 data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; 687 chip->IO_ADDR_R = (void __iomem *)data_phase_addr; 688 689 /* Read the stored ECC value */ 690 oob_ptr = chip->oob_poi; 691 chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); 692 693 /* de-assert chip select */ 694 data_phase_addr = (unsigned long)chip->IO_ADDR_R; 695 data_phase_addr |= ZYNQ_NAND_CLEAR_CS; 696 chip->IO_ADDR_R = (void __iomem *)data_phase_addr; 697 698 oob_ptr += (mtd->oobsize - data_width); 699 chip->read_buf(mtd, oob_ptr, data_width); 700 701 for (i = 0; i < chip->ecc.total; i++) 702 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]); 703 704 eccsteps = chip->ecc.steps; 705 p = buf; 706 707 /* Check ECC error for all blocks and correct if it is correctable */ 708 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 709 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 710 if (stat < 0) 711 mtd->ecc_stats.failed++; 712 else 713 mtd->ecc_stats.corrected += stat; 714 } 715 return 0; 716 } 717 718 /* 719 * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page 720 * read function 721 * @mtd: mtd info structure 722 * @chip: nand chip info structure 723 * @buf: buffer to store read data 724 * @page: page number to read 725 */ 726 static int zynq_nand_read_page_swecc(struct mtd_info *mtd, 727 struct nand_chip *chip, u8 *buf, int oob_required, int page) 728 { 729 int i, eccsize = chip->ecc.size; 730 int eccbytes = chip->ecc.bytes; 731 int eccsteps = chip->ecc.steps; 732 u8 *p = buf; 733 u8 *ecc_calc = chip->buffers->ecccalc; 734 u8 *ecc_code = chip->buffers->ecccode; 735 u32 *eccpos = chip->ecc.layout->eccpos; 736 737 chip->ecc.read_page_raw(mtd, chip, buf, 1, page); 738 739 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 740 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 741 742 for (i = 0; i < chip->ecc.total; i++) 743 ecc_code[i] = chip->oob_poi[eccpos[i]]; 744 745 eccsteps = chip->ecc.steps; 746 p = buf; 747 748 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 749 int stat; 750 751 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 752 if (stat < 0) 753 mtd->ecc_stats.failed++; 754 else 755 mtd->ecc_stats.corrected += stat; 756 } 757 return 0; 758 } 759 760 /* 761 * zynq_nand_select_chip - Select the flash device 762 * @mtd: Pointer to the mtd_info structure 763 * @chip: Chip number to be selected 764 * 765 * This function is empty as the NAND controller handles chip select line 766 * internally based on the chip address passed in command and data phase. 767 */ 768 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip) 769 { 770 /* Not support multiple chips yet */ 771 } 772 773 /* 774 * zynq_nand_cmd_function - Send command to NAND device 775 * @mtd: Pointer to the mtd_info structure 776 * @command: The command to be sent to the flash device 777 * @column: The column address for this command, -1 if none 778 * @page_addr: The page address for this command, -1 if none 779 */ 780 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, 781 int column, int page_addr) 782 { 783 struct nand_chip *chip = mtd->priv; 784 const struct zynq_nand_command_format *curr_cmd = NULL; 785 u8 addr_cycles = 0; 786 struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv; 787 void *cmd_addr; 788 unsigned long cmd_data = 0; 789 unsigned long cmd_phase_addr = 0; 790 unsigned long data_phase_addr = 0; 791 u8 end_cmd = 0; 792 u8 end_cmd_valid = 0; 793 u32 index; 794 795 if (xnand->end_cmd_pending) { 796 /* Check for end command if this command request is same as the 797 * pending command then return 798 */ 799 if (xnand->end_cmd == command) { 800 xnand->end_cmd = 0; 801 xnand->end_cmd_pending = 0; 802 return; 803 } 804 } 805 806 /* Emulate NAND_CMD_READOOB for large page device */ 807 if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) && 808 (command == NAND_CMD_READOOB)) { 809 column += mtd->writesize; 810 command = NAND_CMD_READ0; 811 } 812 813 /* Get the command format */ 814 for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++) 815 if (command == zynq_nand_commands[index].start_cmd) 816 break; 817 818 if (index == ARRAY_SIZE(zynq_nand_commands)) { 819 printf("%s: Unsupported start cmd %02x\n", __func__, command); 820 return; 821 } 822 curr_cmd = &zynq_nand_commands[index]; 823 824 /* Clear interrupt */ 825 writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr); 826 827 /* Get the command phase address */ 828 if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) 829 end_cmd_valid = 1; 830 831 if (curr_cmd->end_cmd == NAND_CMD_NONE) 832 end_cmd = 0x0; 833 else 834 end_cmd = curr_cmd->end_cmd; 835 836 if (command == NAND_CMD_READ0 || 837 command == NAND_CMD_SEQIN) { 838 addr_cycles = chip->onfi_params.addr_cycles & 839 ZYNQ_NAND_ROW_ADDR_CYCL_MASK; 840 addr_cycles += ((chip->onfi_params.addr_cycles & 841 ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4); 842 } else { 843 addr_cycles = curr_cmd->addr_cycles; 844 } 845 846 cmd_phase_addr = (unsigned long)xnand->nand_base | 847 (addr_cycles << ADDR_CYCLES_SHIFT) | 848 (end_cmd_valid << END_CMD_VALID_SHIFT) | 849 (COMMAND_PHASE) | 850 (end_cmd << END_CMD_SHIFT) | 851 (curr_cmd->start_cmd << START_CMD_SHIFT); 852 853 cmd_addr = (void __iomem *)cmd_phase_addr; 854 855 /* Get the data phase address */ 856 end_cmd_valid = 0; 857 858 data_phase_addr = (unsigned long)xnand->nand_base | 859 (0x0 << CLEAR_CS_SHIFT) | 860 (end_cmd_valid << END_CMD_VALID_SHIFT) | 861 (DATA_PHASE) | 862 (end_cmd << END_CMD_SHIFT) | 863 (0x0 << ECC_LAST_SHIFT); 864 865 chip->IO_ADDR_R = (void __iomem *)data_phase_addr; 866 chip->IO_ADDR_W = chip->IO_ADDR_R; 867 868 /* Command phase AXI Read & Write */ 869 if (column != -1 && page_addr != -1) { 870 /* Adjust columns for 16 bit bus width */ 871 if (chip->options & NAND_BUSWIDTH_16) 872 column >>= 1; 873 cmd_data = column; 874 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) { 875 cmd_data |= page_addr << 16; 876 /* Another address cycle for devices > 128MiB */ 877 if (chip->chipsize > (128 << 20)) { 878 writel(cmd_data, cmd_addr); 879 cmd_data = (page_addr >> 16); 880 } 881 } else { 882 cmd_data |= page_addr << 8; 883 } 884 } else if (page_addr != -1) { /* Erase */ 885 cmd_data = page_addr; 886 } else if (column != -1) { /* Change read/write column, read id etc */ 887 /* Adjust columns for 16 bit bus width */ 888 if ((chip->options & NAND_BUSWIDTH_16) && 889 ((command == NAND_CMD_READ0) || 890 (command == NAND_CMD_SEQIN) || 891 (command == NAND_CMD_RNDOUT) || 892 (command == NAND_CMD_RNDIN))) 893 column >>= 1; 894 cmd_data = column; 895 } 896 897 writel(cmd_data, cmd_addr); 898 899 if (curr_cmd->end_cmd_valid) { 900 xnand->end_cmd = curr_cmd->end_cmd; 901 xnand->end_cmd_pending = 1; 902 } 903 904 ndelay(100); 905 906 if ((command == NAND_CMD_READ0) || 907 (command == NAND_CMD_RESET) || 908 (command == NAND_CMD_PARAM) || 909 (command == NAND_CMD_GET_FEATURES)) 910 /* wait until command is processed */ 911 nand_wait_ready(mtd); 912 } 913 914 /* 915 * zynq_nand_read_buf - read chip data into buffer 916 * @mtd: MTD device structure 917 * @buf: buffer to store date 918 * @len: number of bytes to read 919 */ 920 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) 921 { 922 struct nand_chip *chip = mtd->priv; 923 924 /* Make sure that buf is 32 bit aligned */ 925 if (((unsigned long)buf & 0x3) != 0) { 926 if (((unsigned long)buf & 0x1) != 0) { 927 if (len) { 928 *buf = readb(chip->IO_ADDR_R); 929 buf += 1; 930 len--; 931 } 932 } 933 934 if (((unsigned long)buf & 0x3) != 0) { 935 if (len >= 2) { 936 *(u16 *)buf = readw(chip->IO_ADDR_R); 937 buf += 2; 938 len -= 2; 939 } 940 } 941 } 942 943 /* copy aligned data */ 944 while (len >= 4) { 945 *(u32 *)buf = readl(chip->IO_ADDR_R); 946 buf += 4; 947 len -= 4; 948 } 949 950 /* mop up any remaining bytes */ 951 if (len) { 952 if (len >= 2) { 953 *(u16 *)buf = readw(chip->IO_ADDR_R); 954 buf += 2; 955 len -= 2; 956 } 957 if (len) 958 *buf = readb(chip->IO_ADDR_R); 959 } 960 } 961 962 /* 963 * zynq_nand_write_buf - write buffer to chip 964 * @mtd: MTD device structure 965 * @buf: data buffer 966 * @len: number of bytes to write 967 */ 968 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 969 { 970 struct nand_chip *chip = mtd->priv; 971 const u32 *nand = chip->IO_ADDR_W; 972 973 /* Make sure that buf is 32 bit aligned */ 974 if (((unsigned long)buf & 0x3) != 0) { 975 if (((unsigned long)buf & 0x1) != 0) { 976 if (len) { 977 writeb(*buf, nand); 978 buf += 1; 979 len--; 980 } 981 } 982 983 if (((unsigned long)buf & 0x3) != 0) { 984 if (len >= 2) { 985 writew(*(u16 *)buf, nand); 986 buf += 2; 987 len -= 2; 988 } 989 } 990 } 991 992 /* copy aligned data */ 993 while (len >= 4) { 994 writel(*(u32 *)buf, nand); 995 buf += 4; 996 len -= 4; 997 } 998 999 /* mop up any remaining bytes */ 1000 if (len) { 1001 if (len >= 2) { 1002 writew(*(u16 *)buf, nand); 1003 buf += 2; 1004 len -= 2; 1005 } 1006 1007 if (len) 1008 writeb(*buf, nand); 1009 } 1010 } 1011 1012 /* 1013 * zynq_nand_device_ready - Check device ready/busy line 1014 * @mtd: Pointer to the mtd_info structure 1015 * 1016 * returns: 0 on busy or 1 on ready state 1017 */ 1018 static int zynq_nand_device_ready(struct mtd_info *mtd) 1019 { 1020 u32 csr_val; 1021 1022 csr_val = readl(&zynq_nand_smc_base->csr); 1023 /* Check the raw_int_status1 bit */ 1024 if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) { 1025 /* Clear the interrupt condition */ 1026 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr); 1027 return 1; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static int zynq_nand_check_is_16bit_bw_flash(void) 1034 { 1035 int is_16bit_bw = NAND_BW_UNKNOWN; 1036 int mio_num_8bit = 0, mio_num_16bit = 0; 1037 1038 mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8"); 1039 if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) 1040 is_16bit_bw = NAND_BW_8BIT; 1041 1042 mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16"); 1043 if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT && 1044 mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT) 1045 is_16bit_bw = NAND_BW_16BIT; 1046 1047 return is_16bit_bw; 1048 } 1049 1050 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) 1051 { 1052 struct zynq_nand_info *xnand; 1053 struct mtd_info *mtd; 1054 unsigned long ecc_page_size; 1055 u8 maf_id, dev_id, i; 1056 u8 get_feature[4]; 1057 u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00}; 1058 unsigned long ecc_cfg; 1059 int ondie_ecc_enabled = 0; 1060 int err = -1; 1061 int is_16bit_bw; 1062 1063 xnand = calloc(1, sizeof(struct zynq_nand_info)); 1064 if (!xnand) { 1065 printf("%s: failed to allocate\n", __func__); 1066 goto fail; 1067 } 1068 1069 xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR; 1070 mtd = nand_to_mtd(nand_chip); 1071 1072 nand_chip->priv = xnand; 1073 mtd->priv = nand_chip; 1074 1075 /* Set address of NAND IO lines */ 1076 nand_chip->IO_ADDR_R = xnand->nand_base; 1077 nand_chip->IO_ADDR_W = xnand->nand_base; 1078 1079 /* Set the driver entry points for MTD */ 1080 nand_chip->cmdfunc = zynq_nand_cmd_function; 1081 nand_chip->dev_ready = zynq_nand_device_ready; 1082 nand_chip->select_chip = zynq_nand_select_chip; 1083 1084 /* If we don't set this delay driver sets 20us by default */ 1085 nand_chip->chip_delay = 30; 1086 1087 /* Buffer read/write routines */ 1088 nand_chip->read_buf = zynq_nand_read_buf; 1089 nand_chip->write_buf = zynq_nand_write_buf; 1090 1091 is_16bit_bw = zynq_nand_check_is_16bit_bw_flash(); 1092 if (is_16bit_bw == NAND_BW_UNKNOWN) { 1093 printf("%s: Unable detect NAND based on MIO settings\n", 1094 __func__); 1095 goto fail; 1096 } 1097 1098 if (is_16bit_bw == NAND_BW_16BIT) 1099 nand_chip->options = NAND_BUSWIDTH_16; 1100 1101 nand_chip->bbt_options = NAND_BBT_USE_FLASH; 1102 1103 /* Initialize the NAND flash interface on NAND controller */ 1104 if (zynq_nand_init_nand_flash(nand_chip->options) < 0) { 1105 printf("%s: nand flash init failed\n", __func__); 1106 goto fail; 1107 } 1108 1109 /* first scan to find the device and get the page size */ 1110 if (nand_scan_ident(mtd, 1, NULL)) { 1111 printf("%s: nand_scan_ident failed\n", __func__); 1112 goto fail; 1113 } 1114 /* Send the command for reading device ID */ 1115 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1116 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 1117 1118 /* Read manufacturer and device IDs */ 1119 maf_id = nand_chip->read_byte(mtd); 1120 dev_id = nand_chip->read_byte(mtd); 1121 1122 if ((maf_id == 0x2c) && ((dev_id == 0xf1) || 1123 (dev_id == 0xa1) || (dev_id == 0xb1) || 1124 (dev_id == 0xaa) || (dev_id == 0xba) || 1125 (dev_id == 0xda) || (dev_id == 0xca) || 1126 (dev_id == 0xac) || (dev_id == 0xbc) || 1127 (dev_id == 0xdc) || (dev_id == 0xcc) || 1128 (dev_id == 0xa3) || (dev_id == 0xb3) || 1129 (dev_id == 0xd3) || (dev_id == 0xc3))) { 1130 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, 1131 ONDIE_ECC_FEATURE_ADDR, -1); 1132 for (i = 0; i < 4; i++) 1133 writeb(set_feature[i], nand_chip->IO_ADDR_W); 1134 1135 /* Wait for 1us after writing data with SET_FEATURES command */ 1136 ndelay(1000); 1137 1138 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, 1139 ONDIE_ECC_FEATURE_ADDR, -1); 1140 nand_chip->read_buf(mtd, get_feature, 4); 1141 1142 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) { 1143 debug("%s: OnDie ECC flash\n", __func__); 1144 ondie_ecc_enabled = 1; 1145 } else { 1146 printf("%s: Unable to detect OnDie ECC\n", __func__); 1147 } 1148 } 1149 1150 if (ondie_ecc_enabled) { 1151 /* Bypass the controller ECC block */ 1152 ecc_cfg = readl(&zynq_nand_smc_base->emcr); 1153 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK; 1154 writel(ecc_cfg, &zynq_nand_smc_base->emcr); 1155 1156 /* The software ECC routines won't work 1157 * with the SMC controller 1158 */ 1159 nand_chip->ecc.mode = NAND_ECC_HW; 1160 nand_chip->ecc.strength = 1; 1161 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob; 1162 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw; 1163 nand_chip->ecc.write_page = zynq_nand_write_page_raw; 1164 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; 1165 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; 1166 nand_chip->ecc.read_oob = zynq_nand_read_oob; 1167 nand_chip->ecc.write_oob = zynq_nand_write_oob; 1168 nand_chip->ecc.size = mtd->writesize; 1169 nand_chip->ecc.bytes = 0; 1170 1171 /* NAND with on-die ECC supports subpage reads */ 1172 nand_chip->options |= NAND_SUBPAGE_READ; 1173 1174 /* On-Die ECC spare bytes offset 8 is used for ECC codes */ 1175 if (ondie_ecc_enabled) { 1176 nand_chip->ecc.layout = &ondie_nand_oob_64; 1177 /* Use the BBT pattern descriptors */ 1178 nand_chip->bbt_td = &bbt_main_descr; 1179 nand_chip->bbt_md = &bbt_mirror_descr; 1180 } 1181 } else { 1182 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ 1183 nand_chip->ecc.mode = NAND_ECC_HW; 1184 nand_chip->ecc.strength = 1; 1185 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE; 1186 nand_chip->ecc.bytes = 3; 1187 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc; 1188 nand_chip->ecc.correct = zynq_nand_correct_data; 1189 nand_chip->ecc.hwctl = NULL; 1190 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc; 1191 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc; 1192 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; 1193 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; 1194 nand_chip->ecc.read_oob = zynq_nand_read_oob; 1195 nand_chip->ecc.write_oob = zynq_nand_write_oob; 1196 1197 switch (mtd->writesize) { 1198 case 512: 1199 ecc_page_size = 0x1; 1200 /* Set the ECC memory config register */ 1201 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), 1202 &zynq_nand_smc_base->emcr); 1203 break; 1204 case 1024: 1205 ecc_page_size = 0x2; 1206 /* Set the ECC memory config register */ 1207 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), 1208 &zynq_nand_smc_base->emcr); 1209 break; 1210 case 2048: 1211 ecc_page_size = 0x3; 1212 /* Set the ECC memory config register */ 1213 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), 1214 &zynq_nand_smc_base->emcr); 1215 break; 1216 default: 1217 nand_chip->ecc.mode = NAND_ECC_SOFT; 1218 nand_chip->ecc.calculate = nand_calculate_ecc; 1219 nand_chip->ecc.correct = nand_correct_data; 1220 nand_chip->ecc.read_page = zynq_nand_read_page_swecc; 1221 nand_chip->ecc.write_page = zynq_nand_write_page_swecc; 1222 nand_chip->ecc.size = 256; 1223 break; 1224 } 1225 1226 if (mtd->oobsize == 16) 1227 nand_chip->ecc.layout = &nand_oob_16; 1228 else if (mtd->oobsize == 64) 1229 nand_chip->ecc.layout = &nand_oob_64; 1230 else 1231 printf("%s: No oob layout found\n", __func__); 1232 } 1233 1234 /* Second phase scan */ 1235 if (nand_scan_tail(mtd)) { 1236 printf("%s: nand_scan_tail failed\n", __func__); 1237 goto fail; 1238 } 1239 if (nand_register(devnum, mtd)) 1240 goto fail; 1241 return 0; 1242 fail: 1243 free(xnand); 1244 return err; 1245 } 1246 1247 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 1248 1249 void board_nand_init(void) 1250 { 1251 struct nand_chip *nand = &nand_chip[0]; 1252 1253 if (zynq_nand_init(nand, 0)) 1254 puts("ZYNQ NAND init failed\n"); 1255 } 1256