1 /* 2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others 3 * 4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. 5 * Ported to U-Boot by Stefan Agner 6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir 7 * Jason ported to M54418TWR and MVFA5. 8 * Authors: Stefan Agner <stefan.agner@toradex.com> 9 * Bill Pringlemeir <bpringlemeir@nbsps.com> 10 * Shaohui Xie <b21989@freescale.com> 11 * Jason Jin <Jason.jin@freescale.com> 12 * 13 * Based on original driver mpc5121_nfc.c. 14 * 15 * SPDX-License-Identifier: GPL-2.0+ 16 * 17 * Limitations: 18 * - Untested on MPC5125 and M54418. 19 * - DMA and pipelining not used. 20 * - 2K pages or less. 21 * - HW ECC: Only 2K page with 64+ OOB. 22 * - HW ECC: Only 24 and 32-bit error correction implemented. 23 */ 24 25 #include <common.h> 26 #include <malloc.h> 27 28 #include <linux/mtd/mtd.h> 29 #include <linux/mtd/rawnand.h> 30 #include <linux/mtd/partitions.h> 31 32 #include <nand.h> 33 #include <errno.h> 34 #include <asm/io.h> 35 #if CONFIG_NAND_VF610_NFC_DT 36 #include <dm.h> 37 #include <linux/io.h> 38 #include <linux/ioport.h> 39 #endif 40 41 /* Register Offsets */ 42 #define NFC_FLASH_CMD1 0x3F00 43 #define NFC_FLASH_CMD2 0x3F04 44 #define NFC_COL_ADDR 0x3F08 45 #define NFC_ROW_ADDR 0x3F0c 46 #define NFC_ROW_ADDR_INC 0x3F14 47 #define NFC_FLASH_STATUS1 0x3F18 48 #define NFC_FLASH_STATUS2 0x3F1c 49 #define NFC_CACHE_SWAP 0x3F28 50 #define NFC_SECTOR_SIZE 0x3F2c 51 #define NFC_FLASH_CONFIG 0x3F30 52 #define NFC_IRQ_STATUS 0x3F38 53 54 /* Addresses for NFC MAIN RAM BUFFER areas */ 55 #define NFC_MAIN_AREA(n) ((n) * 0x1000) 56 57 #define PAGE_2K 0x0800 58 #define OOB_64 0x0040 59 #define OOB_MAX 0x0100 60 61 /* 62 * NFC_CMD2[CODE] values. See section: 63 * - 31.4.7 Flash Command Code Description, Vybrid manual 64 * - 23.8.6 Flash Command Sequencer, MPC5125 manual 65 * 66 * Briefly these are bitmasks of controller cycles. 67 */ 68 #define READ_PAGE_CMD_CODE 0x7EE0 69 #define READ_ONFI_PARAM_CMD_CODE 0x4860 70 #define PROGRAM_PAGE_CMD_CODE 0x7FC0 71 #define ERASE_CMD_CODE 0x4EC0 72 #define READ_ID_CMD_CODE 0x4804 73 #define RESET_CMD_CODE 0x4040 74 #define STATUS_READ_CMD_CODE 0x4068 75 76 /* NFC ECC mode define */ 77 #define ECC_BYPASS 0 78 #define ECC_45_BYTE 6 79 #define ECC_60_BYTE 7 80 81 /*** Register Mask and bit definitions */ 82 83 /* NFC_FLASH_CMD1 Field */ 84 #define CMD_BYTE2_MASK 0xFF000000 85 #define CMD_BYTE2_SHIFT 24 86 87 /* NFC_FLASH_CM2 Field */ 88 #define CMD_BYTE1_MASK 0xFF000000 89 #define CMD_BYTE1_SHIFT 24 90 #define CMD_CODE_MASK 0x00FFFF00 91 #define CMD_CODE_SHIFT 8 92 #define BUFNO_MASK 0x00000006 93 #define BUFNO_SHIFT 1 94 #define START_BIT (1<<0) 95 96 /* NFC_COL_ADDR Field */ 97 #define COL_ADDR_MASK 0x0000FFFF 98 #define COL_ADDR_SHIFT 0 99 100 /* NFC_ROW_ADDR Field */ 101 #define ROW_ADDR_MASK 0x00FFFFFF 102 #define ROW_ADDR_SHIFT 0 103 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 104 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 105 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 106 #define ROW_ADDR_CHIP_SEL_SHIFT 24 107 108 /* NFC_FLASH_STATUS2 Field */ 109 #define STATUS_BYTE1_MASK 0x000000FF 110 111 /* NFC_FLASH_CONFIG Field */ 112 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 113 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22 114 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21) 115 #define CONFIG_DMA_REQ_BIT (1<<20) 116 #define CONFIG_ECC_MODE_MASK 0x000E0000 117 #define CONFIG_ECC_MODE_SHIFT 17 118 #define CONFIG_FAST_FLASH_BIT (1<<16) 119 #define CONFIG_16BIT (1<<7) 120 #define CONFIG_BOOT_MODE_BIT (1<<6) 121 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) 122 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) 123 #define CONFIG_PAGE_CNT_MASK 0xF 124 #define CONFIG_PAGE_CNT_SHIFT 0 125 126 /* NFC_IRQ_STATUS Field */ 127 #define IDLE_IRQ_BIT (1<<29) 128 #define IDLE_EN_BIT (1<<20) 129 #define CMD_DONE_CLEAR_BIT (1<<18) 130 #define IDLE_CLEAR_BIT (1<<17) 131 132 #define NFC_TIMEOUT (1000) 133 134 /* 135 * ECC status - seems to consume 8 bytes (double word). The documented 136 * status byte is located in the lowest byte of the second word (which is 137 * the 4th or 7th byte depending on endianness). 138 * Calculate an offset to store the ECC status at the end of the buffer. 139 */ 140 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8) 141 142 #define ECC_STATUS 0x4 143 #define ECC_STATUS_MASK 0x80 144 #define ECC_STATUS_ERR_COUNT 0x3F 145 146 enum vf610_nfc_alt_buf { 147 ALT_BUF_DATA = 0, 148 ALT_BUF_ID = 1, 149 ALT_BUF_STAT = 2, 150 ALT_BUF_ONFI = 3, 151 }; 152 153 struct vf610_nfc { 154 struct nand_chip chip; 155 void __iomem *regs; 156 uint buf_offset; 157 int write_sz; 158 /* Status and ID are in alternate locations. */ 159 enum vf610_nfc_alt_buf alt_buf; 160 }; 161 162 #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd)) 163 164 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) 165 #define ECC_HW_MODE ECC_45_BYTE 166 167 static struct nand_ecclayout vf610_nfc_ecc = { 168 .eccbytes = 45, 169 .eccpos = {19, 20, 21, 22, 23, 170 24, 25, 26, 27, 28, 29, 30, 31, 171 32, 33, 34, 35, 36, 37, 38, 39, 172 40, 41, 42, 43, 44, 45, 46, 47, 173 48, 49, 50, 51, 52, 53, 54, 55, 174 56, 57, 58, 59, 60, 61, 62, 63}, 175 .oobfree = { 176 {.offset = 2, 177 .length = 17} } 178 }; 179 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) 180 #define ECC_HW_MODE ECC_60_BYTE 181 182 static struct nand_ecclayout vf610_nfc_ecc = { 183 .eccbytes = 60, 184 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11, 185 12, 13, 14, 15, 16, 17, 18, 19, 186 20, 21, 22, 23, 24, 25, 26, 27, 187 28, 29, 30, 31, 32, 33, 34, 35, 188 36, 37, 38, 39, 40, 41, 42, 43, 189 44, 45, 46, 47, 48, 49, 50, 51, 190 52, 53, 54, 55, 56, 57, 58, 59, 191 60, 61, 62, 63 }, 192 .oobfree = { 193 {.offset = 2, 194 .length = 2} } 195 }; 196 #endif 197 198 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg) 199 { 200 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 201 202 return readl(nfc->regs + reg); 203 } 204 205 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val) 206 { 207 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 208 209 writel(val, nfc->regs + reg); 210 } 211 212 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits) 213 { 214 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits); 215 } 216 217 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits) 218 { 219 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits); 220 } 221 222 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg, 223 u32 mask, u32 shift, u32 val) 224 { 225 vf610_nfc_write(mtd, reg, 226 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift); 227 } 228 229 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) 230 { 231 /* 232 * Use this accessor for the internal SRAM buffers. On the ARM 233 * Freescale Vybrid SoC it's known that the driver can treat 234 * the SRAM buffer as if it's memory. Other platform might need 235 * to treat the buffers differently. 236 * 237 * For the time being, use memcpy 238 */ 239 memcpy(dst, src, n); 240 } 241 242 /* Clear flags for upcoming command */ 243 static inline void vf610_nfc_clear_status(void __iomem *regbase) 244 { 245 void __iomem *reg = regbase + NFC_IRQ_STATUS; 246 u32 tmp = __raw_readl(reg); 247 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; 248 __raw_writel(tmp, reg); 249 } 250 251 /* Wait for complete operation */ 252 static void vf610_nfc_done(struct mtd_info *mtd) 253 { 254 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 255 uint start; 256 257 /* 258 * Barrier is needed after this write. This write need 259 * to be done before reading the next register the first 260 * time. 261 * vf610_nfc_set implicates such a barrier by using writel 262 * to write to the register. 263 */ 264 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT); 265 266 start = get_timer(0); 267 268 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { 269 if (get_timer(start) > NFC_TIMEOUT) { 270 printf("Timeout while waiting for IDLE.\n"); 271 return; 272 } 273 } 274 vf610_nfc_clear_status(nfc->regs); 275 } 276 277 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col) 278 { 279 u32 flash_id; 280 281 if (col < 4) { 282 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1); 283 flash_id >>= (3 - col) * 8; 284 } else { 285 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2); 286 flash_id >>= 24; 287 } 288 289 return flash_id & 0xff; 290 } 291 292 static u8 vf610_nfc_get_status(struct mtd_info *mtd) 293 { 294 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; 295 } 296 297 /* Single command */ 298 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, 299 u32 cmd_code) 300 { 301 void __iomem *reg = regbase + NFC_FLASH_CMD2; 302 u32 tmp; 303 vf610_nfc_clear_status(regbase); 304 305 tmp = __raw_readl(reg); 306 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); 307 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; 308 tmp |= cmd_code << CMD_CODE_SHIFT; 309 __raw_writel(tmp, reg); 310 } 311 312 /* Two commands */ 313 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, 314 u32 cmd_byte2, u32 cmd_code) 315 { 316 void __iomem *reg = regbase + NFC_FLASH_CMD1; 317 u32 tmp; 318 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); 319 320 tmp = __raw_readl(reg); 321 tmp &= ~CMD_BYTE2_MASK; 322 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; 323 __raw_writel(tmp, reg); 324 } 325 326 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) 327 { 328 if (column != -1) { 329 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 330 if (nfc->chip.options & NAND_BUSWIDTH_16) 331 column = column / 2; 332 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK, 333 COL_ADDR_SHIFT, column); 334 } 335 if (page != -1) 336 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 337 ROW_ADDR_SHIFT, page); 338 } 339 340 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode) 341 { 342 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, 343 CONFIG_ECC_MODE_MASK, 344 CONFIG_ECC_MODE_SHIFT, ecc_mode); 345 } 346 347 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) 348 { 349 __raw_writel(size, regbase + NFC_SECTOR_SIZE); 350 } 351 352 /* Send command to NAND chip */ 353 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, 354 int column, int page) 355 { 356 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 357 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; 358 359 nfc->buf_offset = max(column, 0); 360 nfc->alt_buf = ALT_BUF_DATA; 361 362 switch (command) { 363 case NAND_CMD_SEQIN: 364 /* Use valid column/page from preread... */ 365 vf610_nfc_addr_cycle(mtd, column, page); 366 nfc->buf_offset = 0; 367 368 /* 369 * SEQIN => data => PAGEPROG sequence is done by the controller 370 * hence we do not need to issue the command here... 371 */ 372 return; 373 case NAND_CMD_PAGEPROG: 374 trfr_sz += nfc->write_sz; 375 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); 376 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 377 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, 378 command, PROGRAM_PAGE_CMD_CODE); 379 break; 380 381 case NAND_CMD_RESET: 382 vf610_nfc_transfer_size(nfc->regs, 0); 383 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); 384 break; 385 386 case NAND_CMD_READOOB: 387 trfr_sz += mtd->oobsize; 388 column = mtd->writesize; 389 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 390 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, 391 NAND_CMD_READSTART, READ_PAGE_CMD_CODE); 392 vf610_nfc_addr_cycle(mtd, column, page); 393 vf610_nfc_ecc_mode(mtd, ECC_BYPASS); 394 break; 395 396 case NAND_CMD_READ0: 397 trfr_sz += mtd->writesize + mtd->oobsize; 398 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 399 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); 400 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, 401 NAND_CMD_READSTART, READ_PAGE_CMD_CODE); 402 vf610_nfc_addr_cycle(mtd, column, page); 403 break; 404 405 case NAND_CMD_PARAM: 406 nfc->alt_buf = ALT_BUF_ONFI; 407 trfr_sz = 3 * sizeof(struct nand_onfi_params); 408 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 409 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM, 410 READ_ONFI_PARAM_CMD_CODE); 411 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 412 ROW_ADDR_SHIFT, column); 413 vf610_nfc_ecc_mode(mtd, ECC_BYPASS); 414 break; 415 416 case NAND_CMD_ERASE1: 417 vf610_nfc_transfer_size(nfc->regs, 0); 418 vf610_nfc_send_commands(nfc->regs, command, 419 NAND_CMD_ERASE2, ERASE_CMD_CODE); 420 vf610_nfc_addr_cycle(mtd, column, page); 421 break; 422 423 case NAND_CMD_READID: 424 nfc->alt_buf = ALT_BUF_ID; 425 nfc->buf_offset = 0; 426 vf610_nfc_transfer_size(nfc->regs, 0); 427 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); 428 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 429 ROW_ADDR_SHIFT, column); 430 break; 431 432 case NAND_CMD_STATUS: 433 nfc->alt_buf = ALT_BUF_STAT; 434 vf610_nfc_transfer_size(nfc->regs, 0); 435 vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE); 436 break; 437 default: 438 return; 439 } 440 441 vf610_nfc_done(mtd); 442 443 nfc->write_sz = 0; 444 } 445 446 /* Read data from NFC buffers */ 447 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) 448 { 449 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 450 uint c = nfc->buf_offset; 451 452 /* Alternate buffers are only supported through read_byte */ 453 if (nfc->alt_buf) 454 return; 455 456 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); 457 458 nfc->buf_offset += len; 459 } 460 461 /* Write data to NFC buffers */ 462 static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, 463 int len) 464 { 465 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 466 uint c = nfc->buf_offset; 467 uint l; 468 469 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); 470 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); 471 472 nfc->write_sz += l; 473 nfc->buf_offset += l; 474 } 475 476 /* Read byte from NFC buffers */ 477 static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) 478 { 479 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 480 u8 tmp; 481 uint c = nfc->buf_offset; 482 483 switch (nfc->alt_buf) { 484 case ALT_BUF_ID: 485 tmp = vf610_nfc_get_id(mtd, c); 486 break; 487 case ALT_BUF_STAT: 488 tmp = vf610_nfc_get_status(mtd); 489 break; 490 #ifdef __LITTLE_ENDIAN 491 case ALT_BUF_ONFI: 492 /* Reverse byte since the controller uses big endianness */ 493 c = nfc->buf_offset ^ 0x3; 494 /* fall-through */ 495 #endif 496 default: 497 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); 498 break; 499 } 500 nfc->buf_offset++; 501 return tmp; 502 } 503 504 /* Read word from NFC buffers */ 505 static u16 vf610_nfc_read_word(struct mtd_info *mtd) 506 { 507 u16 tmp; 508 509 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); 510 return tmp; 511 } 512 513 /* If not provided, upper layers apply a fixed delay. */ 514 static int vf610_nfc_dev_ready(struct mtd_info *mtd) 515 { 516 /* NFC handles R/B internally; always ready. */ 517 return 1; 518 } 519 520 /* 521 * This function supports Vybrid only (MPC5125 would have full RB and four CS) 522 */ 523 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) 524 { 525 #ifdef CONFIG_VF610 526 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR); 527 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); 528 529 if (chip >= 0) { 530 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; 531 tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT; 532 } 533 534 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp); 535 #endif 536 } 537 538 /* Count the number of 0's in buff upto max_bits */ 539 static inline int count_written_bits(uint8_t *buff, int size, int max_bits) 540 { 541 uint32_t *buff32 = (uint32_t *)buff; 542 int k, written_bits = 0; 543 544 for (k = 0; k < (size / 4); k++) { 545 written_bits += hweight32(~buff32[k]); 546 if (written_bits > max_bits) 547 break; 548 } 549 550 return written_bits; 551 } 552 553 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat, 554 uint8_t *oob, int page) 555 { 556 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 557 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS; 558 u8 ecc_status; 559 u8 ecc_count; 560 int flips; 561 int flips_threshold = nfc->chip.ecc.strength / 2; 562 563 ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff; 564 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT; 565 566 if (!(ecc_status & ECC_STATUS_MASK)) 567 return ecc_count; 568 569 /* Read OOB without ECC unit enabled */ 570 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page); 571 vf610_nfc_read_buf(mtd, oob, mtd->oobsize); 572 573 /* 574 * On an erased page, bit count (including OOB) should be zero or 575 * at least less then half of the ECC strength. 576 */ 577 flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold); 578 flips += count_written_bits(oob, mtd->oobsize, flips_threshold); 579 580 if (unlikely(flips > flips_threshold)) 581 return -EINVAL; 582 583 /* Erased page. */ 584 memset(dat, 0xff, nfc->chip.ecc.size); 585 memset(oob, 0xff, mtd->oobsize); 586 return flips; 587 } 588 589 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, 590 uint8_t *buf, int oob_required, int page) 591 { 592 int eccsize = chip->ecc.size; 593 int stat; 594 595 vf610_nfc_read_buf(mtd, buf, eccsize); 596 if (oob_required) 597 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 598 599 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page); 600 601 if (stat < 0) { 602 mtd->ecc_stats.failed++; 603 return 0; 604 } else { 605 mtd->ecc_stats.corrected += stat; 606 return stat; 607 } 608 } 609 610 /* 611 * ECC will be calculated automatically 612 */ 613 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 614 const uint8_t *buf, int oob_required, int page) 615 { 616 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 617 618 vf610_nfc_write_buf(mtd, buf, mtd->writesize); 619 if (oob_required) 620 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 621 622 /* Always write whole page including OOB due to HW ECC */ 623 nfc->write_sz = mtd->writesize + mtd->oobsize; 624 625 return 0; 626 } 627 628 struct vf610_nfc_config { 629 int hardware_ecc; 630 int width; 631 int flash_bbt; 632 }; 633 634 static int vf610_nfc_nand_init(int devnum, void __iomem *addr) 635 { 636 struct mtd_info *mtd; 637 struct nand_chip *chip; 638 struct vf610_nfc *nfc; 639 int err = 0; 640 struct vf610_nfc_config cfg = { 641 .hardware_ecc = 1, 642 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 643 .width = 16, 644 #else 645 .width = 8, 646 #endif 647 .flash_bbt = 1, 648 }; 649 650 nfc = calloc(1, sizeof(*nfc)); 651 if (!nfc) { 652 printf(KERN_ERR "%s: Memory exhausted!\n", __func__); 653 return -ENOMEM; 654 } 655 656 chip = &nfc->chip; 657 nfc->regs = addr; 658 659 mtd = nand_to_mtd(chip); 660 nand_set_controller_data(chip, nfc); 661 662 if (cfg.width == 16) 663 chip->options |= NAND_BUSWIDTH_16; 664 665 chip->dev_ready = vf610_nfc_dev_ready; 666 chip->cmdfunc = vf610_nfc_command; 667 chip->read_byte = vf610_nfc_read_byte; 668 chip->read_word = vf610_nfc_read_word; 669 chip->read_buf = vf610_nfc_read_buf; 670 chip->write_buf = vf610_nfc_write_buf; 671 chip->select_chip = vf610_nfc_select_chip; 672 673 chip->options |= NAND_NO_SUBPAGE_WRITE; 674 675 chip->ecc.size = PAGE_2K; 676 677 /* Set configuration register. */ 678 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); 679 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); 680 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); 681 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); 682 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); 683 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); 684 685 /* Disable virtual pages, only one elementary transfer unit */ 686 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, 687 CONFIG_PAGE_CNT_SHIFT, 1); 688 689 /* first scan to find the device and get the page size */ 690 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { 691 err = -ENXIO; 692 goto error; 693 } 694 695 if (cfg.width == 16) 696 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); 697 698 /* Bad block options. */ 699 if (cfg.flash_bbt) 700 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB | 701 NAND_BBT_CREATE; 702 703 /* Single buffer only, max 256 OOB minus ECC status */ 704 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) { 705 dev_err(nfc->dev, "Unsupported flash page size\n"); 706 err = -ENXIO; 707 goto error; 708 } 709 710 if (cfg.hardware_ecc) { 711 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { 712 dev_err(nfc->dev, "Unsupported flash with hwecc\n"); 713 err = -ENXIO; 714 goto error; 715 } 716 717 if (chip->ecc.size != mtd->writesize) { 718 dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size); 719 dev_err(nfc->dev, "Step size needs to be page size\n"); 720 err = -ENXIO; 721 goto error; 722 } 723 724 /* Current HW ECC layouts only use 64 bytes of OOB */ 725 if (mtd->oobsize > 64) 726 mtd->oobsize = 64; 727 728 /* propagate ecc.layout to mtd_info */ 729 mtd->ecclayout = chip->ecc.layout; 730 chip->ecc.read_page = vf610_nfc_read_page; 731 chip->ecc.write_page = vf610_nfc_write_page; 732 chip->ecc.mode = NAND_ECC_HW; 733 734 chip->ecc.size = PAGE_2K; 735 chip->ecc.layout = &vf610_nfc_ecc; 736 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) 737 chip->ecc.strength = 24; 738 chip->ecc.bytes = 45; 739 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) 740 chip->ecc.strength = 32; 741 chip->ecc.bytes = 60; 742 #endif 743 744 /* Set ECC_STATUS offset */ 745 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, 746 CONFIG_ECC_SRAM_ADDR_MASK, 747 CONFIG_ECC_SRAM_ADDR_SHIFT, 748 ECC_SRAM_ADDR >> 3); 749 750 /* Enable ECC status in SRAM */ 751 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); 752 } 753 754 /* second phase scan */ 755 err = nand_scan_tail(mtd); 756 if (err) 757 return err; 758 759 err = nand_register(devnum, mtd); 760 if (err) 761 return err; 762 763 return 0; 764 765 error: 766 return err; 767 } 768 769 #if CONFIG_NAND_VF610_NFC_DT 770 static const struct udevice_id vf610_nfc_dt_ids[] = { 771 { 772 .compatible = "fsl,vf610-nfc", 773 }, 774 { /* sentinel */ } 775 }; 776 777 static int vf610_nfc_dt_probe(struct udevice *dev) 778 { 779 struct resource res; 780 int ret; 781 782 ret = dev_read_resource(dev, 0, &res); 783 if (ret) 784 return ret; 785 786 return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start, 787 resource_size(&res))); 788 } 789 790 U_BOOT_DRIVER(vf610_nfc_dt) = { 791 .name = "vf610-nfc-dt", 792 .id = UCLASS_MTD, 793 .of_match = vf610_nfc_dt_ids, 794 .probe = vf610_nfc_dt_probe, 795 }; 796 797 void board_nand_init(void) 798 { 799 struct udevice *dev; 800 int ret; 801 802 ret = uclass_get_device_by_driver(UCLASS_MTD, 803 DM_GET_DRIVER(vf610_nfc_dt), 804 &dev); 805 if (ret && ret != -ENODEV) 806 pr_err("Failed to initialize NAND controller. (error %d)\n", 807 ret); 808 } 809 #else 810 void board_nand_init(void) 811 { 812 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); 813 if (err) 814 printf("VF610 NAND init failed (err %d)\n", err); 815 } 816 #endif /* CONFIG_NAND_VF610_NFC_DT */ 817