1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> 4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de 5 * (C) Copyright 2006 DENX Software Engineering 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <memalign.h> 13 #include <nand.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/funcmux.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <linux/errno.h> 18 #include <asm/gpio.h> 19 #include <fdtdec.h> 20 #include <bouncebuf.h> 21 #include <dm.h> 22 #include "tegra_nand.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define NAND_CMD_TIMEOUT_MS 10 27 28 #define SKIPPED_SPARE_BYTES 4 29 30 /* ECC bytes to be generated for tag data */ 31 #define TAG_ECC_BYTES 4 32 33 static const struct udevice_id tegra_nand_dt_ids[] = { 34 { 35 .compatible = "nvidia,tegra20-nand", 36 }, 37 { /* sentinel */ } 38 }; 39 40 /* 64 byte oob block info for large page (== 2KB) device 41 * 42 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC: 43 * Skipped bytes(4) 44 * Main area Ecc(36) 45 * Tag data(20) 46 * Tag data Ecc(4) 47 * 48 * Yaffs2 will use 16 tag bytes. 49 */ 50 static struct nand_ecclayout eccoob = { 51 .eccbytes = 36, 52 .eccpos = { 53 4, 5, 6, 7, 8, 9, 10, 11, 12, 54 13, 14, 15, 16, 17, 18, 19, 20, 21, 55 22, 23, 24, 25, 26, 27, 28, 29, 30, 56 31, 32, 33, 34, 35, 36, 37, 38, 39, 57 }, 58 .oobavail = 20, 59 .oobfree = { 60 { 61 .offset = 40, 62 .length = 20, 63 }, 64 } 65 }; 66 67 enum { 68 ECC_OK, 69 ECC_TAG_ERROR = 1 << 0, 70 ECC_DATA_ERROR = 1 << 1 71 }; 72 73 /* Timing parameters */ 74 enum { 75 FDT_NAND_MAX_TRP_TREA, 76 FDT_NAND_TWB, 77 FDT_NAND_MAX_TCR_TAR_TRR, 78 FDT_NAND_TWHR, 79 FDT_NAND_MAX_TCS_TCH_TALS_TALH, 80 FDT_NAND_TWH, 81 FDT_NAND_TWP, 82 FDT_NAND_TRH, 83 FDT_NAND_TADL, 84 85 FDT_NAND_TIMING_COUNT 86 }; 87 88 /* Information about an attached NAND chip */ 89 struct fdt_nand { 90 struct nand_ctlr *reg; 91 int enabled; /* 1 to enable, 0 to disable */ 92 struct gpio_desc wp_gpio; /* write-protect GPIO */ 93 s32 width; /* bit width, normally 8 */ 94 u32 timing[FDT_NAND_TIMING_COUNT]; 95 }; 96 97 struct nand_drv { 98 struct nand_ctlr *reg; 99 struct fdt_nand config; 100 }; 101 102 struct tegra_nand_info { 103 struct udevice *dev; 104 struct nand_drv nand_ctrl; 105 struct nand_chip nand_chip; 106 }; 107 108 /** 109 * Wait for command completion 110 * 111 * @param reg nand_ctlr structure 112 * @return 113 * 1 - Command completed 114 * 0 - Timeout 115 */ 116 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg) 117 { 118 u32 reg_val; 119 int running; 120 int i; 121 122 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) { 123 if ((readl(®->command) & CMD_GO) || 124 !(readl(®->status) & STATUS_RBSY0) || 125 !(readl(®->isr) & ISR_IS_CMD_DONE)) { 126 udelay(1); 127 continue; 128 } 129 reg_val = readl(®->dma_mst_ctrl); 130 /* 131 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE 132 * is set, that means DMA engine is running. 133 * 134 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE 135 * is cleared, indicating DMA transfer completion. 136 */ 137 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | 138 DMA_MST_CTRL_EN_B_ENABLE); 139 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) 140 return 1; 141 udelay(1); 142 } 143 return 0; 144 } 145 146 /** 147 * Read one byte from the chip 148 * 149 * @param mtd MTD device structure 150 * @return data byte 151 * 152 * Read function for 8bit bus-width 153 */ 154 static uint8_t read_byte(struct mtd_info *mtd) 155 { 156 struct nand_chip *chip = mtd_to_nand(mtd); 157 struct nand_drv *info; 158 159 info = (struct nand_drv *)nand_get_controller_data(chip); 160 161 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID, 162 &info->reg->command); 163 if (!nand_waitfor_cmd_completion(info->reg)) 164 printf("Command timeout\n"); 165 166 return (uint8_t)readl(&info->reg->resp); 167 } 168 169 /** 170 * Read len bytes from the chip into a buffer 171 * 172 * @param mtd MTD device structure 173 * @param buf buffer to store data to 174 * @param len number of bytes to read 175 * 176 * Read function for 8bit bus-width 177 */ 178 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 179 { 180 int i, s; 181 unsigned int reg; 182 struct nand_chip *chip = mtd_to_nand(mtd); 183 struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip); 184 185 for (i = 0; i < len; i += 4) { 186 s = (len - i) > 4 ? 4 : len - i; 187 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 | 188 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO, 189 &info->reg->command); 190 if (!nand_waitfor_cmd_completion(info->reg)) 191 puts("Command timeout during read_buf\n"); 192 reg = readl(&info->reg->resp); 193 memcpy(buf + i, ®, s); 194 } 195 } 196 197 /** 198 * Check NAND status to see if it is ready or not 199 * 200 * @param mtd MTD device structure 201 * @return 202 * 1 - ready 203 * 0 - not ready 204 */ 205 static int nand_dev_ready(struct mtd_info *mtd) 206 { 207 struct nand_chip *chip = mtd_to_nand(mtd); 208 int reg_val; 209 struct nand_drv *info; 210 211 info = (struct nand_drv *)nand_get_controller_data(chip); 212 213 reg_val = readl(&info->reg->status); 214 if (reg_val & STATUS_RBSY0) 215 return 1; 216 else 217 return 0; 218 } 219 220 /* Dummy implementation: we don't support multiple chips */ 221 static void nand_select_chip(struct mtd_info *mtd, int chipnr) 222 { 223 switch (chipnr) { 224 case -1: 225 case 0: 226 break; 227 228 default: 229 BUG(); 230 } 231 } 232 233 /** 234 * Clear all interrupt status bits 235 * 236 * @param reg nand_ctlr structure 237 */ 238 static void nand_clear_interrupt_status(struct nand_ctlr *reg) 239 { 240 u32 reg_val; 241 242 /* Clear interrupt status */ 243 reg_val = readl(®->isr); 244 writel(reg_val, ®->isr); 245 } 246 247 /** 248 * Send command to NAND device 249 * 250 * @param mtd MTD device structure 251 * @param command the command to be sent 252 * @param column the column address for this command, -1 if none 253 * @param page_addr the page address for this command, -1 if none 254 */ 255 static void nand_command(struct mtd_info *mtd, unsigned int command, 256 int column, int page_addr) 257 { 258 struct nand_chip *chip = mtd_to_nand(mtd); 259 struct nand_drv *info; 260 261 info = (struct nand_drv *)nand_get_controller_data(chip); 262 263 /* 264 * Write out the command to the device. 265 * 266 * Only command NAND_CMD_RESET or NAND_CMD_READID will come 267 * here before mtd->writesize is initialized. 268 */ 269 270 /* Emulate NAND_CMD_READOOB */ 271 if (command == NAND_CMD_READOOB) { 272 assert(mtd->writesize != 0); 273 column += mtd->writesize; 274 command = NAND_CMD_READ0; 275 } 276 277 /* Adjust columns for 16 bit bus-width */ 278 if (column != -1 && (chip->options & NAND_BUSWIDTH_16)) 279 column >>= 1; 280 281 nand_clear_interrupt_status(info->reg); 282 283 /* Stop DMA engine, clear DMA completion status */ 284 writel(DMA_MST_CTRL_EN_A_DISABLE 285 | DMA_MST_CTRL_EN_B_DISABLE 286 | DMA_MST_CTRL_IS_DMA_DONE, 287 &info->reg->dma_mst_ctrl); 288 289 /* 290 * Program and erase have their own busy handlers 291 * status and sequential in needs no delay 292 */ 293 switch (command) { 294 case NAND_CMD_READID: 295 writel(NAND_CMD_READID, &info->reg->cmd_reg1); 296 writel(column & 0xFF, &info->reg->addr_reg1); 297 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, 298 &info->reg->command); 299 break; 300 case NAND_CMD_PARAM: 301 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1); 302 writel(column & 0xFF, &info->reg->addr_reg1); 303 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, 304 &info->reg->command); 305 break; 306 case NAND_CMD_READ0: 307 writel(NAND_CMD_READ0, &info->reg->cmd_reg1); 308 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2); 309 writel((page_addr << 16) | (column & 0xFFFF), 310 &info->reg->addr_reg1); 311 writel(page_addr >> 16, &info->reg->addr_reg2); 312 return; 313 case NAND_CMD_SEQIN: 314 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1); 315 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2); 316 writel((page_addr << 16) | (column & 0xFFFF), 317 &info->reg->addr_reg1); 318 writel(page_addr >> 16, 319 &info->reg->addr_reg2); 320 return; 321 case NAND_CMD_PAGEPROG: 322 return; 323 case NAND_CMD_ERASE1: 324 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1); 325 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2); 326 writel(page_addr, &info->reg->addr_reg1); 327 writel(CMD_GO | CMD_CLE | CMD_ALE | 328 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3, 329 &info->reg->command); 330 break; 331 case NAND_CMD_ERASE2: 332 return; 333 case NAND_CMD_STATUS: 334 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1); 335 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX 336 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT) 337 | CMD_CE0, 338 &info->reg->command); 339 break; 340 case NAND_CMD_RESET: 341 writel(NAND_CMD_RESET, &info->reg->cmd_reg1); 342 writel(CMD_GO | CMD_CLE | CMD_CE0, 343 &info->reg->command); 344 break; 345 case NAND_CMD_RNDOUT: 346 default: 347 printf("%s: Unsupported command %d\n", __func__, command); 348 return; 349 } 350 if (!nand_waitfor_cmd_completion(info->reg)) 351 printf("Command 0x%02X timeout\n", command); 352 } 353 354 /** 355 * Check whether the pointed buffer are all 0xff (blank). 356 * 357 * @param buf data buffer for blank check 358 * @param len length of the buffer in byte 359 * @return 360 * 1 - blank 361 * 0 - non-blank 362 */ 363 static int blank_check(u8 *buf, int len) 364 { 365 int i; 366 367 for (i = 0; i < len; i++) 368 if (buf[i] != 0xFF) 369 return 0; 370 return 1; 371 } 372 373 /** 374 * After a DMA transfer for read, we call this function to see whether there 375 * is any uncorrectable error on the pointed data buffer or oob buffer. 376 * 377 * @param reg nand_ctlr structure 378 * @param databuf data buffer 379 * @param a_len data buffer length 380 * @param oobbuf oob buffer 381 * @param b_len oob buffer length 382 * @return 383 * ECC_OK - no ECC error or correctable ECC error 384 * ECC_TAG_ERROR - uncorrectable tag ECC error 385 * ECC_DATA_ERROR - uncorrectable data ECC error 386 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error 387 */ 388 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf, 389 int a_len, u8 *oobbuf, int b_len) 390 { 391 int return_val = ECC_OK; 392 u32 reg_val; 393 394 if (!(readl(®->isr) & ISR_IS_ECC_ERR)) 395 return ECC_OK; 396 397 /* 398 * Area A is used for the data block (databuf). Area B is used for 399 * the spare block (oobbuf) 400 */ 401 reg_val = readl(®->dec_status); 402 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) { 403 reg_val = readl(®->bch_dec_status_buf); 404 /* 405 * If uncorrectable error occurs on data area, then see whether 406 * they are all FF. If all are FF, it's a blank page. 407 * Not error. 408 */ 409 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) && 410 !blank_check(databuf, a_len)) 411 return_val |= ECC_DATA_ERROR; 412 } 413 414 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) { 415 reg_val = readl(®->bch_dec_status_buf); 416 /* 417 * If uncorrectable error occurs on tag area, then see whether 418 * they are all FF. If all are FF, it's a blank page. 419 * Not error. 420 */ 421 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) && 422 !blank_check(oobbuf, b_len)) 423 return_val |= ECC_TAG_ERROR; 424 } 425 426 return return_val; 427 } 428 429 /** 430 * Set GO bit to send command to device 431 * 432 * @param reg nand_ctlr structure 433 */ 434 static void start_command(struct nand_ctlr *reg) 435 { 436 u32 reg_val; 437 438 reg_val = readl(®->command); 439 reg_val |= CMD_GO; 440 writel(reg_val, ®->command); 441 } 442 443 /** 444 * Clear command GO bit, DMA GO bit, and DMA completion status 445 * 446 * @param reg nand_ctlr structure 447 */ 448 static void stop_command(struct nand_ctlr *reg) 449 { 450 /* Stop command */ 451 writel(0, ®->command); 452 453 /* Stop DMA engine and clear DMA completion status */ 454 writel(DMA_MST_CTRL_GO_DISABLE 455 | DMA_MST_CTRL_IS_DMA_DONE, 456 ®->dma_mst_ctrl); 457 } 458 459 /** 460 * Set up NAND bus width and page size 461 * 462 * @param info nand_info structure 463 * @param *reg_val address of reg_val 464 * @return 0 if ok, -1 on error 465 */ 466 static int set_bus_width_page_size(struct mtd_info *our_mtd, 467 struct fdt_nand *config, u32 *reg_val) 468 { 469 if (config->width == 8) 470 *reg_val = CFG_BUS_WIDTH_8BIT; 471 else if (config->width == 16) 472 *reg_val = CFG_BUS_WIDTH_16BIT; 473 else { 474 debug("%s: Unsupported bus width %d\n", __func__, 475 config->width); 476 return -1; 477 } 478 479 if (our_mtd->writesize == 512) 480 *reg_val |= CFG_PAGE_SIZE_512; 481 else if (our_mtd->writesize == 2048) 482 *reg_val |= CFG_PAGE_SIZE_2048; 483 else if (our_mtd->writesize == 4096) 484 *reg_val |= CFG_PAGE_SIZE_4096; 485 else { 486 debug("%s: Unsupported page size %d\n", __func__, 487 our_mtd->writesize); 488 return -1; 489 } 490 491 return 0; 492 } 493 494 /** 495 * Page read/write function 496 * 497 * @param mtd mtd info structure 498 * @param chip nand chip info structure 499 * @param buf data buffer 500 * @param page page number 501 * @param with_ecc 1 to enable ECC, 0 to disable ECC 502 * @param is_writing 0 for read, 1 for write 503 * @return 0 when successfully completed 504 * -EIO when command timeout 505 */ 506 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip, 507 uint8_t *buf, int page, int with_ecc, int is_writing) 508 { 509 u32 reg_val; 510 int tag_size; 511 struct nand_oobfree *free = chip->ecc.layout->oobfree; 512 /* 4*128=512 (byte) is the value that our HW can support. */ 513 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128); 514 char *tag_ptr; 515 struct nand_drv *info; 516 struct fdt_nand *config; 517 unsigned int bbflags; 518 struct bounce_buffer bbstate, bbstate_oob; 519 520 if ((uintptr_t)buf & 0x03) { 521 printf("buf %p has to be 4-byte aligned\n", buf); 522 return -EINVAL; 523 } 524 525 info = (struct nand_drv *)nand_get_controller_data(chip); 526 config = &info->config; 527 if (set_bus_width_page_size(mtd, config, ®_val)) 528 return -EINVAL; 529 530 /* Need to be 4-byte aligned */ 531 tag_ptr = (char *)tag_buf; 532 533 stop_command(info->reg); 534 535 if (is_writing) 536 bbflags = GEN_BB_READ; 537 else 538 bbflags = GEN_BB_WRITE; 539 540 bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift, 541 bbflags); 542 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a); 543 writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr); 544 545 /* Set ECC selection, configure ECC settings */ 546 if (with_ecc) { 547 if (is_writing) 548 memcpy(tag_ptr, chip->oob_poi + free->offset, 549 chip->ecc.layout->oobavail + TAG_ECC_BYTES); 550 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES; 551 reg_val |= (CFG_SKIP_SPARE_SEL_4 552 | CFG_SKIP_SPARE_ENABLE 553 | CFG_HW_ECC_CORRECTION_ENABLE 554 | CFG_ECC_EN_TAG_DISABLE 555 | CFG_HW_ECC_SEL_RS 556 | CFG_HW_ECC_ENABLE 557 | CFG_TVAL4 558 | (tag_size - 1)); 559 560 if (!is_writing) 561 tag_size += SKIPPED_SPARE_BYTES; 562 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size, 563 bbflags); 564 } else { 565 tag_size = mtd->oobsize; 566 reg_val |= (CFG_SKIP_SPARE_DISABLE 567 | CFG_HW_ECC_CORRECTION_DISABLE 568 | CFG_ECC_EN_TAG_DISABLE 569 | CFG_HW_ECC_DISABLE 570 | (tag_size - 1)); 571 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, 572 tag_size, bbflags); 573 } 574 writel(reg_val, &info->reg->config); 575 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr); 576 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config); 577 writel(tag_size - 1, &info->reg->dma_cfg_b); 578 579 nand_clear_interrupt_status(info->reg); 580 581 reg_val = CMD_CLE | CMD_ALE 582 | CMD_SEC_CMD 583 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT) 584 | CMD_A_VALID 585 | CMD_B_VALID 586 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT) 587 | CMD_CE0; 588 if (!is_writing) 589 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); 590 else 591 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); 592 writel(reg_val, &info->reg->command); 593 594 /* Setup DMA engine */ 595 reg_val = DMA_MST_CTRL_GO_ENABLE 596 | DMA_MST_CTRL_BURST_8WORDS 597 | DMA_MST_CTRL_EN_A_ENABLE 598 | DMA_MST_CTRL_EN_B_ENABLE; 599 600 if (!is_writing) 601 reg_val |= DMA_MST_CTRL_DIR_READ; 602 else 603 reg_val |= DMA_MST_CTRL_DIR_WRITE; 604 605 writel(reg_val, &info->reg->dma_mst_ctrl); 606 607 start_command(info->reg); 608 609 if (!nand_waitfor_cmd_completion(info->reg)) { 610 if (!is_writing) 611 printf("Read Page 0x%X timeout ", page); 612 else 613 printf("Write Page 0x%X timeout ", page); 614 if (with_ecc) 615 printf("with ECC"); 616 else 617 printf("without ECC"); 618 printf("\n"); 619 return -EIO; 620 } 621 622 bounce_buffer_stop(&bbstate_oob); 623 bounce_buffer_stop(&bbstate); 624 625 if (with_ecc && !is_writing) { 626 memcpy(chip->oob_poi, tag_ptr, 627 SKIPPED_SPARE_BYTES); 628 memcpy(chip->oob_poi + free->offset, 629 tag_ptr + SKIPPED_SPARE_BYTES, 630 chip->ecc.layout->oobavail); 631 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf, 632 1 << chip->page_shift, 633 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES), 634 chip->ecc.layout->oobavail); 635 if (reg_val & ECC_TAG_ERROR) 636 printf("Read Page 0x%X tag ECC error\n", page); 637 if (reg_val & ECC_DATA_ERROR) 638 printf("Read Page 0x%X data ECC error\n", 639 page); 640 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR)) 641 return -EIO; 642 } 643 return 0; 644 } 645 646 /** 647 * Hardware ecc based page read function 648 * 649 * @param mtd mtd info structure 650 * @param chip nand chip info structure 651 * @param buf buffer to store read data 652 * @param page page number to read 653 * @return 0 when successfully completed 654 * -EIO when command timeout 655 */ 656 static int nand_read_page_hwecc(struct mtd_info *mtd, 657 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 658 { 659 return nand_rw_page(mtd, chip, buf, page, 1, 0); 660 } 661 662 /** 663 * Hardware ecc based page write function 664 * 665 * @param mtd mtd info structure 666 * @param chip nand chip info structure 667 * @param buf data buffer 668 */ 669 static int nand_write_page_hwecc(struct mtd_info *mtd, 670 struct nand_chip *chip, const uint8_t *buf, int oob_required, 671 int page) 672 { 673 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1); 674 return 0; 675 } 676 677 678 /** 679 * Read raw page data without ecc 680 * 681 * @param mtd mtd info structure 682 * @param chip nand chip info structure 683 * @param buf buffer to store read data 684 * @param page page number to read 685 * @return 0 when successfully completed 686 * -EINVAL when chip->oob_poi is not double-word aligned 687 * -EIO when command timeout 688 */ 689 static int nand_read_page_raw(struct mtd_info *mtd, 690 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 691 { 692 return nand_rw_page(mtd, chip, buf, page, 0, 0); 693 } 694 695 /** 696 * Raw page write function 697 * 698 * @param mtd mtd info structure 699 * @param chip nand chip info structure 700 * @param buf data buffer 701 */ 702 static int nand_write_page_raw(struct mtd_info *mtd, 703 struct nand_chip *chip, const uint8_t *buf, 704 int oob_required, int page) 705 { 706 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1); 707 return 0; 708 } 709 710 /** 711 * OOB data read/write function 712 * 713 * @param mtd mtd info structure 714 * @param chip nand chip info structure 715 * @param page page number to read 716 * @param with_ecc 1 to enable ECC, 0 to disable ECC 717 * @param is_writing 0 for read, 1 for write 718 * @return 0 when successfully completed 719 * -EINVAL when chip->oob_poi is not double-word aligned 720 * -EIO when command timeout 721 */ 722 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip, 723 int page, int with_ecc, int is_writing) 724 { 725 u32 reg_val; 726 int tag_size; 727 struct nand_oobfree *free = chip->ecc.layout->oobfree; 728 struct nand_drv *info; 729 unsigned int bbflags; 730 struct bounce_buffer bbstate_oob; 731 732 if (((int)chip->oob_poi) & 0x03) 733 return -EINVAL; 734 info = (struct nand_drv *)nand_get_controller_data(chip); 735 if (set_bus_width_page_size(mtd, &info->config, ®_val)) 736 return -EINVAL; 737 738 stop_command(info->reg); 739 740 /* Set ECC selection */ 741 tag_size = mtd->oobsize; 742 if (with_ecc) 743 reg_val |= CFG_ECC_EN_TAG_ENABLE; 744 else 745 reg_val |= (CFG_ECC_EN_TAG_DISABLE); 746 747 reg_val |= ((tag_size - 1) | 748 CFG_SKIP_SPARE_DISABLE | 749 CFG_HW_ECC_CORRECTION_DISABLE | 750 CFG_HW_ECC_DISABLE); 751 writel(reg_val, &info->reg->config); 752 753 if (is_writing && with_ecc) 754 tag_size -= TAG_ECC_BYTES; 755 756 if (is_writing) 757 bbflags = GEN_BB_READ; 758 else 759 bbflags = GEN_BB_WRITE; 760 761 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size, 762 bbflags); 763 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr); 764 765 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config); 766 767 writel(tag_size - 1, &info->reg->dma_cfg_b); 768 769 nand_clear_interrupt_status(info->reg); 770 771 reg_val = CMD_CLE | CMD_ALE 772 | CMD_SEC_CMD 773 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT) 774 | CMD_B_VALID 775 | CMD_CE0; 776 if (!is_writing) 777 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); 778 else 779 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); 780 writel(reg_val, &info->reg->command); 781 782 /* Setup DMA engine */ 783 reg_val = DMA_MST_CTRL_GO_ENABLE 784 | DMA_MST_CTRL_BURST_8WORDS 785 | DMA_MST_CTRL_EN_B_ENABLE; 786 if (!is_writing) 787 reg_val |= DMA_MST_CTRL_DIR_READ; 788 else 789 reg_val |= DMA_MST_CTRL_DIR_WRITE; 790 791 writel(reg_val, &info->reg->dma_mst_ctrl); 792 793 start_command(info->reg); 794 795 if (!nand_waitfor_cmd_completion(info->reg)) { 796 if (!is_writing) 797 printf("Read OOB of Page 0x%X timeout\n", page); 798 else 799 printf("Write OOB of Page 0x%X timeout\n", page); 800 return -EIO; 801 } 802 803 bounce_buffer_stop(&bbstate_oob); 804 805 if (with_ecc && !is_writing) { 806 reg_val = (u32)check_ecc_error(info->reg, 0, 0, 807 (u8 *)(chip->oob_poi + free->offset), 808 chip->ecc.layout->oobavail); 809 if (reg_val & ECC_TAG_ERROR) 810 printf("Read OOB of Page 0x%X tag ECC error\n", page); 811 } 812 return 0; 813 } 814 815 /** 816 * OOB data read function 817 * 818 * @param mtd mtd info structure 819 * @param chip nand chip info structure 820 * @param page page number to read 821 */ 822 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 823 int page) 824 { 825 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 826 nand_rw_oob(mtd, chip, page, 0, 0); 827 return 0; 828 } 829 830 /** 831 * OOB data write function 832 * 833 * @param mtd mtd info structure 834 * @param chip nand chip info structure 835 * @param page page number to write 836 * @return 0 when successfully completed 837 * -EINVAL when chip->oob_poi is not double-word aligned 838 * -EIO when command timeout 839 */ 840 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 841 int page) 842 { 843 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 844 845 return nand_rw_oob(mtd, chip, page, 0, 1); 846 } 847 848 /** 849 * Set up NAND memory timings according to the provided parameters 850 * 851 * @param timing Timing parameters 852 * @param reg NAND controller register address 853 */ 854 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT], 855 struct nand_ctlr *reg) 856 { 857 u32 reg_val, clk_rate, clk_period, time_val; 858 859 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH, 860 CLOCK_ID_PERIPH) / 1000000; 861 clk_period = 1000 / clk_rate; 862 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << 863 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK; 864 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << 865 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK; 866 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; 867 if (time_val > 2) 868 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) & 869 TIMING_TCR_TAR_TRR_CNT_MASK; 870 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << 871 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK; 872 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period; 873 if (time_val > 1) 874 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) & 875 TIMING_TCS_CNT_MASK; 876 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << 877 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK; 878 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << 879 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK; 880 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << 881 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK; 882 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << 883 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK; 884 writel(reg_val, ®->timing); 885 886 reg_val = 0; 887 time_val = timing[FDT_NAND_TADL] / clk_period; 888 if (time_val > 2) 889 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK; 890 writel(reg_val, ®->timing2); 891 } 892 893 /** 894 * Decode NAND parameters from the device tree 895 * 896 * @param dev Driver model device 897 * @param config Device tree NAND configuration 898 * @return 0 if ok, -ve on error (FDT_ERR_...) 899 */ 900 static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config) 901 { 902 int err; 903 904 config->reg = (struct nand_ctlr *)dev_read_addr(dev); 905 config->enabled = dev_read_enabled(dev); 906 config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8); 907 err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio, 908 GPIOD_IS_OUT); 909 if (err) 910 return err; 911 err = dev_read_u32_array(dev, "nvidia,timing", config->timing, 912 FDT_NAND_TIMING_COUNT); 913 if (err < 0) 914 return err; 915 916 return 0; 917 } 918 919 static int tegra_probe(struct udevice *dev) 920 { 921 struct tegra_nand_info *tegra = dev_get_priv(dev); 922 struct nand_chip *nand = &tegra->nand_chip; 923 struct nand_drv *info = &tegra->nand_ctrl; 924 struct fdt_nand *config = &info->config; 925 struct mtd_info *our_mtd; 926 int ret; 927 928 if (fdt_decode_nand(dev, config)) { 929 printf("Could not decode nand-flash in device tree\n"); 930 return -1; 931 } 932 if (!config->enabled) 933 return -1; 934 info->reg = config->reg; 935 nand->ecc.mode = NAND_ECC_HW; 936 nand->ecc.layout = &eccoob; 937 938 nand->options = LP_OPTIONS; 939 nand->cmdfunc = nand_command; 940 nand->read_byte = read_byte; 941 nand->read_buf = read_buf; 942 nand->ecc.read_page = nand_read_page_hwecc; 943 nand->ecc.write_page = nand_write_page_hwecc; 944 nand->ecc.read_page_raw = nand_read_page_raw; 945 nand->ecc.write_page_raw = nand_write_page_raw; 946 nand->ecc.read_oob = nand_read_oob; 947 nand->ecc.write_oob = nand_write_oob; 948 nand->ecc.strength = 1; 949 nand->select_chip = nand_select_chip; 950 nand->dev_ready = nand_dev_ready; 951 nand_set_controller_data(nand, &tegra->nand_ctrl); 952 953 /* Disable subpage writes as we do not provide ecc->hwctl */ 954 nand->options |= NAND_NO_SUBPAGE_WRITE; 955 956 /* Adjust controller clock rate */ 957 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000); 958 959 /* Adjust timing for NAND device */ 960 setup_timing(config->timing, info->reg); 961 962 dm_gpio_set_value(&config->wp_gpio, 1); 963 964 our_mtd = nand_to_mtd(nand); 965 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); 966 if (ret) 967 return ret; 968 969 nand->ecc.size = our_mtd->writesize; 970 nand->ecc.bytes = our_mtd->oobsize; 971 972 ret = nand_scan_tail(our_mtd); 973 if (ret) 974 return ret; 975 976 ret = nand_register(0, our_mtd); 977 if (ret) { 978 dev_err(dev, "Failed to register MTD: %d\n", ret); 979 return ret; 980 } 981 982 return 0; 983 } 984 985 U_BOOT_DRIVER(tegra_nand) = { 986 .name = "tegra-nand", 987 .id = UCLASS_MTD, 988 .of_match = tegra_nand_dt_ids, 989 .probe = tegra_probe, 990 .priv_auto_alloc_size = sizeof(struct tegra_nand_info), 991 }; 992 993 void board_nand_init(void) 994 { 995 struct udevice *dev; 996 int ret; 997 998 ret = uclass_get_device_by_driver(UCLASS_MTD, 999 DM_GET_DRIVER(tegra_nand), &dev); 1000 if (ret && ret != -ENODEV) 1001 pr_err("Failed to initialize %s. (error %d)\n", dev->name, 1002 ret); 1003 } 1004