1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) STMicroelectronics 2019 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <nand.h> 11 #include <reset.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 15 /* Bad block marker length */ 16 #define FMC2_BBM_LEN 2 17 18 /* ECC step size */ 19 #define FMC2_ECC_STEP_SIZE 512 20 21 /* Command delay */ 22 #define FMC2_RB_DELAY_US 30 23 24 /* Max chip enable */ 25 #define FMC2_MAX_CE 2 26 27 /* Timings */ 28 #define FMC2_THIZ 1 29 #define FMC2_TIO 8000 30 #define FMC2_TSYNC 3000 31 #define FMC2_PCR_TIMING_MASK 0xf 32 #define FMC2_PMEM_PATT_TIMING_MASK 0xff 33 34 /* FMC2 Controller Registers */ 35 #define FMC2_BCR1 0x0 36 #define FMC2_PCR 0x80 37 #define FMC2_SR 0x84 38 #define FMC2_PMEM 0x88 39 #define FMC2_PATT 0x8c 40 #define FMC2_HECCR 0x94 41 #define FMC2_BCHISR 0x254 42 #define FMC2_BCHICR 0x258 43 #define FMC2_BCHPBR1 0x260 44 #define FMC2_BCHPBR2 0x264 45 #define FMC2_BCHPBR3 0x268 46 #define FMC2_BCHPBR4 0x26c 47 #define FMC2_BCHDSR0 0x27c 48 #define FMC2_BCHDSR1 0x280 49 #define FMC2_BCHDSR2 0x284 50 #define FMC2_BCHDSR3 0x288 51 #define FMC2_BCHDSR4 0x28c 52 53 /* Register: FMC2_BCR1 */ 54 #define FMC2_BCR1_FMC2EN BIT(31) 55 56 /* Register: FMC2_PCR */ 57 #define FMC2_PCR_PWAITEN BIT(1) 58 #define FMC2_PCR_PBKEN BIT(2) 59 #define FMC2_PCR_PWID_MASK GENMASK(5, 4) 60 #define FMC2_PCR_PWID(x) (((x) & 0x3) << 4) 61 #define FMC2_PCR_PWID_BUSWIDTH_8 0 62 #define FMC2_PCR_PWID_BUSWIDTH_16 1 63 #define FMC2_PCR_ECCEN BIT(6) 64 #define FMC2_PCR_ECCALG BIT(8) 65 #define FMC2_PCR_TCLR_MASK GENMASK(12, 9) 66 #define FMC2_PCR_TCLR(x) (((x) & 0xf) << 9) 67 #define FMC2_PCR_TCLR_DEFAULT 0xf 68 #define FMC2_PCR_TAR_MASK GENMASK(16, 13) 69 #define FMC2_PCR_TAR(x) (((x) & 0xf) << 13) 70 #define FMC2_PCR_TAR_DEFAULT 0xf 71 #define FMC2_PCR_ECCSS_MASK GENMASK(19, 17) 72 #define FMC2_PCR_ECCSS(x) (((x) & 0x7) << 17) 73 #define FMC2_PCR_ECCSS_512 1 74 #define FMC2_PCR_ECCSS_2048 3 75 #define FMC2_PCR_BCHECC BIT(24) 76 #define FMC2_PCR_WEN BIT(25) 77 78 /* Register: FMC2_SR */ 79 #define FMC2_SR_NWRF BIT(6) 80 81 /* Register: FMC2_PMEM */ 82 #define FMC2_PMEM_MEMSET(x) (((x) & 0xff) << 0) 83 #define FMC2_PMEM_MEMWAIT(x) (((x) & 0xff) << 8) 84 #define FMC2_PMEM_MEMHOLD(x) (((x) & 0xff) << 16) 85 #define FMC2_PMEM_MEMHIZ(x) (((x) & 0xff) << 24) 86 #define FMC2_PMEM_DEFAULT 0x0a0a0a0a 87 88 /* Register: FMC2_PATT */ 89 #define FMC2_PATT_ATTSET(x) (((x) & 0xff) << 0) 90 #define FMC2_PATT_ATTWAIT(x) (((x) & 0xff) << 8) 91 #define FMC2_PATT_ATTHOLD(x) (((x) & 0xff) << 16) 92 #define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24) 93 #define FMC2_PATT_DEFAULT 0x0a0a0a0a 94 95 /* Register: FMC2_BCHISR */ 96 #define FMC2_BCHISR_DERF BIT(1) 97 #define FMC2_BCHISR_EPBRF BIT(4) 98 99 /* Register: FMC2_BCHICR */ 100 #define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0) 101 102 /* Register: FMC2_BCHDSR0 */ 103 #define FMC2_BCHDSR0_DUE BIT(0) 104 #define FMC2_BCHDSR0_DEF BIT(1) 105 #define FMC2_BCHDSR0_DEN_MASK GENMASK(7, 4) 106 #define FMC2_BCHDSR0_DEN_SHIFT 4 107 108 /* Register: FMC2_BCHDSR1 */ 109 #define FMC2_BCHDSR1_EBP1_MASK GENMASK(12, 0) 110 #define FMC2_BCHDSR1_EBP2_MASK GENMASK(28, 16) 111 #define FMC2_BCHDSR1_EBP2_SHIFT 16 112 113 /* Register: FMC2_BCHDSR2 */ 114 #define FMC2_BCHDSR2_EBP3_MASK GENMASK(12, 0) 115 #define FMC2_BCHDSR2_EBP4_MASK GENMASK(28, 16) 116 #define FMC2_BCHDSR2_EBP4_SHIFT 16 117 118 /* Register: FMC2_BCHDSR3 */ 119 #define FMC2_BCHDSR3_EBP5_MASK GENMASK(12, 0) 120 #define FMC2_BCHDSR3_EBP6_MASK GENMASK(28, 16) 121 #define FMC2_BCHDSR3_EBP6_SHIFT 16 122 123 /* Register: FMC2_BCHDSR4 */ 124 #define FMC2_BCHDSR4_EBP7_MASK GENMASK(12, 0) 125 #define FMC2_BCHDSR4_EBP8_MASK GENMASK(28, 16) 126 #define FMC2_BCHDSR4_EBP8_SHIFT 16 127 128 #define FMC2_NSEC_PER_SEC 1000000000L 129 130 enum stm32_fmc2_ecc { 131 FMC2_ECC_HAM = 1, 132 FMC2_ECC_BCH4 = 4, 133 FMC2_ECC_BCH8 = 8 134 }; 135 136 struct stm32_fmc2_timings { 137 u8 tclr; 138 u8 tar; 139 u8 thiz; 140 u8 twait; 141 u8 thold_mem; 142 u8 tset_mem; 143 u8 thold_att; 144 u8 tset_att; 145 }; 146 147 struct stm32_fmc2_nand { 148 struct nand_chip chip; 149 struct stm32_fmc2_timings timings; 150 int ncs; 151 int cs_used[FMC2_MAX_CE]; 152 }; 153 154 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) 155 { 156 return container_of(chip, struct stm32_fmc2_nand, chip); 157 } 158 159 struct stm32_fmc2_nfc { 160 struct nand_hw_control base; 161 struct stm32_fmc2_nand nand; 162 struct nand_ecclayout ecclayout; 163 void __iomem *io_base; 164 void __iomem *data_base[FMC2_MAX_CE]; 165 void __iomem *cmd_base[FMC2_MAX_CE]; 166 void __iomem *addr_base[FMC2_MAX_CE]; 167 struct clk clk; 168 169 u8 cs_assigned; 170 int cs_sel; 171 }; 172 173 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base) 174 { 175 return container_of(base, struct stm32_fmc2_nfc, base); 176 } 177 178 /* Timings configuration */ 179 static void stm32_fmc2_timings_init(struct nand_chip *chip) 180 { 181 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 182 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 183 struct stm32_fmc2_timings *timings = &nand->timings; 184 u32 pcr = readl(fmc2->io_base + FMC2_PCR); 185 u32 pmem, patt; 186 187 /* Set tclr/tar timings */ 188 pcr &= ~FMC2_PCR_TCLR_MASK; 189 pcr |= FMC2_PCR_TCLR(timings->tclr); 190 pcr &= ~FMC2_PCR_TAR_MASK; 191 pcr |= FMC2_PCR_TAR(timings->tar); 192 193 /* Set tset/twait/thold/thiz timings in common bank */ 194 pmem = FMC2_PMEM_MEMSET(timings->tset_mem); 195 pmem |= FMC2_PMEM_MEMWAIT(timings->twait); 196 pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem); 197 pmem |= FMC2_PMEM_MEMHIZ(timings->thiz); 198 199 /* Set tset/twait/thold/thiz timings in attribut bank */ 200 patt = FMC2_PATT_ATTSET(timings->tset_att); 201 patt |= FMC2_PATT_ATTWAIT(timings->twait); 202 patt |= FMC2_PATT_ATTHOLD(timings->thold_att); 203 patt |= FMC2_PATT_ATTHIZ(timings->thiz); 204 205 writel(pcr, fmc2->io_base + FMC2_PCR); 206 writel(pmem, fmc2->io_base + FMC2_PMEM); 207 writel(patt, fmc2->io_base + FMC2_PATT); 208 } 209 210 /* Controller configuration */ 211 static void stm32_fmc2_setup(struct nand_chip *chip) 212 { 213 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 214 u32 pcr = readl(fmc2->io_base + FMC2_PCR); 215 216 /* Configure ECC algorithm (default configuration is Hamming) */ 217 pcr &= ~FMC2_PCR_ECCALG; 218 pcr &= ~FMC2_PCR_BCHECC; 219 if (chip->ecc.strength == FMC2_ECC_BCH8) { 220 pcr |= FMC2_PCR_ECCALG; 221 pcr |= FMC2_PCR_BCHECC; 222 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { 223 pcr |= FMC2_PCR_ECCALG; 224 } 225 226 /* Set buswidth */ 227 pcr &= ~FMC2_PCR_PWID_MASK; 228 if (chip->options & NAND_BUSWIDTH_16) 229 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16); 230 231 /* Set ECC sector size */ 232 pcr &= ~FMC2_PCR_ECCSS_MASK; 233 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); 234 235 writel(pcr, fmc2->io_base + FMC2_PCR); 236 } 237 238 /* Select target */ 239 static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr) 240 { 241 struct nand_chip *chip = mtd_to_nand(mtd); 242 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 243 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 244 245 if (chipnr < 0 || chipnr >= nand->ncs) 246 return; 247 248 if (nand->cs_used[chipnr] == fmc2->cs_sel) 249 return; 250 251 fmc2->cs_sel = nand->cs_used[chipnr]; 252 chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel]; 253 chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel]; 254 255 /* FMC2 setup routine */ 256 stm32_fmc2_setup(chip); 257 258 /* Apply timings */ 259 stm32_fmc2_timings_init(chip); 260 } 261 262 /* Set bus width to 16-bit or 8-bit */ 263 static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set) 264 { 265 u32 pcr = readl(fmc2->io_base + FMC2_PCR); 266 267 pcr &= ~FMC2_PCR_PWID_MASK; 268 if (set) 269 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16); 270 writel(pcr, fmc2->io_base + FMC2_PCR); 271 } 272 273 /* Enable/disable ECC */ 274 static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable) 275 { 276 u32 pcr = readl(fmc2->io_base + FMC2_PCR); 277 278 pcr &= ~FMC2_PCR_ECCEN; 279 if (enable) 280 pcr |= FMC2_PCR_ECCEN; 281 writel(pcr, fmc2->io_base + FMC2_PCR); 282 } 283 284 /* Clear irq sources in case of bch is used */ 285 static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2) 286 { 287 writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR); 288 } 289 290 /* Send command and address cycles */ 291 static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd, 292 unsigned int ctrl) 293 { 294 struct nand_chip *chip = mtd_to_nand(mtd); 295 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 296 297 if (cmd == NAND_CMD_NONE) 298 return; 299 300 if (ctrl & NAND_CLE) { 301 writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]); 302 return; 303 } 304 305 writeb(cmd, fmc2->addr_base[fmc2->cs_sel]); 306 } 307 308 /* 309 * Enable ECC logic and reset syndrome/parity bits previously calculated 310 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0 311 */ 312 static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode) 313 { 314 struct nand_chip *chip = mtd_to_nand(mtd); 315 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 316 317 stm32_fmc2_set_ecc(fmc2, false); 318 319 if (chip->ecc.strength != FMC2_ECC_HAM) { 320 u32 pcr = readl(fmc2->io_base + FMC2_PCR); 321 322 if (mode == NAND_ECC_WRITE) 323 pcr |= FMC2_PCR_WEN; 324 else 325 pcr &= ~FMC2_PCR_WEN; 326 writel(pcr, fmc2->io_base + FMC2_PCR); 327 328 stm32_fmc2_clear_bch_irq(fmc2); 329 } 330 331 stm32_fmc2_set_ecc(fmc2, true); 332 } 333 334 /* 335 * ECC Hamming calculation 336 * ECC is 3 bytes for 512 bytes of data (supports error correction up to 337 * max of 1-bit) 338 */ 339 static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data, 340 u8 *ecc) 341 { 342 struct nand_chip *chip = mtd_to_nand(mtd); 343 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 344 u32 heccr, sr; 345 int ret; 346 347 ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr, 348 sr & FMC2_SR_NWRF, 10000); 349 if (ret < 0) { 350 pr_err("Ham timeout\n"); 351 return ret; 352 } 353 354 heccr = readl(fmc2->io_base + FMC2_HECCR); 355 356 ecc[0] = heccr; 357 ecc[1] = heccr >> 8; 358 ecc[2] = heccr >> 16; 359 360 /* Disable ecc */ 361 stm32_fmc2_set_ecc(fmc2, false); 362 363 return 0; 364 } 365 366 static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat, 367 u8 *read_ecc, u8 *calc_ecc) 368 { 369 u8 bit_position = 0, b0, b1, b2; 370 u32 byte_addr = 0, b; 371 u32 i, shifting = 1; 372 373 /* Indicate which bit and byte is faulty (if any) */ 374 b0 = read_ecc[0] ^ calc_ecc[0]; 375 b1 = read_ecc[1] ^ calc_ecc[1]; 376 b2 = read_ecc[2] ^ calc_ecc[2]; 377 b = b0 | (b1 << 8) | (b2 << 16); 378 379 /* No errors */ 380 if (likely(!b)) 381 return 0; 382 383 /* Calculate bit position */ 384 for (i = 0; i < 3; i++) { 385 switch (b % 4) { 386 case 2: 387 bit_position += shifting; 388 case 1: 389 break; 390 default: 391 return -EBADMSG; 392 } 393 shifting <<= 1; 394 b >>= 2; 395 } 396 397 /* Calculate byte position */ 398 shifting = 1; 399 for (i = 0; i < 9; i++) { 400 switch (b % 4) { 401 case 2: 402 byte_addr += shifting; 403 case 1: 404 break; 405 default: 406 return -EBADMSG; 407 } 408 shifting <<= 1; 409 b >>= 2; 410 } 411 412 /* Flip the bit */ 413 dat[byte_addr] ^= (1 << bit_position); 414 415 return 1; 416 } 417 418 /* 419 * ECC BCH calculation and correction 420 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to 421 * max of 4-bit/8-bit) 422 */ 423 424 static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data, 425 u8 *ecc) 426 { 427 struct nand_chip *chip = mtd_to_nand(mtd); 428 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 429 u32 bchpbr, bchisr; 430 int ret; 431 432 /* Wait until the BCH code is ready */ 433 ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr, 434 bchisr & FMC2_BCHISR_EPBRF, 10000); 435 if (ret < 0) { 436 pr_err("Bch timeout\n"); 437 return ret; 438 } 439 440 /* Read parity bits */ 441 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1); 442 ecc[0] = bchpbr; 443 ecc[1] = bchpbr >> 8; 444 ecc[2] = bchpbr >> 16; 445 ecc[3] = bchpbr >> 24; 446 447 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2); 448 ecc[4] = bchpbr; 449 ecc[5] = bchpbr >> 8; 450 ecc[6] = bchpbr >> 16; 451 452 if (chip->ecc.strength == FMC2_ECC_BCH8) { 453 ecc[7] = bchpbr >> 24; 454 455 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3); 456 ecc[8] = bchpbr; 457 ecc[9] = bchpbr >> 8; 458 ecc[10] = bchpbr >> 16; 459 ecc[11] = bchpbr >> 24; 460 461 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4); 462 ecc[12] = bchpbr; 463 } 464 465 /* Disable ecc */ 466 stm32_fmc2_set_ecc(fmc2, false); 467 468 return 0; 469 } 470 471 /* BCH algorithm correction */ 472 static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat, 473 u8 *read_ecc, u8 *calc_ecc) 474 { 475 struct nand_chip *chip = mtd_to_nand(mtd); 476 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 477 u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr; 478 u16 pos[8]; 479 int i, ret, den, eccsize = chip->ecc.size; 480 unsigned int nb_errs = 0; 481 482 /* Wait until the decoding error is ready */ 483 ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr, 484 bchisr & FMC2_BCHISR_DERF, 10000); 485 if (ret < 0) { 486 pr_err("Bch timeout\n"); 487 return ret; 488 } 489 490 bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0); 491 bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1); 492 bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2); 493 bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3); 494 bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4); 495 496 /* Disable ECC */ 497 stm32_fmc2_set_ecc(fmc2, false); 498 499 /* No errors found */ 500 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF))) 501 return 0; 502 503 /* Too many errors detected */ 504 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE)) 505 return -EBADMSG; 506 507 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; 508 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; 509 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; 510 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; 511 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; 512 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; 513 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; 514 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; 515 516 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; 517 for (i = 0; i < den; i++) { 518 if (pos[i] < eccsize * 8) { 519 __change_bit(pos[i], (unsigned long *)dat); 520 nb_errs++; 521 } 522 } 523 524 return nb_errs; 525 } 526 527 static int stm32_fmc2_read_page(struct mtd_info *mtd, 528 struct nand_chip *chip, u8 *buf, 529 int oob_required, int page) 530 { 531 int i, s, stat, eccsize = chip->ecc.size; 532 int eccbytes = chip->ecc.bytes; 533 int eccsteps = chip->ecc.steps; 534 int eccstrength = chip->ecc.strength; 535 u8 *p = buf; 536 u8 *ecc_calc = chip->buffers->ecccalc; 537 u8 *ecc_code = chip->buffers->ecccode; 538 unsigned int max_bitflips = 0; 539 540 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps; 541 s++, i += eccbytes, p += eccsize) { 542 chip->ecc.hwctl(mtd, NAND_ECC_READ); 543 544 /* Read the nand page sector (512 bytes) */ 545 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1); 546 chip->read_buf(mtd, p, eccsize); 547 548 /* Read the corresponding ECC bytes */ 549 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1); 550 chip->read_buf(mtd, ecc_code, eccbytes); 551 552 /* Correct the data */ 553 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc); 554 if (stat == -EBADMSG) 555 /* Check for empty pages with bitflips */ 556 stat = nand_check_erased_ecc_chunk(p, eccsize, 557 ecc_code, eccbytes, 558 NULL, 0, 559 eccstrength); 560 561 if (stat < 0) { 562 mtd->ecc_stats.failed++; 563 } else { 564 mtd->ecc_stats.corrected += stat; 565 max_bitflips = max_t(unsigned int, max_bitflips, stat); 566 } 567 } 568 569 /* Read oob */ 570 if (oob_required) { 571 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 572 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 573 } 574 575 return max_bitflips; 576 } 577 578 /* Controller initialization */ 579 static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2) 580 { 581 u32 pcr = readl(fmc2->io_base + FMC2_PCR); 582 u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1); 583 584 /* Set CS used to undefined */ 585 fmc2->cs_sel = -1; 586 587 /* Enable wait feature and nand flash memory bank */ 588 pcr |= FMC2_PCR_PWAITEN; 589 pcr |= FMC2_PCR_PBKEN; 590 591 /* Set buswidth to 8 bits mode for identification */ 592 pcr &= ~FMC2_PCR_PWID_MASK; 593 594 /* ECC logic is disabled */ 595 pcr &= ~FMC2_PCR_ECCEN; 596 597 /* Default mode */ 598 pcr &= ~FMC2_PCR_ECCALG; 599 pcr &= ~FMC2_PCR_BCHECC; 600 pcr &= ~FMC2_PCR_WEN; 601 602 /* Set default ECC sector size */ 603 pcr &= ~FMC2_PCR_ECCSS_MASK; 604 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); 605 606 /* Set default tclr/tar timings */ 607 pcr &= ~FMC2_PCR_TCLR_MASK; 608 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); 609 pcr &= ~FMC2_PCR_TAR_MASK; 610 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); 611 612 /* Enable FMC2 controller */ 613 bcr1 |= FMC2_BCR1_FMC2EN; 614 615 writel(bcr1, fmc2->io_base + FMC2_BCR1); 616 writel(pcr, fmc2->io_base + FMC2_PCR); 617 writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM); 618 writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT); 619 } 620 621 /* Controller timings */ 622 static void stm32_fmc2_calc_timings(struct nand_chip *chip, 623 const struct nand_sdr_timings *sdrt) 624 { 625 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); 626 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 627 struct stm32_fmc2_timings *tims = &nand->timings; 628 unsigned long hclk = clk_get_rate(&fmc2->clk); 629 unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000); 630 int tar, tclr, thiz, twait, tset_mem, tset_att, thold_mem, thold_att; 631 632 tar = hclkp; 633 if (tar < sdrt->tAR_min) 634 tar = sdrt->tAR_min; 635 tims->tar = DIV_ROUND_UP(tar, hclkp) - 1; 636 if (tims->tar > FMC2_PCR_TIMING_MASK) 637 tims->tar = FMC2_PCR_TIMING_MASK; 638 639 tclr = hclkp; 640 if (tclr < sdrt->tCLR_min) 641 tclr = sdrt->tCLR_min; 642 tims->tclr = DIV_ROUND_UP(tclr, hclkp) - 1; 643 if (tims->tclr > FMC2_PCR_TIMING_MASK) 644 tims->tclr = FMC2_PCR_TIMING_MASK; 645 646 tims->thiz = FMC2_THIZ; 647 thiz = (tims->thiz + 1) * hclkp; 648 649 /* 650 * tWAIT > tRP 651 * tWAIT > tWP 652 * tWAIT > tREA + tIO 653 */ 654 twait = hclkp; 655 if (twait < sdrt->tRP_min) 656 twait = sdrt->tRP_min; 657 if (twait < sdrt->tWP_min) 658 twait = sdrt->tWP_min; 659 if (twait < sdrt->tREA_max + FMC2_TIO) 660 twait = sdrt->tREA_max + FMC2_TIO; 661 tims->twait = DIV_ROUND_UP(twait, hclkp); 662 if (tims->twait == 0) 663 tims->twait = 1; 664 else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK) 665 tims->twait = FMC2_PMEM_PATT_TIMING_MASK; 666 667 /* 668 * tSETUP_MEM > tCS - tWAIT 669 * tSETUP_MEM > tALS - tWAIT 670 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 671 */ 672 tset_mem = hclkp; 673 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait)) 674 tset_mem = sdrt->tCS_min - twait; 675 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait)) 676 tset_mem = sdrt->tALS_min - twait; 677 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 678 (tset_mem < sdrt->tDS_min - (twait - thiz))) 679 tset_mem = sdrt->tDS_min - (twait - thiz); 680 tims->tset_mem = DIV_ROUND_UP(tset_mem, hclkp); 681 if (tims->tset_mem == 0) 682 tims->tset_mem = 1; 683 else if (tims->tset_mem > FMC2_PMEM_PATT_TIMING_MASK) 684 tims->tset_mem = FMC2_PMEM_PATT_TIMING_MASK; 685 686 /* 687 * tHOLD_MEM > tCH 688 * tHOLD_MEM > tREH - tSETUP_MEM 689 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 690 */ 691 thold_mem = hclkp; 692 if (thold_mem < sdrt->tCH_min) 693 thold_mem = sdrt->tCH_min; 694 if (sdrt->tREH_min > tset_mem && 695 (thold_mem < sdrt->tREH_min - tset_mem)) 696 thold_mem = sdrt->tREH_min - tset_mem; 697 if ((sdrt->tRC_min > tset_mem + twait) && 698 (thold_mem < sdrt->tRC_min - (tset_mem + twait))) 699 thold_mem = sdrt->tRC_min - (tset_mem + twait); 700 if ((sdrt->tWC_min > tset_mem + twait) && 701 (thold_mem < sdrt->tWC_min - (tset_mem + twait))) 702 thold_mem = sdrt->tWC_min - (tset_mem + twait); 703 tims->thold_mem = DIV_ROUND_UP(thold_mem, hclkp); 704 if (tims->thold_mem == 0) 705 tims->thold_mem = 1; 706 else if (tims->thold_mem > FMC2_PMEM_PATT_TIMING_MASK) 707 tims->thold_mem = FMC2_PMEM_PATT_TIMING_MASK; 708 709 /* 710 * tSETUP_ATT > tCS - tWAIT 711 * tSETUP_ATT > tCLS - tWAIT 712 * tSETUP_ATT > tALS - tWAIT 713 * tSETUP_ATT > tRHW - tHOLD_MEM 714 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 715 */ 716 tset_att = hclkp; 717 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait)) 718 tset_att = sdrt->tCS_min - twait; 719 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait)) 720 tset_att = sdrt->tCLS_min - twait; 721 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait)) 722 tset_att = sdrt->tALS_min - twait; 723 if (sdrt->tRHW_min > thold_mem && 724 (tset_att < sdrt->tRHW_min - thold_mem)) 725 tset_att = sdrt->tRHW_min - thold_mem; 726 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 727 (tset_att < sdrt->tDS_min - (twait - thiz))) 728 tset_att = sdrt->tDS_min - (twait - thiz); 729 tims->tset_att = DIV_ROUND_UP(tset_att, hclkp); 730 if (tims->tset_att == 0) 731 tims->tset_att = 1; 732 else if (tims->tset_att > FMC2_PMEM_PATT_TIMING_MASK) 733 tims->tset_att = FMC2_PMEM_PATT_TIMING_MASK; 734 735 /* 736 * tHOLD_ATT > tALH 737 * tHOLD_ATT > tCH 738 * tHOLD_ATT > tCLH 739 * tHOLD_ATT > tCOH 740 * tHOLD_ATT > tDH 741 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 742 * tHOLD_ATT > tADL - tSETUP_MEM 743 * tHOLD_ATT > tWH - tSETUP_MEM 744 * tHOLD_ATT > tWHR - tSETUP_MEM 745 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 746 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 747 */ 748 thold_att = hclkp; 749 if (thold_att < sdrt->tALH_min) 750 thold_att = sdrt->tALH_min; 751 if (thold_att < sdrt->tCH_min) 752 thold_att = sdrt->tCH_min; 753 if (thold_att < sdrt->tCLH_min) 754 thold_att = sdrt->tCLH_min; 755 if (thold_att < sdrt->tCOH_min) 756 thold_att = sdrt->tCOH_min; 757 if (thold_att < sdrt->tDH_min) 758 thold_att = sdrt->tDH_min; 759 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && 760 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) 761 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; 762 if (sdrt->tADL_min > tset_mem && 763 (thold_att < sdrt->tADL_min - tset_mem)) 764 thold_att = sdrt->tADL_min - tset_mem; 765 if (sdrt->tWH_min > tset_mem && 766 (thold_att < sdrt->tWH_min - tset_mem)) 767 thold_att = sdrt->tWH_min - tset_mem; 768 if (sdrt->tWHR_min > tset_mem && 769 (thold_att < sdrt->tWHR_min - tset_mem)) 770 thold_att = sdrt->tWHR_min - tset_mem; 771 if ((sdrt->tRC_min > tset_att + twait) && 772 (thold_att < sdrt->tRC_min - (tset_att + twait))) 773 thold_att = sdrt->tRC_min - (tset_att + twait); 774 if ((sdrt->tWC_min > tset_att + twait) && 775 (thold_att < sdrt->tWC_min - (tset_att + twait))) 776 thold_att = sdrt->tWC_min - (tset_att + twait); 777 tims->thold_att = DIV_ROUND_UP(thold_att, hclkp); 778 if (tims->thold_att == 0) 779 tims->thold_att = 1; 780 else if (tims->thold_att > FMC2_PMEM_PATT_TIMING_MASK) 781 tims->thold_att = FMC2_PMEM_PATT_TIMING_MASK; 782 } 783 784 static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr, 785 const struct nand_data_interface *conf) 786 { 787 struct nand_chip *chip = mtd_to_nand(mtd); 788 const struct nand_sdr_timings *sdrt; 789 790 sdrt = nand_get_sdr_timings(conf); 791 if (IS_ERR(sdrt)) 792 return PTR_ERR(sdrt); 793 794 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 795 return 0; 796 797 stm32_fmc2_calc_timings(chip, sdrt); 798 799 /* Apply timings */ 800 stm32_fmc2_timings_init(chip); 801 802 return 0; 803 } 804 805 /* NAND callbacks setup */ 806 static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip) 807 { 808 chip->ecc.hwctl = stm32_fmc2_hwctl; 809 810 /* 811 * Specific callbacks to read/write a page depending on 812 * the algo used (Hamming, BCH). 813 */ 814 if (chip->ecc.strength == FMC2_ECC_HAM) { 815 /* Hamming is used */ 816 chip->ecc.calculate = stm32_fmc2_ham_calculate; 817 chip->ecc.correct = stm32_fmc2_ham_correct; 818 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3; 819 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK; 820 return; 821 } 822 823 /* BCH is used */ 824 chip->ecc.read_page = stm32_fmc2_read_page; 825 chip->ecc.calculate = stm32_fmc2_bch_calculate; 826 chip->ecc.correct = stm32_fmc2_bch_correct; 827 828 if (chip->ecc.strength == FMC2_ECC_BCH8) 829 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13; 830 else 831 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7; 832 } 833 834 /* FMC2 caps */ 835 static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength) 836 { 837 /* Hamming */ 838 if (strength == FMC2_ECC_HAM) 839 return 4; 840 841 /* BCH8 */ 842 if (strength == FMC2_ECC_BCH8) 843 return 14; 844 845 /* BCH4 */ 846 return 8; 847 } 848 849 NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes, 850 FMC2_ECC_STEP_SIZE, 851 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8); 852 853 /* FMC2 probe */ 854 static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2, 855 ofnode node) 856 { 857 struct stm32_fmc2_nand *nand = &fmc2->nand; 858 u32 cs[FMC2_MAX_CE]; 859 int ret, i; 860 861 if (!ofnode_get_property(node, "reg", &nand->ncs)) 862 return -EINVAL; 863 864 nand->ncs /= sizeof(u32); 865 if (!nand->ncs) { 866 pr_err("Invalid reg property size\n"); 867 return -EINVAL; 868 } 869 870 ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs); 871 if (ret < 0) { 872 pr_err("Could not retrieve reg property\n"); 873 return -EINVAL; 874 } 875 876 for (i = 0; i < nand->ncs; i++) { 877 if (cs[i] > FMC2_MAX_CE) { 878 pr_err("Invalid reg value: %d\n", 879 nand->cs_used[i]); 880 return -EINVAL; 881 } 882 883 if (fmc2->cs_assigned & BIT(cs[i])) { 884 pr_err("Cs already assigned: %d\n", 885 nand->cs_used[i]); 886 return -EINVAL; 887 } 888 889 fmc2->cs_assigned |= BIT(cs[i]); 890 nand->cs_used[i] = cs[i]; 891 } 892 893 nand->chip.flash_node = ofnode_to_offset(node); 894 895 return 0; 896 } 897 898 static int stm32_fmc2_parse_dt(struct udevice *dev, 899 struct stm32_fmc2_nfc *fmc2) 900 { 901 ofnode child; 902 int ret, nchips = 0; 903 904 dev_for_each_subnode(child, dev) 905 nchips++; 906 907 if (!nchips) { 908 pr_err("NAND chip not defined\n"); 909 return -EINVAL; 910 } 911 912 if (nchips > 1) { 913 pr_err("Too many NAND chips defined\n"); 914 return -EINVAL; 915 } 916 917 dev_for_each_subnode(child, dev) { 918 ret = stm32_fmc2_parse_child(fmc2, child); 919 if (ret) 920 return ret; 921 } 922 923 return 0; 924 } 925 926 static int stm32_fmc2_probe(struct udevice *dev) 927 { 928 struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev); 929 struct stm32_fmc2_nand *nand = &fmc2->nand; 930 struct nand_chip *chip = &nand->chip; 931 struct mtd_info *mtd = &chip->mtd; 932 struct nand_ecclayout *ecclayout; 933 struct resource resource; 934 struct reset_ctl reset; 935 int oob_index, chip_cs, mem_region, ret, i; 936 937 spin_lock_init(&fmc2->controller.lock); 938 init_waitqueue_head(&fmc2->controller.wq); 939 940 ret = stm32_fmc2_parse_dt(dev, fmc2); 941 if (ret) 942 return ret; 943 944 /* Get resources */ 945 ret = dev_read_resource(dev, 0, &resource); 946 if (ret) { 947 pr_err("Resource io_base not found"); 948 return ret; 949 } 950 fmc2->io_base = (void __iomem *)resource.start; 951 952 for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE; 953 chip_cs++, mem_region += 3) { 954 if (!(fmc2->cs_assigned & BIT(chip_cs))) 955 continue; 956 957 ret = dev_read_resource(dev, mem_region, &resource); 958 if (ret) { 959 pr_err("Resource data_base not found for cs%d", 960 chip_cs); 961 return ret; 962 } 963 fmc2->data_base[chip_cs] = (void __iomem *)resource.start; 964 965 ret = dev_read_resource(dev, mem_region + 1, &resource); 966 if (ret) { 967 pr_err("Resource cmd_base not found for cs%d", 968 chip_cs); 969 return ret; 970 } 971 fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start; 972 973 ret = dev_read_resource(dev, mem_region + 2, &resource); 974 if (ret) { 975 pr_err("Resource addr_base not found for cs%d", 976 chip_cs); 977 return ret; 978 } 979 fmc2->addr_base[chip_cs] = (void __iomem *)resource.start; 980 } 981 982 /* Enable the clock */ 983 ret = clk_get_by_index(dev, 0, &fmc2->clk); 984 if (ret) 985 return ret; 986 987 ret = clk_enable(&fmc2->clk); 988 if (ret) 989 return ret; 990 991 /* Reset */ 992 ret = reset_get_by_index(dev, 0, &reset); 993 if (!ret) { 994 reset_assert(&reset); 995 udelay(2); 996 reset_deassert(&reset); 997 } 998 999 /* FMC2 init routine */ 1000 stm32_fmc2_init(fmc2); 1001 1002 chip->controller = &fmc2->base; 1003 chip->select_chip = stm32_fmc2_select_chip; 1004 chip->setup_data_interface = stm32_fmc2_setup_interface; 1005 chip->cmd_ctrl = stm32_fmc2_cmd_ctrl; 1006 chip->chip_delay = FMC2_RB_DELAY_US; 1007 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | 1008 NAND_USE_BOUNCE_BUFFER; 1009 1010 /* Default ECC settings */ 1011 chip->ecc.mode = NAND_ECC_HW; 1012 chip->ecc.size = FMC2_ECC_STEP_SIZE; 1013 chip->ecc.strength = FMC2_ECC_BCH8; 1014 1015 /* Scan to find existence of the device */ 1016 ret = nand_scan_ident(mtd, nand->ncs, NULL); 1017 if (ret) 1018 return ret; 1019 1020 /* 1021 * Only NAND_ECC_HW mode is actually supported 1022 * Hamming => ecc.strength = 1 1023 * BCH4 => ecc.strength = 4 1024 * BCH8 => ecc.strength = 8 1025 * ECC sector size = 512 1026 */ 1027 if (chip->ecc.mode != NAND_ECC_HW) { 1028 pr_err("Nand_ecc_mode is not well defined in the DT\n"); 1029 return -EINVAL; 1030 } 1031 1032 ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps, 1033 mtd->oobsize - FMC2_BBM_LEN); 1034 if (ret) { 1035 pr_err("No valid ECC settings set\n"); 1036 return ret; 1037 } 1038 1039 if (chip->bbt_options & NAND_BBT_USE_FLASH) 1040 chip->bbt_options |= NAND_BBT_NO_OOB; 1041 1042 /* NAND callbacks setup */ 1043 stm32_fmc2_nand_callbacks_setup(chip); 1044 1045 /* Define ECC layout */ 1046 ecclayout = &fmc2->ecclayout; 1047 ecclayout->eccbytes = chip->ecc.bytes * 1048 (mtd->writesize / chip->ecc.size); 1049 oob_index = FMC2_BBM_LEN; 1050 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) 1051 ecclayout->eccpos[i] = oob_index; 1052 ecclayout->oobfree->offset = oob_index; 1053 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; 1054 chip->ecc.layout = ecclayout; 1055 1056 /* Configure bus width to 16-bit */ 1057 if (chip->options & NAND_BUSWIDTH_16) 1058 stm32_fmc2_set_buswidth_16(fmc2, true); 1059 1060 /* Scan the device to fill MTD data-structures */ 1061 ret = nand_scan_tail(mtd); 1062 if (ret) 1063 return ret; 1064 1065 return nand_register(0, mtd); 1066 } 1067 1068 static const struct udevice_id stm32_fmc2_match[] = { 1069 { .compatible = "st,stm32mp15-fmc2" }, 1070 { /* Sentinel */ } 1071 }; 1072 1073 U_BOOT_DRIVER(stm32_fmc2_nand) = { 1074 .name = "stm32_fmc2_nand", 1075 .id = UCLASS_MTD, 1076 .of_match = stm32_fmc2_match, 1077 .probe = stm32_fmc2_probe, 1078 .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc), 1079 }; 1080 1081 void board_nand_init(void) 1082 { 1083 struct udevice *dev; 1084 int ret; 1085 1086 ret = uclass_get_device_by_driver(UCLASS_MTD, 1087 DM_GET_DRIVER(stm32_fmc2_nand), 1088 &dev); 1089 if (ret && ret != -ENODEV) 1090 pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n", 1091 ret); 1092 } 1093