1 /* 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com> 3 * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <inttypes.h> 12 #include <nand.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/kernel.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/nand.h> 18 #include <linux/mtd/partitions.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define NANDC_V9_BOOTROM_ECC 70 23 #define NANDC_V9_NUM_BANKS 4 24 #define NANDC_V9_DEF_TIMEOUT 20000 25 #define NANDC_V9_READ 0 26 #define NANDC_V9_WRITE 1 27 #define NANDC_REG_V9_FMCTL 0x00 28 #define NANDC_REG_V9_FMWAIT 0x04 29 #define NANDC_REG_V9_FLCTL 0x10 30 #define NANDC_REG_V9_BCHCTL 0x20 31 #define NANDC_REG_V9_DMA_CFG 0x30 32 #define NANDC_REG_V9_DMA_BUF0 0x34 33 #define NANDC_REG_V9_DMA_BUF1 0x38 34 #define NANDC_REG_V9_DMA_ST 0x40 35 #define NANDC_REG_V9_VER 0x80 36 #define NANDC_REG_V9_INTEN 0x120 37 #define NANDC_REG_V9_INTCLR 0x124 38 #define NANDC_REG_V9_INTST 0x128 39 #define NANDC_REG_V9_BCHST 0x150 40 #define NANDC_REG_V9_SPARE0 0x200 41 #define NANDC_REG_V9_SPARE1 0x204 42 #define NANDC_REG_V9_RANDMZ 0x208 43 #define NANDC_REG_V9_BANK0 0x800 44 #define NANDC_REG_V9_SRAM0 0x1000 45 #define NANDC_REG_V9_SRAM_SIZE 0x400 46 47 #define NANDC_REG_V9_DATA 0x00 48 #define NANDC_REG_V9_ADDR 0x04 49 #define NANDC_REG_V9_CMD 0x08 50 51 /* FMCTL */ 52 #define NANDC_V9_FM_WP BIT(8) 53 #define NANDC_V9_FM_CE_SEL_M 0xFF 54 #define NANDC_V9_FM_CE_SEL(x) (1 << (x)) 55 #define NANDC_V9_FM_FREADY BIT(9) 56 57 /* FLCTL */ 58 #define NANDC_V9_FL_RST BIT(0) 59 #define NANDC_V9_FL_DIR_S 0x1 60 #define NANDC_V9_FL_XFER_START BIT(2) 61 #define NANDC_V9_FL_XFER_EN BIT(3) 62 #define NANDC_V9_FL_ST_BUF_S 0x4 63 #define NANDC_V9_FL_XFER_COUNT BIT(5) 64 #define NANDC_V9_FL_ACORRECT BIT(10) 65 #define NANDC_V9_FL_XFER_READY BIT(20) 66 67 /* BCHCTL */ 68 #define NAND_V9_BCH_MODE_S 25 69 #define NAND_V9_BCH_MODE_M 0x7 70 71 /* BCHST */ 72 #define NANDC_V9_BCH0_ST_ERR BIT(2) 73 #define NANDC_V9_BCH1_ST_ERR BIT(18) 74 #define NANDC_V9_ECC_ERR_CNT0(x) (((x) & (0x7F << 3)) >> 3) 75 #define NANDC_V9_ECC_ERR_CNT1(x) (((x) & (0x7F << 19)) >> 19) 76 77 struct rk_nand { 78 uint32_t banks[NANDC_V9_NUM_BANKS]; 79 struct nand_hw_control controller; 80 uint32_t ecc_strength; 81 uint32_t max_ecc_strength; 82 struct mtd_info mtd; 83 bool bootromblocks; 84 void __iomem *regs; 85 int selected_bank; 86 struct udevice *dev; 87 }; 88 89 static struct nand_ecclayout nand_oob_fix = { 90 .eccbytes = 24, 91 .eccpos = { 92 4, 5, 6, 7, 8, 9, 10 93 }, 94 .oobfree = { 95 { 96 .offset = 0, 97 .length = 4 98 } 99 } 100 }; 101 102 static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl) 103 { 104 return container_of(ctrl, struct rk_nand, controller); 105 } 106 107 static void rockchip_nand_init(struct rk_nand *rknand) 108 { 109 writel(0, rknand->regs + NANDC_REG_V9_RANDMZ); 110 writel(0, rknand->regs + NANDC_REG_V9_DMA_CFG); 111 writel(0, rknand->regs + NANDC_REG_V9_BCHCTL); 112 writel(NANDC_V9_FM_WP, rknand->regs + NANDC_REG_V9_FMCTL); 113 writel(0x1081, rknand->regs + NANDC_REG_V9_FMWAIT); 114 } 115 116 static void rockchip_nand_select_chip(struct mtd_info *mtd, int chipnr) 117 { 118 struct nand_chip *chip = mtd_to_nand(mtd); 119 struct rk_nand *rknand = to_rknand(chip->controller); 120 void __iomem *bank_base; 121 uint32_t reg; 122 int banknr; 123 124 reg = readl(rknand->regs + NANDC_REG_V9_FMCTL); 125 reg &= ~NANDC_V9_FM_CE_SEL_M; 126 127 if (chipnr == -1) { 128 banknr = -1; 129 } else { 130 banknr = rknand->banks[chipnr]; 131 bank_base = rknand->regs + NANDC_REG_V9_BANK0 + banknr * 0x100; 132 133 chip->IO_ADDR_R = bank_base; 134 chip->IO_ADDR_W = bank_base; 135 136 reg |= 1 << banknr; 137 } 138 writel(reg, rknand->regs + NANDC_REG_V9_FMCTL); 139 140 rknand->selected_bank = banknr; 141 } 142 143 static void rockchip_nand_cmd_ctrl(struct mtd_info *mtd, 144 int dat, 145 unsigned int ctrl) 146 { 147 struct nand_chip *chip = mtd_to_nand(mtd); 148 struct rk_nand *rknand = to_rknand(chip->controller); 149 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0 150 + rknand->selected_bank * 0x100; 151 152 if (ctrl & NAND_CTRL_CHANGE) { 153 if (ctrl & NAND_ALE) 154 bank_base += NANDC_REG_V9_ADDR; 155 else if (ctrl & NAND_CLE) 156 bank_base += NANDC_REG_V9_CMD; 157 chip->IO_ADDR_W = bank_base; 158 } 159 160 if (dat != NAND_CMD_NONE) 161 writeb(dat & 0xFF, chip->IO_ADDR_W); 162 } 163 164 static void rockchip_nand_read_buf(struct mtd_info *mtd, 165 uint8_t *buf, 166 int len) 167 { 168 struct nand_chip *chip = mtd_to_nand(mtd); 169 struct rk_nand *rknand = to_rknand(chip->controller); 170 int offs = 0; 171 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0 172 + rknand->selected_bank * 0x100; 173 174 for (offs = 0; offs < len; offs++) 175 buf[offs] = readb(bank_base); 176 } 177 178 static void rockchip_nand_write_buf(struct mtd_info *mtd, 179 const uint8_t *buf, 180 int len) 181 { 182 struct nand_chip *chip = mtd_to_nand(mtd); 183 struct rk_nand *rknand = to_rknand(chip->controller); 184 int offs = 0; 185 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0 186 + rknand->selected_bank * 0x100; 187 188 for (offs = 0; offs < len; offs++) 189 writeb(buf[offs], bank_base); 190 } 191 192 static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) 193 { 194 uint8_t ret; 195 196 rockchip_nand_read_buf(mtd, &ret, 1); 197 198 return ret; 199 } 200 201 static int rockchip_nand_dev_ready(struct mtd_info *mtd) 202 { 203 struct nand_chip *chip = mtd_to_nand(mtd); 204 struct rk_nand *rknand = to_rknand(chip->controller); 205 206 if (readl(rknand->regs + NANDC_REG_V9_FMCTL) & NANDC_V9_FM_FREADY) 207 return 1; 208 209 return 0; 210 } 211 212 static int rockchip_nand_hw_ecc_setup(struct mtd_info *mtd, 213 struct nand_ecc_ctrl *ecc, 214 uint32_t strength) 215 { 216 struct nand_chip *chip = mtd_to_nand(mtd); 217 struct rk_nand *rknand = to_rknand(chip->controller); 218 u32 reg; 219 220 ecc->strength = strength; 221 ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8); 222 ecc->bytes = ALIGN(ecc->bytes, 2); 223 224 switch (ecc->strength) { 225 case 70: 226 reg = 0x00000001; 227 break; 228 case 60: 229 reg = 0x06000001; 230 break; 231 case 40: 232 reg = 0x04000001; 233 break; 234 case 16: 235 reg = 0x02000001; 236 break; 237 default: 238 return -EINVAL; 239 } 240 writel(reg, rknand->regs + NANDC_REG_V9_BCHCTL); 241 242 return 0; 243 } 244 245 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, 246 u8 dir, 247 u8 st_buf) 248 { 249 u32 reg; 250 251 reg = (dir << NANDC_V9_FL_DIR_S) | (st_buf << NANDC_V9_FL_ST_BUF_S) | 252 NANDC_V9_FL_XFER_EN | NANDC_V9_FL_XFER_COUNT | 253 NANDC_V9_FL_ACORRECT; 254 writel(reg, rknand->regs + NANDC_REG_V9_FLCTL); 255 256 reg |= NANDC_V9_FL_XFER_START; 257 writel(reg, rknand->regs + NANDC_REG_V9_FLCTL); 258 } 259 260 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) 261 { 262 int timeout = NANDC_V9_DEF_TIMEOUT; 263 int reg; 264 265 while (timeout--) { 266 reg = readl(rknand->regs + NANDC_REG_V9_FLCTL); 267 268 if ((reg & NANDC_V9_FL_XFER_READY) != 0) 269 break; 270 271 udelay(1); 272 } 273 274 if (timeout == 0) 275 return -1; 276 277 return 0; 278 } 279 280 static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob) 281 { 282 struct nand_chip *chip = mtd_to_nand(mtd); 283 struct nand_ecc_ctrl *ecc = &chip->ecc; 284 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); 285 int len = mtd->oobsize - offset; 286 287 if (len <= 0) 288 return; 289 290 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1); 291 292 rockchip_nand_read_buf(mtd, oob + offset, len); 293 } 294 295 static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8 *oob) 296 { 297 struct nand_chip *chip = mtd_to_nand(mtd); 298 struct nand_ecc_ctrl *ecc = &chip->ecc; 299 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); 300 int len = mtd->oobsize - offset; 301 302 if (len <= 0) 303 return; 304 305 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1); 306 307 rockchip_nand_write_buf(mtd, oob + offset, len); 308 } 309 310 static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info *mtd, 311 struct nand_chip *chip, 312 uint8_t *buf, 313 int oob_required, 314 int page) 315 { 316 struct rk_nand *rknand = to_rknand(chip->controller); 317 struct nand_ecc_ctrl *ecc = &chip->ecc; 318 void __iomem *sram_base = rknand->regs + NANDC_REG_V9_SRAM0; 319 unsigned int max_bitflips = 0; 320 int ret, step, bch_st; 321 int offset = page * mtd->writesize; 322 323 if (rknand->bootromblocks && (offset < (4 * mtd->erasesize))) 324 rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V9_BOOTROM_ECC); 325 326 rockchip_nand_pio_xfer_start(rknand, NANDC_V9_READ, 0); 327 328 for (step = 0; step < ecc->steps; step++) { 329 int data_off = step * ecc->size; 330 int oob_off = step * (ecc->bytes + ecc->prepad); 331 u8 *data = buf + data_off; 332 u8 *oob = chip->oob_poi + oob_off; 333 334 ret = rockchip_nand_wait_pio_xfer_done(rknand); 335 if (ret) 336 return ret; 337 338 bch_st = readl(rknand->regs + NANDC_REG_V9_BCHST); 339 340 if (bch_st & NANDC_V9_BCH0_ST_ERR) { 341 mtd->ecc_stats.failed++; 342 max_bitflips = -1; 343 } else { 344 ret = NANDC_V9_ECC_ERR_CNT0(bch_st); 345 mtd->ecc_stats.corrected += ret; 346 max_bitflips = max_t(unsigned int, max_bitflips, ret); 347 } 348 349 if ((step + 1) < ecc->steps) 350 rockchip_nand_pio_xfer_start(rknand, NANDC_V9_READ, 351 (step + 1) & 0x1); 352 353 memcpy_fromio(data, sram_base + NANDC_REG_V9_SRAM_SIZE * 354 (step & 1), ecc->size); 355 356 if (step & 1) 357 memcpy_fromio(oob, rknand->regs + NANDC_REG_V9_SPARE1, 4); 358 else 359 memcpy_fromio(oob, rknand->regs + NANDC_REG_V9_SPARE0, 4); 360 } 361 362 rockchip_nand_read_extra_oob(mtd, chip->oob_poi); 363 364 if (rknand->bootromblocks) 365 rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); 366 367 return max_bitflips; 368 } 369 370 static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd, 371 int page, 372 const u8 *oob, 373 bool bootromblocks) 374 { 375 int pages_per_block = mtd->erasesize / mtd->writesize; 376 int offset = page * mtd->writesize; 377 378 if ((offset < (2 * mtd->erasesize)) || !(page % 2) || 379 (offset >= (7 * mtd->erasesize)) || !bootromblocks) 380 return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] << 24); 381 382 return (page % pages_per_block + 1) * 4; 383 } 384 385 static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info *mtd, 386 struct nand_chip *chip, 387 const uint8_t *buf, 388 int oob_required, 389 int page) 390 { 391 struct rk_nand *rknand = to_rknand(chip->controller); 392 struct nand_ecc_ctrl *ecc = &chip->ecc; 393 void __iomem *sram_base = rknand->regs + NANDC_REG_V9_SRAM0; 394 int ret, index, step = 0; 395 int offset = page * mtd->writesize; 396 int data_off = step * ecc->size; 397 int oob_off = step * (ecc->bytes + ecc->prepad); 398 const u8 *data = buf + data_off; 399 const u8 *oob = chip->oob_poi + oob_off; 400 401 if (rknand->bootromblocks && (offset < (7 * mtd->erasesize))) 402 rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V9_BOOTROM_ECC); 403 404 index = rockchip_nand_make_bootrom_compat(mtd, page, oob, 405 rknand->bootromblocks); 406 407 memcpy_toio(sram_base, data, ecc->size); 408 memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE0, &index, ecc->prepad); 409 410 for (step = 1; step <= ecc->steps; step++) { 411 rockchip_nand_pio_xfer_start(rknand, NANDC_V9_WRITE, 412 (step - 1) & 0x1); 413 data_off = step * ecc->size; 414 oob_off = step * (ecc->bytes + ecc->prepad); 415 data = buf + data_off; 416 oob = chip->oob_poi + oob_off; 417 418 if (step < ecc->steps) { 419 memcpy_toio(sram_base + NANDC_REG_V9_SRAM_SIZE * 420 (step & 1), data, ecc->size); 421 if (step & 1) 422 memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE1, 423 oob, ecc->prepad); 424 else 425 memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE0, 426 oob, ecc->prepad); 427 } 428 429 ret = rockchip_nand_wait_pio_xfer_done(rknand); 430 if (ret) 431 return ret; 432 } 433 434 rockchip_nand_write_extra_oob(mtd, chip->oob_poi); 435 436 if (rknand->bootromblocks) 437 rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); 438 439 return 0; 440 } 441 442 static const u8 strengths[] = {70, 60, 40, 16}; 443 444 static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd, 445 struct nand_ecc_ctrl *ecc) 446 { 447 uint32_t max_strength, index; 448 449 max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 / 14; 450 451 for (index = 0; index < ARRAY_SIZE(strengths); index++) 452 if (max_strength >= strengths[index]) 453 break; 454 455 if (index >= ARRAY_SIZE(strengths)) 456 return -ENOTSUPP; 457 458 return strengths[index]; 459 } 460 461 static bool rockchip_nand_strength_is_valid(int strength) 462 { 463 uint32_t index; 464 465 for (index = 0; index < ARRAY_SIZE(strengths); index++) 466 if (strength == strengths[index]) 467 break; 468 469 if (index == ARRAY_SIZE(strengths)) 470 return false; 471 472 return true; 473 } 474 475 static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 476 struct nand_ecc_ctrl *ecc) 477 { 478 struct nand_chip *chip = mtd_to_nand(mtd); 479 struct rk_nand *rknand = to_rknand(chip->controller); 480 uint32_t strength; 481 int index; 482 483 ecc->prepad = 4; 484 ecc->steps = mtd->writesize / ecc->size; 485 486 if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node, 487 "rockchip,protect-bootrom-blocks")) 488 rknand->bootromblocks = true; 489 else 490 rknand->bootromblocks = false; 491 492 if (rockchip_nand_strength_is_valid(ecc->strength)) 493 strength = ecc->strength; 494 else 495 strength = rockchip_nand_ecc_max_strength(mtd, ecc); 496 497 rknand->max_ecc_strength = 70; 498 if (strength > rknand->max_ecc_strength) 499 strength = rknand->max_ecc_strength; 500 501 rockchip_nand_hw_ecc_setup(mtd, ecc, strength); 502 503 rknand->ecc_strength = ecc->strength; 504 505 nand_oob_fix.eccbytes = ecc->bytes * ecc->steps; 506 for (index = 0; index < ecc->bytes; index++) 507 nand_oob_fix.eccpos[index] = index + ecc->prepad; 508 ecc->layout = &nand_oob_fix; 509 510 if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) { 511 return -EINVAL; 512 } 513 514 return 0; 515 } 516 517 static int rockchip_nand_ecc_init(struct mtd_info *mtd, 518 struct nand_ecc_ctrl *ecc) 519 { 520 int ret; 521 522 switch (ecc->mode) { 523 case NAND_ECC_HW_SYNDROME: 524 ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc); 525 if (ret) 526 return ret; 527 ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page; 528 ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page; 529 break; 530 case NAND_ECC_SOFT_BCH: 531 case NAND_ECC_NONE: 532 case NAND_ECC_SOFT: 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 return 0; 539 } 540 541 static int rockchip_nand_block_bad(struct mtd_info *mtd, loff_t ofs) 542 { 543 int page, res = 0, i; 544 struct nand_chip *chip = mtd_to_nand(mtd); 545 u16 bad = 0xff; 546 int chipnr = (int)(ofs >> chip->chip_shift); 547 548 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 549 chip->select_chip(mtd, chipnr); 550 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 551 if(rockchip_nand_hw_syndrome_pio_read_page(mtd, 552 chip, chip->buffers->databuf, 0, page) == -1) { 553 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 554 for (i = 0; i < 8; i++) { 555 bad = chip->read_byte(mtd); 556 if (bad) 557 break; 558 } 559 if (i >= 8) 560 res = 1; 561 } 562 chip->select_chip(mtd, -1); 563 if (res) 564 printf("%s 0x%x %x %x\n", __func__, page, res, bad); 565 return res; 566 } 567 568 static int rockchip_nand_chip_init(int node, struct rk_nand *rknand, int devnum) 569 { 570 const void *blob = gd->fdt_blob; 571 struct nand_chip *chip; 572 struct mtd_info *mtd; 573 int ret; 574 575 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 576 577 chip->chip_delay = 50; 578 chip->flash_node = node; 579 chip->select_chip = rockchip_nand_select_chip; 580 chip->cmd_ctrl = rockchip_nand_cmd_ctrl; 581 chip->read_buf = rockchip_nand_read_buf; 582 chip->write_buf = rockchip_nand_write_buf; 583 chip->read_byte = rockchip_nand_read_byte; 584 chip->dev_ready = rockchip_nand_dev_ready; 585 chip->controller = &rknand->controller; 586 chip->block_bad = rockchip_nand_block_bad; 587 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 588 chip->options = NAND_NO_SUBPAGE_WRITE; 589 590 rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1); 591 592 if (rknand->banks[devnum] < 0) 593 return -EINVAL; 594 595 mtd = nand_to_mtd(chip); 596 mtd->dev = rknand->dev; 597 if (rknand->dev) 598 rknand->dev->priv = mtd; 599 600 ret = nand_scan_ident(mtd, 1, NULL); 601 if (ret) 602 return ret; 603 604 ret = rockchip_nand_ecc_init(mtd, &chip->ecc); 605 if (ret) { 606 debug("rockchip_nand_ecc_init failed: %d\n", ret); 607 return ret; 608 } 609 610 ret = nand_scan_tail(mtd); 611 if (ret) { 612 debug("nand_scan_tail failed: %d\n", ret); 613 return ret; 614 } 615 616 ret = nand_register(devnum, mtd); 617 if (ret) { 618 debug("Failed to register mtd device: %d\n", ret); 619 return ret; 620 } 621 mtd->name = "rk-nand"; 622 return 0; 623 } 624 625 static int rockchip_nand_chips_init(int node, struct rk_nand *rknand) 626 { 627 const void *blob = gd->fdt_blob; 628 int nand_node; 629 int ret, i = 0; 630 631 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0; 632 nand_node = fdt_next_subnode(blob, nand_node)) { 633 ret = rockchip_nand_chip_init(nand_node, rknand, i++); 634 if (ret) 635 return ret; 636 } 637 638 return 0; 639 } 640 641 #ifdef CONFIG_NAND_ROCKCHIP_DT 642 static const struct udevice_id rockchip_nandc_ids[] = { 643 { .compatible = "rockchip,rk-nandc" }, 644 { } 645 }; 646 647 static int rockchip_nandc_probe(struct udevice *dev) 648 { 649 const void *blob = gd->fdt_blob; 650 struct rk_nand *rknand = dev_get_priv(dev); 651 fdt_addr_t regs; 652 int ret = 0, node; 653 654 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 655 656 rknand->dev = dev; 657 658 regs = dev_read_addr(dev); 659 if (regs == FDT_ADDR_T_NONE) { 660 debug("Nand address not found\n"); 661 return ret; 662 } 663 664 rknand->regs = (void *)regs; 665 666 spin_lock_init(&rknand->controller.lock); 667 init_waitqueue_head(&rknand->controller.wq); 668 669 rockchip_nand_init(rknand); 670 671 ret = rockchip_nand_chips_init(node, rknand); 672 if (ret) 673 debug("Failed to init nand chips\n"); 674 675 return ret; 676 } 677 678 static int rockchip_nandc_bind(struct udevice *udev) 679 { 680 int ret = 0; 681 682 #ifdef CONFIG_MTD_BLK 683 struct udevice *bdev; 684 685 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD, 686 0, 512, 0, &bdev); 687 if (ret) 688 printf("Cannot create block device\n"); 689 #endif 690 return ret; 691 } 692 693 U_BOOT_DRIVER(rk_nandc_v9) = { 694 .name = "rk_nandc_v9", 695 .id = UCLASS_MTD, 696 .of_match = rockchip_nandc_ids, 697 .bind = rockchip_nandc_bind, 698 .probe = rockchip_nandc_probe, 699 .priv_auto_alloc_size = sizeof(struct rk_nand), 700 }; 701 702 void board_nand_init(void) 703 { 704 struct udevice *dev; 705 int ret; 706 707 ret = uclass_get_device_by_driver(UCLASS_MTD, 708 DM_GET_DRIVER(rk_nandc_v9), 709 &dev); 710 if (ret && ret != -ENODEV) 711 pr_err("Failed to initialize NAND controller. (error %d)\n", 712 ret); 713 } 714 #else 715 716 void board_nand_init(void) 717 { 718 const void *blob = gd->fdt_blob; 719 struct rk_nand *rknand; 720 fdt_addr_t regs; 721 int node; 722 int ret; 723 724 rknand = kzalloc(sizeof(*rknand), GFP_KERNEL); 725 726 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 727 728 if (node < 0) { 729 debug("Nand node not found\n"); 730 goto err; 731 } 732 733 if (!fdtdec_get_is_enabled(blob, node)) { 734 debug("Nand disabled in device tree\n"); 735 goto err; 736 } 737 738 regs = fdt_get_base_address(blob, node); 739 if (regs == FDT_ADDR_T_NONE) { 740 debug("Nand address not found\n"); 741 goto err; 742 } 743 744 rknand->regs = (void *)regs; 745 746 spin_lock_init(&rknand->controller.lock); 747 init_waitqueue_head(&rknand->controller.wq); 748 749 rockchip_nand_init(rknand); 750 751 ret = rockchip_nand_chips_init(node, rknand); 752 if (ret) { 753 debug("Failed to init nand chips\n"); 754 goto err; 755 } 756 757 return; 758 err: 759 kfree(rknand); 760 } 761 762 #endif 763 764 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) 765 { 766 struct mtd_info *mtd; 767 size_t length = size; 768 769 mtd = get_nand_dev_by_index(0); 770 return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst); 771 } 772 773 void nand_deselect(void) {} 774