1 /* 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com> 3 * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <inttypes.h> 12 #include <nand.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/kernel.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/nand.h> 18 #include <linux/mtd/partitions.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #ifdef CONFIG_ROCKCHIP_RK3568 23 #define NANDC_V9_BOOTROM_ECC 16 24 #else 25 #define NANDC_V9_BOOTROM_ECC 70 26 #endif 27 #define NANDC_V9_NUM_BANKS 4 28 #define NANDC_V9_DEF_TIMEOUT 20000 29 #define NANDC_V9_READ 0 30 #define NANDC_V9_WRITE 1 31 #define NANDC_REG_V9_FMCTL 0x00 32 #define NANDC_REG_V9_FMWAIT 0x04 33 #define NANDC_REG_V9_FLCTL 0x10 34 #define NANDC_REG_V9_BCHCTL 0x20 35 #define NANDC_REG_V9_DMA_CFG 0x30 36 #define NANDC_REG_V9_DMA_BUF0 0x34 37 #define NANDC_REG_V9_DMA_BUF1 0x38 38 #define NANDC_REG_V9_DMA_ST 0x40 39 #define NANDC_REG_V9_VER 0x80 40 #define NANDC_REG_V9_INTEN 0x120 41 #define NANDC_REG_V9_INTCLR 0x124 42 #define NANDC_REG_V9_INTST 0x128 43 #define NANDC_REG_V9_BCHST 0x150 44 #define NANDC_REG_V9_SPARE0 0x200 45 #define NANDC_REG_V9_SPARE1 0x204 46 #define NANDC_REG_V9_RANDMZ 0x208 47 #define NANDC_REG_V9_BANK0 0x800 48 #define NANDC_REG_V9_SRAM0 0x1000 49 #define NANDC_REG_V9_SRAM_SIZE 0x400 50 51 #define NANDC_REG_V9_DATA 0x00 52 #define NANDC_REG_V9_ADDR 0x04 53 #define NANDC_REG_V9_CMD 0x08 54 55 /* FMCTL */ 56 #define NANDC_V9_FM_WP BIT(8) 57 #define NANDC_V9_FM_CE_SEL_M 0xFF 58 #define NANDC_V9_FM_CE_SEL(x) (1 << (x)) 59 #define NANDC_V9_FM_FREADY BIT(9) 60 61 /* FLCTL */ 62 #define NANDC_V9_FL_RST BIT(0) 63 #define NANDC_V9_FL_DIR_S 0x1 64 #define NANDC_V9_FL_XFER_START BIT(2) 65 #define NANDC_V9_FL_XFER_EN BIT(3) 66 #define NANDC_V9_FL_ST_BUF_S 0x4 67 #define NANDC_V9_FL_XFER_COUNT BIT(5) 68 #define NANDC_V9_FL_ACORRECT BIT(10) 69 #define NANDC_V9_FL_XFER_READY BIT(20) 70 #define NANDC_V9_FL_ASYNC_TOG_MIX BIT(29) 71 72 /* BCHCTL */ 73 #define NAND_V9_BCH_MODE_S 25 74 #define NAND_V9_BCH_MODE_M 0x7 75 76 /* BCHST */ 77 #define NANDC_V9_BCH0_ST_ERR BIT(2) 78 #define NANDC_V9_BCH1_ST_ERR BIT(18) 79 #define NANDC_V9_ECC_ERR_CNT0(x) (((x) & (0x7F << 3)) >> 3) 80 #define NANDC_V9_ECC_ERR_CNT1(x) (((x) & (0x7F << 19)) >> 19) 81 82 struct rk_nand { 83 uint32_t banks[NANDC_V9_NUM_BANKS]; 84 struct nand_hw_control controller; 85 uint32_t ecc_strength; 86 struct mtd_info mtd; 87 bool bootromblocks; 88 void __iomem *regs; 89 int selected_bank; 90 struct udevice *dev; 91 }; 92 93 static struct nand_ecclayout nand_oob_fix = { 94 .eccbytes = 24, 95 .eccpos = { 96 4, 5, 6, 7, 8, 9, 10 97 }, 98 .oobfree = { 99 { 100 .offset = 0, 101 .length = 4 102 } 103 } 104 }; 105 106 static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl) 107 { 108 return container_of(ctrl, struct rk_nand, controller); 109 } 110 111 static void rockchip_nand_init(struct rk_nand *rknand) 112 { 113 writel(0, rknand->regs + NANDC_REG_V9_RANDMZ); 114 writel(0, rknand->regs + NANDC_REG_V9_DMA_CFG); 115 writel(0, rknand->regs + NANDC_REG_V9_BCHCTL); 116 writel(NANDC_V9_FM_WP, rknand->regs + NANDC_REG_V9_FMCTL); 117 writel(0x1081, rknand->regs + NANDC_REG_V9_FMWAIT); 118 } 119 120 static void rockchip_nand_select_chip(struct mtd_info *mtd, int chipnr) 121 { 122 struct nand_chip *chip = mtd_to_nand(mtd); 123 struct rk_nand *rknand = to_rknand(chip->controller); 124 void __iomem *bank_base; 125 uint32_t reg; 126 int banknr; 127 128 reg = readl(rknand->regs + NANDC_REG_V9_FMCTL); 129 reg &= ~NANDC_V9_FM_CE_SEL_M; 130 131 if (chipnr == -1) { 132 banknr = -1; 133 } else { 134 banknr = rknand->banks[chipnr]; 135 bank_base = rknand->regs + NANDC_REG_V9_BANK0 + banknr * 0x100; 136 137 chip->IO_ADDR_R = bank_base; 138 chip->IO_ADDR_W = bank_base; 139 140 reg |= 1 << banknr; 141 } 142 writel(reg, rknand->regs + NANDC_REG_V9_FMCTL); 143 144 rknand->selected_bank = banknr; 145 } 146 147 static void rockchip_nand_cmd_ctrl(struct mtd_info *mtd, 148 int dat, 149 unsigned int ctrl) 150 { 151 struct nand_chip *chip = mtd_to_nand(mtd); 152 struct rk_nand *rknand = to_rknand(chip->controller); 153 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0 154 + rknand->selected_bank * 0x100; 155 156 if (ctrl & NAND_CTRL_CHANGE) { 157 if (ctrl & NAND_ALE) 158 bank_base += NANDC_REG_V9_ADDR; 159 else if (ctrl & NAND_CLE) 160 bank_base += NANDC_REG_V9_CMD; 161 chip->IO_ADDR_W = bank_base; 162 } 163 164 if (dat != NAND_CMD_NONE) 165 writeb(dat & 0xFF, chip->IO_ADDR_W); 166 } 167 168 static void rockchip_nand_read_buf(struct mtd_info *mtd, 169 uint8_t *buf, 170 int len) 171 { 172 struct nand_chip *chip = mtd_to_nand(mtd); 173 struct rk_nand *rknand = to_rknand(chip->controller); 174 int offs = 0; 175 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0 176 + rknand->selected_bank * 0x100; 177 178 for (offs = 0; offs < len; offs++) 179 buf[offs] = readb(bank_base); 180 } 181 182 static void rockchip_nand_write_buf(struct mtd_info *mtd, 183 const uint8_t *buf, 184 int len) 185 { 186 struct nand_chip *chip = mtd_to_nand(mtd); 187 struct rk_nand *rknand = to_rknand(chip->controller); 188 int offs = 0; 189 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0 190 + rknand->selected_bank * 0x100; 191 192 for (offs = 0; offs < len; offs++) 193 writeb(buf[offs], bank_base); 194 } 195 196 static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) 197 { 198 uint8_t ret; 199 200 rockchip_nand_read_buf(mtd, &ret, 1); 201 202 return ret; 203 } 204 205 static int rockchip_nand_dev_ready(struct mtd_info *mtd) 206 { 207 struct nand_chip *chip = mtd_to_nand(mtd); 208 struct rk_nand *rknand = to_rknand(chip->controller); 209 210 if (readl(rknand->regs + NANDC_REG_V9_FMCTL) & NANDC_V9_FM_FREADY) 211 return 1; 212 213 return 0; 214 } 215 216 static int rockchip_nand_hw_ecc_setup(struct mtd_info *mtd, 217 struct nand_ecc_ctrl *ecc, 218 uint32_t strength) 219 { 220 struct nand_chip *chip = mtd_to_nand(mtd); 221 struct rk_nand *rknand = to_rknand(chip->controller); 222 u32 reg; 223 224 ecc->strength = strength; 225 ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8); 226 ecc->bytes = ALIGN(ecc->bytes, 2); 227 228 switch (ecc->strength) { 229 case 70: 230 reg = 0x00000001; 231 break; 232 case 60: 233 reg = 0x06000001; 234 break; 235 case 40: 236 reg = 0x04000001; 237 break; 238 case 16: 239 reg = 0x02000001; 240 break; 241 default: 242 return -EINVAL; 243 } 244 writel(reg, rknand->regs + NANDC_REG_V9_BCHCTL); 245 246 return 0; 247 } 248 249 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, 250 u8 dir, 251 u8 st_buf) 252 { 253 u32 reg; 254 255 reg = (dir << NANDC_V9_FL_DIR_S) | (st_buf << NANDC_V9_FL_ST_BUF_S) | 256 NANDC_V9_FL_XFER_EN | NANDC_V9_FL_XFER_COUNT | 257 NANDC_V9_FL_ACORRECT | NANDC_V9_FL_ASYNC_TOG_MIX; 258 writel(reg, rknand->regs + NANDC_REG_V9_FLCTL); 259 260 reg |= NANDC_V9_FL_XFER_START; 261 writel(reg, rknand->regs + NANDC_REG_V9_FLCTL); 262 } 263 264 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) 265 { 266 int timeout = NANDC_V9_DEF_TIMEOUT; 267 int reg; 268 269 while (timeout--) { 270 reg = readl(rknand->regs + NANDC_REG_V9_FLCTL); 271 272 if ((reg & NANDC_V9_FL_XFER_READY) != 0) 273 break; 274 275 udelay(1); 276 } 277 278 if (timeout == 0) 279 return -1; 280 281 return 0; 282 } 283 284 static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob) 285 { 286 struct nand_chip *chip = mtd_to_nand(mtd); 287 struct nand_ecc_ctrl *ecc = &chip->ecc; 288 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); 289 int len = mtd->oobsize - offset; 290 291 if (len <= 0) 292 return; 293 294 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1); 295 296 rockchip_nand_read_buf(mtd, oob + offset, len); 297 } 298 299 static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8 *oob) 300 { 301 struct nand_chip *chip = mtd_to_nand(mtd); 302 struct nand_ecc_ctrl *ecc = &chip->ecc; 303 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); 304 int len = mtd->oobsize - offset; 305 306 if (len <= 0) 307 return; 308 309 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1); 310 311 rockchip_nand_write_buf(mtd, oob + offset, len); 312 } 313 314 static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info *mtd, 315 struct nand_chip *chip, 316 uint8_t *buf, 317 int oob_required, 318 int page) 319 { 320 struct rk_nand *rknand = to_rknand(chip->controller); 321 struct nand_ecc_ctrl *ecc = &chip->ecc; 322 void __iomem *sram_base = rknand->regs + NANDC_REG_V9_SRAM0; 323 unsigned int max_bitflips = 0; 324 int ret, step, bch_st; 325 int offset = page * mtd->writesize; 326 327 if (rknand->bootromblocks && (offset < (4 * mtd->erasesize))) 328 rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V9_BOOTROM_ECC); 329 330 rockchip_nand_pio_xfer_start(rknand, NANDC_V9_READ, 0); 331 332 for (step = 0; step < ecc->steps; step++) { 333 int data_off = step * ecc->size; 334 int oob_off = step * (ecc->bytes + ecc->prepad); 335 u8 *data = buf + data_off; 336 u8 *oob = chip->oob_poi + oob_off; 337 338 ret = rockchip_nand_wait_pio_xfer_done(rknand); 339 if (ret) 340 return ret; 341 342 bch_st = readl(rknand->regs + NANDC_REG_V9_BCHST); 343 344 if (bch_st & NANDC_V9_BCH0_ST_ERR) { 345 mtd->ecc_stats.failed++; 346 max_bitflips = -1; 347 } else { 348 ret = NANDC_V9_ECC_ERR_CNT0(bch_st); 349 mtd->ecc_stats.corrected += ret; 350 max_bitflips = max_t(unsigned int, max_bitflips, ret); 351 } 352 353 if ((step + 1) < ecc->steps) 354 rockchip_nand_pio_xfer_start(rknand, NANDC_V9_READ, 355 (step + 1) & 0x1); 356 357 memcpy_fromio(data, sram_base + NANDC_REG_V9_SRAM_SIZE * 358 (step & 1), ecc->size); 359 360 if (step & 1) 361 memcpy_fromio(oob, rknand->regs + NANDC_REG_V9_SPARE1, 4); 362 else 363 memcpy_fromio(oob, rknand->regs + NANDC_REG_V9_SPARE0, 4); 364 } 365 366 rockchip_nand_read_extra_oob(mtd, chip->oob_poi); 367 368 if (rknand->bootromblocks) 369 rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); 370 371 return max_bitflips; 372 } 373 374 static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd, 375 int page, 376 const u8 *oob, 377 bool bootromblocks) 378 { 379 int pages_per_block = mtd->erasesize / mtd->writesize; 380 int offset = page * mtd->writesize; 381 382 if ((offset < (2 * mtd->erasesize)) || !(page % 2) || 383 (offset >= (7 * mtd->erasesize)) || !bootromblocks) 384 return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] << 24); 385 386 return (page % pages_per_block + 1) * 4; 387 } 388 389 static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info *mtd, 390 struct nand_chip *chip, 391 const uint8_t *buf, 392 int oob_required, 393 int page) 394 { 395 struct rk_nand *rknand = to_rknand(chip->controller); 396 struct nand_ecc_ctrl *ecc = &chip->ecc; 397 void __iomem *sram_base = rknand->regs + NANDC_REG_V9_SRAM0; 398 int ret, index, step = 0; 399 int offset = page * mtd->writesize; 400 int data_off = step * ecc->size; 401 int oob_off = step * (ecc->bytes + ecc->prepad); 402 const u8 *data = buf + data_off; 403 const u8 *oob = chip->oob_poi + oob_off; 404 405 if (rknand->bootromblocks && (offset < (7 * mtd->erasesize))) 406 rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V9_BOOTROM_ECC); 407 408 index = rockchip_nand_make_bootrom_compat(mtd, page, oob, 409 rknand->bootromblocks); 410 411 memcpy_toio(sram_base, data, ecc->size); 412 memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE0, &index, ecc->prepad); 413 414 for (step = 1; step <= ecc->steps; step++) { 415 rockchip_nand_pio_xfer_start(rknand, NANDC_V9_WRITE, 416 (step - 1) & 0x1); 417 data_off = step * ecc->size; 418 oob_off = step * (ecc->bytes + ecc->prepad); 419 data = buf + data_off; 420 oob = chip->oob_poi + oob_off; 421 422 if (step < ecc->steps) { 423 memcpy_toio(sram_base + NANDC_REG_V9_SRAM_SIZE * 424 (step & 1), data, ecc->size); 425 if (step & 1) 426 memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE1, 427 oob, ecc->prepad); 428 else 429 memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE0, 430 oob, ecc->prepad); 431 } 432 433 ret = rockchip_nand_wait_pio_xfer_done(rknand); 434 if (ret) 435 return ret; 436 } 437 438 rockchip_nand_write_extra_oob(mtd, chip->oob_poi); 439 440 if (rknand->bootromblocks) 441 rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); 442 443 return 0; 444 } 445 446 static const u8 strengths[] = {70, 60, 40, 16}; 447 448 static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd, 449 struct nand_ecc_ctrl *ecc) 450 { 451 uint32_t max_strength, index; 452 453 max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 / 14; 454 455 for (index = 0; index < ARRAY_SIZE(strengths); index++) 456 if (max_strength >= strengths[index]) 457 break; 458 459 if (index >= ARRAY_SIZE(strengths)) 460 return -ENOTSUPP; 461 462 return strengths[index]; 463 } 464 465 static bool rockchip_nand_strength_is_valid(int strength) 466 { 467 uint32_t index; 468 469 for (index = 0; index < ARRAY_SIZE(strengths); index++) 470 if (strength == strengths[index]) 471 break; 472 473 if (index == ARRAY_SIZE(strengths)) 474 return false; 475 476 return true; 477 } 478 479 static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 480 struct nand_ecc_ctrl *ecc) 481 { 482 struct nand_chip *chip = mtd_to_nand(mtd); 483 struct rk_nand *rknand = to_rknand(chip->controller); 484 uint32_t strength; 485 int index; 486 487 ecc->prepad = 4; 488 ecc->steps = mtd->writesize / ecc->size; 489 490 if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node, 491 "rockchip,protect-bootrom-blocks")) 492 rknand->bootromblocks = true; 493 else 494 rknand->bootromblocks = false; 495 496 if (rockchip_nand_strength_is_valid(ecc->strength)) 497 strength = ecc->strength; 498 else 499 strength = rockchip_nand_ecc_max_strength(mtd, ecc); 500 501 rockchip_nand_hw_ecc_setup(mtd, ecc, strength); 502 503 rknand->ecc_strength = ecc->strength; 504 505 nand_oob_fix.eccbytes = ecc->bytes * ecc->steps; 506 for (index = 0; index < ecc->bytes; index++) 507 nand_oob_fix.eccpos[index] = index + ecc->prepad; 508 ecc->layout = &nand_oob_fix; 509 510 if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) { 511 return -EINVAL; 512 } 513 514 return 0; 515 } 516 517 static int rockchip_nand_ecc_init(struct mtd_info *mtd, 518 struct nand_ecc_ctrl *ecc) 519 { 520 int ret; 521 522 switch (ecc->mode) { 523 case NAND_ECC_HW: 524 case NAND_ECC_HW_SYNDROME: 525 ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc); 526 if (ret) 527 return ret; 528 ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page; 529 ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page; 530 break; 531 case NAND_ECC_SOFT_BCH: 532 case NAND_ECC_NONE: 533 case NAND_ECC_SOFT: 534 break; 535 default: 536 return -EINVAL; 537 } 538 539 return 0; 540 } 541 542 static int rockchip_nand_block_bad(struct mtd_info *mtd, loff_t ofs) 543 { 544 int page, res = 0; 545 struct nand_chip *chip = mtd_to_nand(mtd); 546 u16 bad = 0xff; 547 int chipnr = (int)(ofs >> chip->chip_shift); 548 549 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 550 chip->select_chip(mtd, chipnr); 551 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 552 if(rockchip_nand_hw_syndrome_pio_read_page(mtd, 553 chip, chip->buffers->databuf, 0, page) == -1) { 554 /* first page of the block*/ 555 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 556 bad = chip->read_byte(mtd); 557 if (bad != 0xFF) 558 res = 1; 559 /* second page of the block*/ 560 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, 561 page + 1); 562 bad = chip->read_byte(mtd); 563 if (bad != 0xFF) 564 res = 1; 565 /* last page of the block */ 566 page += ((mtd->erasesize - mtd->writesize) >> chip->chip_shift); 567 page--; 568 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 569 bad = chip->read_byte(mtd); 570 if (bad != 0xFF) 571 res = 1; 572 } 573 chip->select_chip(mtd, -1); 574 if (res) 575 printf("%s 0x%x %x %x\n", __func__, page, res, bad); 576 return res; 577 } 578 579 static int rockchip_nand_chip_init(int node, struct rk_nand *rknand, int devnum) 580 { 581 const void *blob = gd->fdt_blob; 582 struct nand_chip *chip; 583 struct mtd_info *mtd; 584 int ret; 585 586 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 587 588 chip->chip_delay = 50; 589 chip->flash_node = node; 590 chip->select_chip = rockchip_nand_select_chip; 591 chip->cmd_ctrl = rockchip_nand_cmd_ctrl; 592 chip->read_buf = rockchip_nand_read_buf; 593 chip->write_buf = rockchip_nand_write_buf; 594 chip->read_byte = rockchip_nand_read_byte; 595 chip->dev_ready = rockchip_nand_dev_ready; 596 chip->controller = &rknand->controller; 597 chip->block_bad = rockchip_nand_block_bad; 598 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 599 chip->options = NAND_NO_SUBPAGE_WRITE; 600 601 rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1); 602 603 if (rknand->banks[devnum] < 0) 604 return -EINVAL; 605 606 mtd = nand_to_mtd(chip); 607 mtd->dev = rknand->dev; 608 if (rknand->dev) 609 rknand->dev->priv = mtd; 610 611 ret = nand_scan_ident(mtd, 1, NULL); 612 if (ret) 613 return ret; 614 615 ret = rockchip_nand_ecc_init(mtd, &chip->ecc); 616 if (ret) { 617 debug("rockchip_nand_ecc_init failed: %d\n", ret); 618 return ret; 619 } 620 621 ret = nand_scan_tail(mtd); 622 if (ret) { 623 debug("nand_scan_tail failed: %d\n", ret); 624 return ret; 625 } 626 627 ret = nand_register(devnum, mtd); 628 if (ret) { 629 debug("Failed to register mtd device: %d\n", ret); 630 return ret; 631 } 632 memcpy(&rknand->mtd, mtd, sizeof(struct mtd_info)); 633 634 return 0; 635 } 636 637 static int rockchip_nand_chips_init(int node, struct rk_nand *rknand) 638 { 639 const void *blob = gd->fdt_blob; 640 int nand_node; 641 int ret, i = 0; 642 643 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0; 644 nand_node = fdt_next_subnode(blob, nand_node)) { 645 ret = rockchip_nand_chip_init(nand_node, rknand, i++); 646 if (ret) 647 return ret; 648 } 649 650 return 0; 651 } 652 653 #ifdef CONFIG_NAND_ROCKCHIP_DT 654 static const struct udevice_id rockchip_nandc_ids[] = { 655 { .compatible = "rockchip,rk-nandc" }, 656 { } 657 }; 658 659 static int rockchip_nandc_probe(struct udevice *dev) 660 { 661 const void *blob = gd->fdt_blob; 662 struct rk_nand *rknand = dev_get_priv(dev); 663 struct mtd_info *mtd = dev_get_uclass_priv(dev); 664 fdt_addr_t regs; 665 int ret = 0, node; 666 667 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 668 669 rknand->dev = dev; 670 671 regs = dev_read_addr(dev); 672 if (regs == FDT_ADDR_T_NONE) { 673 debug("Nand address not found\n"); 674 return ret; 675 } 676 677 rknand->regs = (void *)regs; 678 679 spin_lock_init(&rknand->controller.lock); 680 init_waitqueue_head(&rknand->controller.wq); 681 682 rockchip_nand_init(rknand); 683 684 ret = rockchip_nand_chips_init(node, rknand); 685 if (ret) 686 debug("Failed to init nand chips\n"); 687 688 memcpy(mtd, &rknand->mtd, sizeof(struct mtd_info)); 689 690 return ret; 691 } 692 693 static int rockchip_nandc_bind(struct udevice *udev) 694 { 695 int ret = 0; 696 697 #ifdef CONFIG_MTD_BLK 698 struct udevice *bdev; 699 700 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD, 701 BLK_MTD_NAND, 512, 0, &bdev); 702 if (ret) 703 printf("Cannot create block device\n"); 704 #endif 705 return ret; 706 } 707 708 U_BOOT_DRIVER(rk_nandc_v9) = { 709 .name = "rk_nandc_v9", 710 .id = UCLASS_MTD, 711 .of_match = rockchip_nandc_ids, 712 .bind = rockchip_nandc_bind, 713 .probe = rockchip_nandc_probe, 714 .priv_auto_alloc_size = sizeof(struct rk_nand), 715 }; 716 717 void board_nand_init(void) 718 { 719 struct udevice *dev; 720 int ret; 721 722 ret = uclass_get_device_by_driver(UCLASS_MTD, 723 DM_GET_DRIVER(rk_nandc_v9), 724 &dev); 725 if (ret && ret != -ENODEV) 726 pr_err("Failed to initialize NAND controller. (error %d)\n", 727 ret); 728 } 729 #else 730 731 void board_nand_init(void) 732 { 733 const void *blob = gd->fdt_blob; 734 struct rk_nand *rknand; 735 fdt_addr_t regs; 736 int node; 737 int ret; 738 739 rknand = kzalloc(sizeof(*rknand), GFP_KERNEL); 740 741 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 742 743 if (node < 0) { 744 debug("Nand node not found\n"); 745 goto err; 746 } 747 748 if (!fdtdec_get_is_enabled(blob, node)) { 749 debug("Nand disabled in device tree\n"); 750 goto err; 751 } 752 753 regs = fdt_get_base_address(blob, node); 754 if (regs == FDT_ADDR_T_NONE) { 755 debug("Nand address not found\n"); 756 goto err; 757 } 758 759 rknand->regs = (void *)regs; 760 761 spin_lock_init(&rknand->controller.lock); 762 init_waitqueue_head(&rknand->controller.wq); 763 764 rockchip_nand_init(rknand); 765 766 ret = rockchip_nand_chips_init(node, rknand); 767 if (ret) { 768 debug("Failed to init nand chips\n"); 769 goto err; 770 } 771 772 return; 773 err: 774 kfree(rknand); 775 } 776 777 #endif 778 779 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) 780 { 781 struct mtd_info *mtd; 782 size_t length = size; 783 784 mtd = get_nand_dev_by_index(0); 785 return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst); 786 } 787 788 void nand_deselect(void) {} 789