1 /* 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <fdt_support.h> 11 #include <inttypes.h> 12 #include <nand.h> 13 #include <linux/kernel.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/nand.h> 16 #include <linux/mtd/partitions.h> 17 #include <linux/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #define NANDC_V6_BOOTROM_ECC 24 22 #define NANDC_V6_NUM_BANKS 4 23 #define NANDC_V6_DEF_TIMEOUT 20000 24 #define NANDC_V6_READ 0 25 #define NANDC_V6_WRITE 1 26 27 #define NANDC_REG_V6_FMCTL 0x00 28 #define NANDC_REG_V6_FMWAIT 0x04 29 #define NANDC_REG_V6_FLCTL 0x08 30 #define NANDC_REG_V6_BCHCTL 0x0c 31 #define NANDC_REG_V6_DMA_CFG 0x10 32 #define NANDC_REG_V6_DMA_BUF0 0x14 33 #define NANDC_REG_V6_DMA_BUF1 0x18 34 #define NANDC_REG_V6_DMA_ST 0x1C 35 #define NANDC_REG_V6_BCHST 0x20 36 #define NANDC_REG_V6_RANDMZ 0x150 37 #define NANDC_REG_V6_VER 0x160 38 #define NANDC_REG_V6_INTEN 0x16C 39 #define NANDC_REG_V6_INTCLR 0x170 40 #define NANDC_REG_V6_INTST 0x174 41 #define NANDC_REG_V6_SPARE0 0x200 42 #define NANDC_REG_V6_SPARE1 0x230 43 #define NANDC_REG_V6_BANK0 0x800 44 #define NANDC_REG_V6_SRAM0 0x1000 45 #define NANDC_REG_V6_SRAM_SIZE 0x400 46 47 #define NANDC_REG_V6_DATA 0x00 48 #define NANDC_REG_V6_ADDR 0x04 49 #define NANDC_REG_V6_CMD 0x08 50 51 /* FMCTL */ 52 #define NANDC_V6_FM_WP BIT(8) 53 #define NANDC_V6_FM_CE_SEL_M 0xFF 54 #define NANDC_V6_FM_CE_SEL(x) (1 << (x)) 55 #define NANDC_V6_FM_FREADY BIT(9) 56 57 /* FLCTL */ 58 #define NANDC_V6_FL_RST BIT(0) 59 #define NANDC_V6_FL_DIR_S 0x1 60 #define NANDC_V6_FL_XFER_START BIT(2) 61 #define NANDC_V6_FL_XFER_EN BIT(3) 62 #define NANDC_V6_FL_ST_BUF_S 0x4 63 #define NANDC_V6_FL_XFER_COUNT BIT(5) 64 #define NANDC_V6_FL_ACORRECT BIT(10) 65 #define NANDC_V6_FL_XFER_READY BIT(20) 66 67 /* BCHCTL */ 68 #define NAND_V6_BCH_REGION_S 0x5 69 #define NAND_V6_BCH_REGION_M 0x7 70 71 /* BCHST */ 72 #define NANDC_V6_BCH0_ST_ERR BIT(2) 73 #define NANDC_V6_BCH1_ST_ERR BIT(15) 74 #define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \ 75 | ((x & (1 << 27)) >> 22)) & 0x3F) 76 #define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \ 77 | ((x & (1 << 29)) >> 24)) & 0x3F) 78 79 struct rk_nand { 80 void __iomem *regs; 81 u8 chipnr; 82 u8 id[5]; 83 u8 *databuf; 84 struct udevice *dev; 85 struct mtd_info *mtd; 86 }; 87 88 static struct rk_nand *g_rk_nand; 89 static u32 nand_page_size; 90 static u32 nand_page_num; 91 static u32 nand_block_num; 92 93 static void nandc_init(struct rk_nand *rknand) 94 { 95 writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT); 96 } 97 98 static void rockchip_nand_wait_dev_ready(void __iomem *regs) 99 { 100 u32 reg; 101 u32 timeout = NANDC_V6_DEF_TIMEOUT; 102 103 while (timeout--) { 104 udelay(1); 105 reg = readl(regs + NANDC_REG_V6_FMCTL); 106 107 if ((reg & NANDC_V6_FM_FREADY)) 108 break; 109 } 110 } 111 112 static void rockchip_nand_select_chip(void __iomem *regs, int chipnr) 113 { 114 u32 reg; 115 116 reg = readl(regs + NANDC_REG_V6_FMCTL); 117 reg &= ~NANDC_V6_FM_CE_SEL_M; 118 if (chipnr != -1) 119 reg |= 1 << chipnr; 120 writel(reg, regs + NANDC_REG_V6_FMCTL); 121 } 122 123 static void rockchip_nand_read_page(void __iomem *regs, 124 int page, int col) 125 { 126 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0; 127 128 writeb(0x00, bank_base + NANDC_REG_V6_CMD); 129 writeb(col, bank_base + NANDC_REG_V6_ADDR); 130 writeb(col >> 8, bank_base + NANDC_REG_V6_ADDR); 131 writeb(page, bank_base + NANDC_REG_V6_ADDR); 132 writeb(page >> 8, bank_base + NANDC_REG_V6_ADDR); 133 writeb(page >> 16, bank_base + NANDC_REG_V6_ADDR); 134 writeb(0x30, bank_base + NANDC_REG_V6_CMD); 135 } 136 137 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, 138 u8 dir, 139 u8 st_buf) 140 { 141 u32 reg; 142 143 reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL); 144 reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S))); 145 writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); 146 147 reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) | 148 NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT | 149 NANDC_V6_FL_ACORRECT; 150 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 151 152 reg |= NANDC_V6_FL_XFER_START; 153 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 154 } 155 156 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) 157 { 158 int timeout = NANDC_V6_DEF_TIMEOUT; 159 int reg; 160 161 while (timeout--) { 162 reg = readl(rknand->regs + NANDC_REG_V6_FLCTL); 163 164 if ((reg & NANDC_V6_FL_XFER_READY) != 0) 165 break; 166 167 udelay(1); 168 } 169 170 if (timeout == 0) 171 return -1; 172 173 return 0; 174 } 175 176 static int nandc_read_page(unsigned int page, uint8_t *buf) 177 { 178 void __iomem *sram_base = g_rk_nand->regs + NANDC_REG_V6_SRAM0; 179 unsigned int max_bitflips = 0; 180 int ret, step, bch_st, ecc_step; 181 182 ecc_step = nand_page_size / 1024; 183 rockchip_nand_select_chip(g_rk_nand->regs, 0); 184 rockchip_nand_read_page(g_rk_nand->regs, page, 0); 185 rockchip_nand_wait_dev_ready(g_rk_nand->regs); 186 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 0); 187 188 for (step = 0; step < ecc_step; step++) { 189 int data_off = step * 1024; 190 u8 *data = buf + data_off; 191 192 ret = rockchip_nand_wait_pio_xfer_done(g_rk_nand); 193 if (ret) 194 return ret; 195 196 bch_st = readl(g_rk_nand->regs + NANDC_REG_V6_BCHST); 197 198 if (bch_st & NANDC_V6_BCH0_ST_ERR) { 199 max_bitflips = -1; 200 } else { 201 ret = NANDC_V6_ECC_ERR_CNT0(bch_st); 202 max_bitflips = max_t(unsigned int, max_bitflips, ret); 203 } 204 205 if ((step + 1) < ecc_step) 206 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 207 (step + 1) & 0x1); 208 209 memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE * 210 (step & 1), 1024); 211 } 212 rockchip_nand_select_chip(g_rk_nand->regs, -1); 213 214 return max_bitflips; 215 } 216 217 static int is_badblock(unsigned int page) 218 { 219 int res = 0, i; 220 u16 bad = 0xff; 221 void __iomem *regs = g_rk_nand->regs; 222 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0; 223 224 if (nandc_read_page(page, g_rk_nand->databuf) == -1) { 225 rockchip_nand_select_chip(regs, 0); 226 rockchip_nand_read_page(regs, page, nand_page_size); 227 rockchip_nand_wait_dev_ready(regs); 228 for (i = 0; i < 8; i++) { 229 bad = readb(bank_base); 230 if (bad) 231 break; 232 } 233 if (i >= 8) 234 res = 1; 235 rockchip_nand_select_chip(regs, 0); 236 } 237 if (res) 238 printf("%s 0x%x %x %x\n", __func__, page, res, bad); 239 return res; 240 } 241 242 static void read_flash_id(struct rk_nand *rknand, uint8_t *id) 243 { 244 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0; 245 246 rockchip_nand_wait_dev_ready(g_rk_nand->regs); 247 writeb(0x90, bank_base + NANDC_REG_V6_CMD); 248 writeb(0x00, bank_base + NANDC_REG_V6_ADDR); 249 udelay(1); 250 id[0] = readb(bank_base); 251 id[1] = readb(bank_base); 252 id[2] = readb(bank_base); 253 id[3] = readb(bank_base); 254 id[4] = readb(bank_base); 255 rockchip_nand_select_chip(rknand->regs, -1); 256 if (id[0] != 0xFF && id[0] != 0x00) 257 printf("NAND:%x %x\n", id[0], id[1]); 258 } 259 260 #ifdef CONFIG_NAND_ROCKCHIP_DT 261 static const struct udevice_id rockchip_nandc_ids[] = { 262 { .compatible = "rockchip,rk-nandc" }, 263 { } 264 }; 265 266 static int spl_nand_block_isbad(struct mtd_info *mtd, loff_t ofs) 267 { 268 return is_badblock((u32)ofs / nand_page_size); 269 } 270 271 static int spl_nand_read_page(struct mtd_info *mtd, loff_t from, size_t len, 272 size_t *retlen, u_char *buf) 273 { 274 int read_size, offset, read_len; 275 unsigned int page; 276 unsigned int max_pages = nand_page_num * nand_block_num; 277 278 /* Convert to page number */ 279 page = (u32)from / nand_page_size; 280 offset = from & (nand_page_size - 1); 281 read_len = len; 282 *retlen = 0; 283 284 while (read_len) { 285 read_size = nand_page_size - offset; 286 if (read_size > read_len) 287 read_size = read_len; 288 if (offset || read_size < nand_page_size) { 289 if (nandc_read_page(page, g_rk_nand->databuf) < 0) 290 return -EIO; 291 memcpy(buf, g_rk_nand->databuf + offset, read_size); 292 offset = 0; 293 } else { 294 if (nandc_read_page(page, buf) < 0) 295 return -EIO; 296 } 297 page++; 298 read_len -= read_size; 299 buf += read_size; 300 if (page >= max_pages) 301 return -EIO; 302 } 303 304 *retlen = len; 305 306 return 0; 307 } 308 309 static int rockchip_nandc_probe(struct udevice *dev) 310 { 311 const void *blob = gd->fdt_blob; 312 struct rk_nand *rknand = dev_get_priv(dev); 313 struct mtd_info *mtd = dev_get_uclass_priv(dev); 314 fdt_addr_t regs; 315 int ret = -ENODEV; 316 int node; 317 u8 *id; 318 319 g_rk_nand = rknand; 320 rknand->dev = dev; 321 322 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 323 324 if (node < 0) { 325 printf("Nand node not found\n"); 326 return -ENODEV; 327 } 328 329 if (!fdtdec_get_is_enabled(blob, node)) { 330 debug("Nand disabled in device tree\n"); 331 return -ENODEV; 332 } 333 334 regs = fdt_get_base_address(blob, node); 335 if (!regs) { 336 debug("Nand address not found\n"); 337 return -ENODEV; 338 } 339 340 rknand->regs = (void *)regs; 341 342 nandc_init(g_rk_nand); 343 read_flash_id(g_rk_nand, g_rk_nand->id); 344 345 id = g_rk_nand->id; 346 if (id[0] == id[1]) 347 return -ENODEV; 348 349 if (id[1] == 0xA1 || id[1] == 0xF1 || 350 id[1] == 0xD1 || id[1] == 0xAA || 351 id[1] == 0xDA || id[1] == 0xAC || 352 id[1] == 0xDC || id[1] == 0xA3 || 353 id[1] == 0xD3 || id[1] == 0x95 || 354 id[1] == 0x48 || id[1] == 0x63) { 355 nand_page_size = 2048; 356 nand_page_num = 64; 357 nand_block_num = 1024; 358 if (id[1] == 0xDC || id[1] == 0xAC) { 359 if ((id[0] == 0x2C && id[3] == 0xA6) || 360 (id[0] == 0xC2 && id[3] == 0xA2) || 361 (id[0] == 0x98 && id[3] == 0x26) || 362 (id[0] == 0xCD && id[3] == 0xA2)) { 363 nand_page_size = 4096; 364 nand_block_num = 2048; 365 } else { 366 nand_block_num = 4096; 367 } 368 } else if (id[1] == 0xDA) { 369 nand_block_num = 2048; 370 } else if (id[1] == 0x48) { 371 nand_page_size = 4096; 372 nand_page_num = 128; 373 nand_block_num = 4096; 374 } else if (id[1] == 0xD3) { 375 if ((id[2] == 0xD1 && id[4] == 0x5a) || /* S34ML08G2 */ 376 (id[3] == 0x05 && id[4] == 0x04)) { /* S34ML08G3 */ 377 nand_block_num = 8192; 378 } else { 379 nand_page_size = 4096; 380 nand_block_num = 4096; 381 } 382 } else if (id[1] == 0x63 && id[3] == 0x19) { /* IS34ML08G088 */ 383 nand_page_size = 4096; 384 nand_page_num = 64; 385 nand_block_num = 4096; 386 } 387 g_rk_nand->chipnr = 1; 388 g_rk_nand->databuf = kzalloc(nand_page_size, GFP_KERNEL); 389 if (!g_rk_nand) 390 return -ENOMEM; 391 mtd->_block_isbad = spl_nand_block_isbad; 392 mtd->_read = spl_nand_read_page; 393 mtd->size = (size_t)nand_page_size * nand_page_num * 394 nand_block_num; 395 mtd->writesize = nand_page_size; 396 mtd->erasesize = nand_page_size * nand_page_num; 397 mtd->erasesize_shift = ffs(mtd->erasesize) - 1; 398 mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1; 399 mtd->type = MTD_NANDFLASH; 400 mtd->dev = rknand->dev; 401 mtd->priv = rknand; 402 add_mtd_device(mtd); 403 rknand->mtd = mtd; 404 ret = 0; 405 } 406 407 return ret; 408 } 409 410 static int rockchip_nandc_bind(struct udevice *udev) 411 { 412 int ret = 0; 413 414 #ifdef CONFIG_MTD_BLK 415 struct udevice *bdev; 416 417 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD, 418 BLK_MTD_NAND, 512, 0, &bdev); 419 if (ret) 420 printf("Cannot create block device\n"); 421 #endif 422 return ret; 423 } 424 425 U_BOOT_DRIVER(rk_nandc_v6) = { 426 .name = "rk_nandc_v6", 427 .id = UCLASS_MTD, 428 .of_match = rockchip_nandc_ids, 429 .bind = rockchip_nandc_bind, 430 .probe = rockchip_nandc_probe, 431 .priv_auto_alloc_size = sizeof(struct rk_nand), 432 }; 433 434 void board_nand_init(void) 435 { 436 struct udevice *dev; 437 int ret; 438 439 ret = uclass_get_device_by_driver(UCLASS_MTD, 440 DM_GET_DRIVER(rk_nandc_v6), 441 &dev); 442 if (ret && ret != -ENODEV) 443 pr_err("Failed to initialize NAND controller. (error %d)\n", 444 ret); 445 } 446 447 int nand_spl_load_image(u32 offs, u32 size, void *buf) 448 { 449 return -EIO; 450 } 451 452 void nand_init(void){}; 453 454 int rk_nand_init(void) 455 { 456 return -ENODEV; 457 } 458 459 #else 460 void board_nand_init(void) 461 { 462 const void *blob = gd->fdt_blob; 463 static int initialized; 464 fdt_addr_t regs; 465 int node; 466 467 if (initialized) 468 return; 469 470 initialized = 1; 471 nand_page_size = CONFIG_SYS_NAND_PAGE_SIZE; 472 nand_page_num = CONFIG_SYS_NAND_PAGE_COUNT; 473 474 if (g_rk_nand) 475 return; 476 477 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 478 479 if (node < 0) { 480 printf("Nand node not found\n"); 481 return; 482 } 483 484 if (!fdtdec_get_is_enabled(blob, node)) { 485 debug("Nand disabled in device tree\n"); 486 return; 487 } 488 489 regs = fdt_get_base_address(blob, node); 490 if (!regs) { 491 debug("Nand address not found\n"); 492 return; 493 } 494 495 g_rk_nand = kzalloc(sizeof(*g_rk_nand), GFP_KERNEL); 496 g_rk_nand->regs = (void *)regs; 497 g_rk_nand->databuf = kzalloc(nand_page_size, GFP_KERNEL); 498 nandc_init(g_rk_nand); 499 read_flash_id(g_rk_nand, g_rk_nand->id); 500 501 if (g_rk_nand->id[0] == g_rk_nand->id[1]) 502 goto err; 503 504 if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 || 505 g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA || 506 g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC || 507 g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 || 508 g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 || 509 g_rk_nand->id[1] == 0x48) { 510 g_rk_nand->chipnr = 1; 511 return; 512 } 513 514 err: 515 kfree(g_rk_nand->databuf); 516 kfree(g_rk_nand); 517 g_rk_nand = NULL; 518 } 519 520 int nand_spl_load_image(u32 offs, u32 size, void *buf) 521 { 522 int i; 523 unsigned int page; 524 int force_bad_block_check = 1; 525 unsigned int maxpages = CONFIG_SYS_NAND_SIZE / 526 nand_page_size; 527 528 /* Convert to page number */ 529 page = offs / nand_page_size; 530 i = 0; 531 532 size = roundup(size, nand_page_size); 533 while (i < size / nand_page_size) { 534 /* 535 * Check if we have crossed a block boundary, and if so 536 * check for bad block. 537 */ 538 if (force_bad_block_check || !(page % nand_page_num)) { 539 /* 540 * Yes, new block. See if this block is good. If not, 541 * loop until we find a good block. 542 */ 543 while (is_badblock(page)) { 544 page = page + nand_page_num; 545 /* Check i we've reached the end of flash. */ 546 if (page >= maxpages) 547 return -EIO; 548 } 549 } 550 551 force_bad_block_check = 0; 552 553 if (nandc_read_page(page, buf) < 0) 554 return -EIO; 555 556 page++; 557 i++; 558 buf = buf + nand_page_size; 559 } 560 return 0; 561 } 562 563 void nand_init(void) 564 { 565 board_nand_init(); 566 } 567 568 int rk_nand_init(void) 569 { 570 board_nand_init(); 571 if (g_rk_nand && g_rk_nand->chipnr) 572 return 0; 573 else 574 return -ENODEV; 575 } 576 #endif 577 578 void nand_deselect(void) {} 579 580