1 /* 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <inttypes.h> 10 #include <nand.h> 11 #include <linux/kernel.h> 12 #include <linux/mtd/mtd.h> 13 #include <linux/mtd/nand.h> 14 #include <linux/mtd/partitions.h> 15 #include <linux/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define NANDC_V6_BOOTROM_ECC 24 20 #define NANDC_V6_NUM_BANKS 4 21 #define NANDC_V6_DEF_TIMEOUT 20000 22 #define NANDC_V6_READ 0 23 #define NANDC_V6_WRITE 1 24 25 #define NANDC_REG_V6_FMCTL 0x00 26 #define NANDC_REG_V6_FMWAIT 0x04 27 #define NANDC_REG_V6_FLCTL 0x08 28 #define NANDC_REG_V6_BCHCTL 0x0c 29 #define NANDC_REG_V6_DMA_CFG 0x10 30 #define NANDC_REG_V6_DMA_BUF0 0x14 31 #define NANDC_REG_V6_DMA_BUF1 0x18 32 #define NANDC_REG_V6_DMA_ST 0x1C 33 #define NANDC_REG_V6_BCHST 0x20 34 #define NANDC_REG_V6_RANDMZ 0x150 35 #define NANDC_REG_V6_VER 0x160 36 #define NANDC_REG_V6_INTEN 0x16C 37 #define NANDC_REG_V6_INTCLR 0x170 38 #define NANDC_REG_V6_INTST 0x174 39 #define NANDC_REG_V6_SPARE0 0x200 40 #define NANDC_REG_V6_SPARE1 0x230 41 #define NANDC_REG_V6_BANK0 0x800 42 #define NANDC_REG_V6_SRAM0 0x1000 43 #define NANDC_REG_V6_SRAM_SIZE 0x400 44 45 #define NANDC_REG_V6_DATA 0x00 46 #define NANDC_REG_V6_ADDR 0x04 47 #define NANDC_REG_V6_CMD 0x08 48 49 /* FMCTL */ 50 #define NANDC_V6_FM_WP BIT(8) 51 #define NANDC_V6_FM_CE_SEL_M 0xFF 52 #define NANDC_V6_FM_CE_SEL(x) (1 << (x)) 53 #define NANDC_V6_FM_FREADY BIT(9) 54 55 /* FLCTL */ 56 #define NANDC_V6_FL_RST BIT(0) 57 #define NANDC_V6_FL_DIR_S 0x1 58 #define NANDC_V6_FL_XFER_START BIT(2) 59 #define NANDC_V6_FL_XFER_EN BIT(3) 60 #define NANDC_V6_FL_ST_BUF_S 0x4 61 #define NANDC_V6_FL_XFER_COUNT BIT(5) 62 #define NANDC_V6_FL_ACORRECT BIT(10) 63 #define NANDC_V6_FL_XFER_READY BIT(20) 64 65 /* BCHCTL */ 66 #define NAND_V6_BCH_REGION_S 0x5 67 #define NAND_V6_BCH_REGION_M 0x7 68 69 /* BCHST */ 70 #define NANDC_V6_BCH0_ST_ERR BIT(2) 71 #define NANDC_V6_BCH1_ST_ERR BIT(15) 72 #define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \ 73 | ((x & (1 << 27)) >> 22)) & 0x3F) 74 #define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \ 75 | ((x & (1 << 29)) >> 24)) & 0x3F) 76 77 struct rk_nand { 78 void __iomem *regs; 79 u8 chipnr; 80 u8 id[5]; 81 u8 *databuf; 82 }; 83 84 struct rk_nand *g_rk_nand; 85 86 static void nandc_init(struct rk_nand *rknand) 87 { 88 writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT); 89 } 90 91 static void rockchip_nand_wait_dev_ready(void __iomem *regs) 92 { 93 u32 reg; 94 u32 timeout = NANDC_V6_DEF_TIMEOUT; 95 96 while (timeout--) { 97 udelay(1); 98 reg = readl(regs + NANDC_REG_V6_FMCTL); 99 100 if ((reg & NANDC_V6_FM_FREADY)) 101 break; 102 } 103 } 104 105 static void rockchip_nand_select_chip(void __iomem *regs, int chipnr) 106 { 107 u32 reg; 108 109 reg = readl(regs + NANDC_REG_V6_FMCTL); 110 reg &= ~NANDC_V6_FM_CE_SEL_M; 111 if (chipnr != -1) 112 reg |= 1 << chipnr; 113 writel(reg, regs + NANDC_REG_V6_FMCTL); 114 } 115 116 static void rockchip_nand_read_page(void __iomem *regs, 117 int page, int col) 118 { 119 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0; 120 121 writeb(0x00, bank_base + NANDC_REG_V6_CMD); 122 writeb(col, bank_base + NANDC_REG_V6_ADDR); 123 writeb(col >> 8, bank_base + NANDC_REG_V6_ADDR); 124 writeb(page, bank_base + NANDC_REG_V6_ADDR); 125 writeb(page >> 8, bank_base + NANDC_REG_V6_ADDR); 126 writeb(page >> 16, bank_base + NANDC_REG_V6_ADDR); 127 writeb(0x30, bank_base + NANDC_REG_V6_CMD); 128 } 129 130 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, 131 u8 dir, 132 u8 st_buf) 133 { 134 u32 reg; 135 136 reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL); 137 reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S))); 138 writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); 139 140 reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) | 141 NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT | 142 NANDC_V6_FL_ACORRECT; 143 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 144 145 reg |= NANDC_V6_FL_XFER_START; 146 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 147 } 148 149 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) 150 { 151 int timeout = NANDC_V6_DEF_TIMEOUT; 152 int reg; 153 154 while (timeout--) { 155 reg = readl(rknand->regs + NANDC_REG_V6_FLCTL); 156 157 if ((reg & NANDC_V6_FL_XFER_READY) != 0) 158 break; 159 160 udelay(1); 161 } 162 163 if (timeout == 0) 164 return -1; 165 166 return 0; 167 } 168 169 static int nandc_read_page(unsigned int page, uint8_t *buf) 170 { 171 void __iomem *sram_base = g_rk_nand->regs + NANDC_REG_V6_SRAM0; 172 unsigned int max_bitflips = 0; 173 int ret, step, bch_st, ecc_step; 174 175 ecc_step = CONFIG_SYS_NAND_PAGE_SIZE / 1024; 176 rockchip_nand_select_chip(g_rk_nand->regs, 0); 177 rockchip_nand_read_page(g_rk_nand->regs, page, 0); 178 rockchip_nand_wait_dev_ready(g_rk_nand->regs); 179 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 0); 180 181 for (step = 0; step < ecc_step; step++) { 182 int data_off = step * 1024; 183 u8 *data = buf + data_off; 184 185 ret = rockchip_nand_wait_pio_xfer_done(g_rk_nand); 186 if (ret) 187 return ret; 188 189 bch_st = readl(g_rk_nand->regs + NANDC_REG_V6_BCHST); 190 191 if (bch_st & NANDC_V6_BCH0_ST_ERR) { 192 max_bitflips = -1; 193 } else { 194 ret = NANDC_V6_ECC_ERR_CNT0(bch_st); 195 max_bitflips = max_t(unsigned int, max_bitflips, ret); 196 } 197 198 if ((step + 1) < ecc_step) 199 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 200 (step + 1) & 0x1); 201 202 memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE * 203 (step & 1), 1024); 204 } 205 rockchip_nand_select_chip(g_rk_nand->regs, -1); 206 207 return max_bitflips; 208 } 209 210 static int is_badblock(unsigned int page) 211 { 212 int res = 0, i; 213 u16 bad = 0xff; 214 void __iomem *regs = g_rk_nand->regs; 215 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0; 216 217 if (nandc_read_page(page, g_rk_nand->databuf) == -1) { 218 rockchip_nand_select_chip(regs, 0); 219 rockchip_nand_read_page(regs, page, 220 CONFIG_SYS_NAND_PAGE_SIZE); 221 rockchip_nand_wait_dev_ready(regs); 222 for (i = 0; i < 8; i++) { 223 bad = readb(bank_base); 224 if (bad) 225 break; 226 } 227 if (i >= 8) 228 res = 1; 229 rockchip_nand_select_chip(regs, 0); 230 } 231 if (res) 232 printf("%s 0x%x %x %x\n", __func__, page, res, bad); 233 return res; 234 } 235 236 static void read_flash_id(struct rk_nand *rknand, uint8_t *id) 237 { 238 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0; 239 240 rockchip_nand_wait_dev_ready(g_rk_nand->regs); 241 writeb(0x90, bank_base + NANDC_REG_V6_CMD); 242 writeb(0x00, bank_base + NANDC_REG_V6_ADDR); 243 udelay(1); 244 id[0] = readb(bank_base); 245 id[1] = readb(bank_base); 246 id[2] = readb(bank_base); 247 id[3] = readb(bank_base); 248 id[4] = readb(bank_base); 249 rockchip_nand_select_chip(rknand->regs, -1); 250 printf("%s %x %x %x %x %x\n", __func__, id[0], id[1], id[2], id[3], 251 id[4]); 252 } 253 254 void board_nand_init(void) 255 { 256 const void *blob = gd->fdt_blob; 257 fdt_addr_t regs; 258 int node; 259 260 if (g_rk_nand) 261 return; 262 263 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 264 265 if (node < 0) { 266 printf("Nand node not found\n"); 267 goto err; 268 } 269 270 if (!fdtdec_get_is_enabled(blob, node)) { 271 debug("Nand disabled in device tree\n"); 272 goto err; 273 } 274 275 regs = fdt_get_base_address(blob, node); 276 if (regs == FDT_ADDR_T_NONE) { 277 debug("Nand address not found\n"); 278 goto err; 279 } 280 281 g_rk_nand = kzalloc(sizeof(*g_rk_nand), GFP_KERNEL); 282 g_rk_nand->regs = (void *)regs; 283 g_rk_nand->databuf = kzalloc(CONFIG_SYS_NAND_PAGE_SIZE, GFP_KERNEL); 284 nandc_init(g_rk_nand); 285 read_flash_id(g_rk_nand, g_rk_nand->id); 286 if (g_rk_nand->id[0] != 0xFF && g_rk_nand->id[1] != 0xFF && 287 g_rk_nand->id[0] != 0x00 && g_rk_nand->id[1] != 0x00) 288 g_rk_nand->chipnr = 1; 289 return; 290 err: 291 kfree(g_rk_nand); 292 } 293 294 int nand_spl_load_image(u32 offs, u32 size, void *buf) 295 { 296 int i; 297 unsigned int page; 298 unsigned int maxpages = CONFIG_SYS_NAND_SIZE / 299 CONFIG_SYS_NAND_PAGE_SIZE; 300 301 /* Convert to page number */ 302 page = offs / CONFIG_SYS_NAND_PAGE_SIZE; 303 i = 0; 304 305 size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE); 306 while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) { 307 /* 308 * Check if we have crossed a block boundary, and if so 309 * check for bad block. 310 */ 311 if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { 312 /* 313 * Yes, new block. See if this block is good. If not, 314 * loop until we find a good block. 315 */ 316 while (is_badblock(page)) { 317 page = page + CONFIG_SYS_NAND_PAGE_COUNT; 318 /* Check i we've reached the end of flash. */ 319 if (page >= maxpages) 320 return -EIO; 321 } 322 } 323 324 if (nandc_read_page(page, buf) < 0) 325 return -EIO; 326 327 page++; 328 i++; 329 buf = buf + CONFIG_SYS_NAND_PAGE_SIZE; 330 } 331 return 0; 332 } 333 334 void nand_init(void) 335 { 336 board_nand_init(); 337 } 338 339 int rk_nand_init(void) 340 { 341 board_nand_init(); 342 if (g_rk_nand && g_rk_nand->chipnr) 343 return 0; 344 else 345 return -ENODEV; 346 } 347 348 void nand_deselect(void) {} 349