1 /* 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <fdt_support.h> 11 #include <inttypes.h> 12 #include <nand.h> 13 #include <linux/kernel.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/nand.h> 16 #include <linux/mtd/partitions.h> 17 #include <linux/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #define NANDC_V6_BOOTROM_ECC 24 22 #define NANDC_V6_NUM_BANKS 4 23 #define NANDC_V6_DEF_TIMEOUT 20000 24 #define NANDC_V6_READ 0 25 #define NANDC_V6_WRITE 1 26 27 #define NANDC_REG_V6_FMCTL 0x00 28 #define NANDC_REG_V6_FMWAIT 0x04 29 #define NANDC_REG_V6_FLCTL 0x08 30 #define NANDC_REG_V6_BCHCTL 0x0c 31 #define NANDC_REG_V6_DMA_CFG 0x10 32 #define NANDC_REG_V6_DMA_BUF0 0x14 33 #define NANDC_REG_V6_DMA_BUF1 0x18 34 #define NANDC_REG_V6_DMA_ST 0x1C 35 #define NANDC_REG_V6_BCHST 0x20 36 #define NANDC_REG_V6_RANDMZ 0x150 37 #define NANDC_REG_V6_VER 0x160 38 #define NANDC_REG_V6_INTEN 0x16C 39 #define NANDC_REG_V6_INTCLR 0x170 40 #define NANDC_REG_V6_INTST 0x174 41 #define NANDC_REG_V6_SPARE0 0x200 42 #define NANDC_REG_V6_SPARE1 0x230 43 #define NANDC_REG_V6_BANK0 0x800 44 #define NANDC_REG_V6_SRAM0 0x1000 45 #define NANDC_REG_V6_SRAM_SIZE 0x400 46 47 #define NANDC_REG_V6_DATA 0x00 48 #define NANDC_REG_V6_ADDR 0x04 49 #define NANDC_REG_V6_CMD 0x08 50 51 /* FMCTL */ 52 #define NANDC_V6_FM_WP BIT(8) 53 #define NANDC_V6_FM_CE_SEL_M 0xFF 54 #define NANDC_V6_FM_CE_SEL(x) (1 << (x)) 55 #define NANDC_V6_FM_FREADY BIT(9) 56 57 /* FLCTL */ 58 #define NANDC_V6_FL_RST BIT(0) 59 #define NANDC_V6_FL_DIR_S 0x1 60 #define NANDC_V6_FL_XFER_START BIT(2) 61 #define NANDC_V6_FL_XFER_EN BIT(3) 62 #define NANDC_V6_FL_ST_BUF_S 0x4 63 #define NANDC_V6_FL_XFER_COUNT BIT(5) 64 #define NANDC_V6_FL_ACORRECT BIT(10) 65 #define NANDC_V6_FL_XFER_READY BIT(20) 66 67 /* BCHCTL */ 68 #define NAND_V6_BCH_REGION_S 0x5 69 #define NAND_V6_BCH_REGION_M 0x7 70 71 /* BCHST */ 72 #define NANDC_V6_BCH0_ST_ERR BIT(2) 73 #define NANDC_V6_BCH1_ST_ERR BIT(15) 74 #define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \ 75 | ((x & (1 << 27)) >> 22)) & 0x3F) 76 #define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \ 77 | ((x & (1 << 29)) >> 24)) & 0x3F) 78 79 struct rk_nand { 80 void __iomem *regs; 81 u8 chipnr; 82 u8 id[5]; 83 u8 *databuf; 84 struct udevice *dev; 85 struct mtd_info *mtd; 86 }; 87 88 struct rk_nand *g_rk_nand; 89 90 static void nandc_init(struct rk_nand *rknand) 91 { 92 writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT); 93 } 94 95 static void rockchip_nand_wait_dev_ready(void __iomem *regs) 96 { 97 u32 reg; 98 u32 timeout = NANDC_V6_DEF_TIMEOUT; 99 100 while (timeout--) { 101 udelay(1); 102 reg = readl(regs + NANDC_REG_V6_FMCTL); 103 104 if ((reg & NANDC_V6_FM_FREADY)) 105 break; 106 } 107 } 108 109 static void rockchip_nand_select_chip(void __iomem *regs, int chipnr) 110 { 111 u32 reg; 112 113 reg = readl(regs + NANDC_REG_V6_FMCTL); 114 reg &= ~NANDC_V6_FM_CE_SEL_M; 115 if (chipnr != -1) 116 reg |= 1 << chipnr; 117 writel(reg, regs + NANDC_REG_V6_FMCTL); 118 } 119 120 static void rockchip_nand_read_page(void __iomem *regs, 121 int page, int col) 122 { 123 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0; 124 125 writeb(0x00, bank_base + NANDC_REG_V6_CMD); 126 writeb(col, bank_base + NANDC_REG_V6_ADDR); 127 writeb(col >> 8, bank_base + NANDC_REG_V6_ADDR); 128 writeb(page, bank_base + NANDC_REG_V6_ADDR); 129 writeb(page >> 8, bank_base + NANDC_REG_V6_ADDR); 130 writeb(page >> 16, bank_base + NANDC_REG_V6_ADDR); 131 writeb(0x30, bank_base + NANDC_REG_V6_CMD); 132 } 133 134 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, 135 u8 dir, 136 u8 st_buf) 137 { 138 u32 reg; 139 140 reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL); 141 reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S))); 142 writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); 143 144 reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) | 145 NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT | 146 NANDC_V6_FL_ACORRECT; 147 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 148 149 reg |= NANDC_V6_FL_XFER_START; 150 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 151 } 152 153 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) 154 { 155 int timeout = NANDC_V6_DEF_TIMEOUT; 156 int reg; 157 158 while (timeout--) { 159 reg = readl(rknand->regs + NANDC_REG_V6_FLCTL); 160 161 if ((reg & NANDC_V6_FL_XFER_READY) != 0) 162 break; 163 164 udelay(1); 165 } 166 167 if (timeout == 0) 168 return -1; 169 170 return 0; 171 } 172 173 static int nandc_read_page(unsigned int page, uint8_t *buf) 174 { 175 void __iomem *sram_base = g_rk_nand->regs + NANDC_REG_V6_SRAM0; 176 unsigned int max_bitflips = 0; 177 int ret, step, bch_st, ecc_step; 178 179 ecc_step = CONFIG_SYS_NAND_PAGE_SIZE / 1024; 180 rockchip_nand_select_chip(g_rk_nand->regs, 0); 181 rockchip_nand_read_page(g_rk_nand->regs, page, 0); 182 rockchip_nand_wait_dev_ready(g_rk_nand->regs); 183 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 0); 184 185 for (step = 0; step < ecc_step; step++) { 186 int data_off = step * 1024; 187 u8 *data = buf + data_off; 188 189 ret = rockchip_nand_wait_pio_xfer_done(g_rk_nand); 190 if (ret) 191 return ret; 192 193 bch_st = readl(g_rk_nand->regs + NANDC_REG_V6_BCHST); 194 195 if (bch_st & NANDC_V6_BCH0_ST_ERR) { 196 max_bitflips = -1; 197 } else { 198 ret = NANDC_V6_ECC_ERR_CNT0(bch_st); 199 max_bitflips = max_t(unsigned int, max_bitflips, ret); 200 } 201 202 if ((step + 1) < ecc_step) 203 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V6_READ, 204 (step + 1) & 0x1); 205 206 memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE * 207 (step & 1), 1024); 208 } 209 rockchip_nand_select_chip(g_rk_nand->regs, -1); 210 211 return max_bitflips; 212 } 213 214 static int is_badblock(unsigned int page) 215 { 216 int res = 0, i; 217 u16 bad = 0xff; 218 void __iomem *regs = g_rk_nand->regs; 219 void __iomem *bank_base = regs + NANDC_REG_V6_BANK0; 220 221 if (nandc_read_page(page, g_rk_nand->databuf) == -1) { 222 rockchip_nand_select_chip(regs, 0); 223 rockchip_nand_read_page(regs, page, 224 CONFIG_SYS_NAND_PAGE_SIZE); 225 rockchip_nand_wait_dev_ready(regs); 226 for (i = 0; i < 8; i++) { 227 bad = readb(bank_base); 228 if (bad) 229 break; 230 } 231 if (i >= 8) 232 res = 1; 233 rockchip_nand_select_chip(regs, 0); 234 } 235 if (res) 236 printf("%s 0x%x %x %x\n", __func__, page, res, bad); 237 return res; 238 } 239 240 static void read_flash_id(struct rk_nand *rknand, uint8_t *id) 241 { 242 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0; 243 244 rockchip_nand_wait_dev_ready(g_rk_nand->regs); 245 writeb(0x90, bank_base + NANDC_REG_V6_CMD); 246 writeb(0x00, bank_base + NANDC_REG_V6_ADDR); 247 udelay(1); 248 id[0] = readb(bank_base); 249 id[1] = readb(bank_base); 250 id[2] = readb(bank_base); 251 id[3] = readb(bank_base); 252 id[4] = readb(bank_base); 253 rockchip_nand_select_chip(rknand->regs, -1); 254 if (id[0] != 0xFF && id[0] != 0x00) 255 printf("NAND:%x %x\n", id[0], id[1]); 256 } 257 258 #ifdef CONFIG_NAND_ROCKCHIP_DT 259 static const struct udevice_id rockchip_nandc_ids[] = { 260 { .compatible = "rockchip,rk-nandc" }, 261 { } 262 }; 263 264 static int spl_nand_block_isbad(struct mtd_info *mtd, loff_t ofs) 265 { 266 return is_badblock(ofs / CONFIG_SYS_NAND_PAGE_SIZE); 267 } 268 269 static int spl_nand_read_page(struct mtd_info *mtd, loff_t from, size_t len, 270 size_t *retlen, u_char *buf) 271 { 272 int read_size, offset, read_len; 273 unsigned int page; 274 unsigned int max_pages = CONFIG_SYS_NAND_SIZE / 275 CONFIG_SYS_NAND_PAGE_SIZE; 276 277 /* Convert to page number */ 278 page = from / CONFIG_SYS_NAND_PAGE_SIZE; 279 offset = from & (CONFIG_SYS_NAND_PAGE_SIZE - 1); 280 read_len = len; 281 *retlen = 0; 282 283 while (read_len) { 284 read_size = CONFIG_SYS_NAND_PAGE_SIZE - offset; 285 if (read_size > read_len) 286 read_size = read_len; 287 if (offset || read_size < CONFIG_SYS_NAND_PAGE_SIZE) { 288 if (nandc_read_page(page, g_rk_nand->databuf) < 0) 289 return -EIO; 290 memcpy(buf, g_rk_nand->databuf + offset, read_size); 291 offset = 0; 292 } else { 293 if (nandc_read_page(page, buf) < 0) 294 return -EIO; 295 } 296 page++; 297 read_len -= read_size; 298 buf += read_size; 299 if (page >= max_pages) 300 return -EIO; 301 } 302 303 *retlen = len; 304 305 return 0; 306 } 307 308 static int rockchip_nandc_probe(struct udevice *dev) 309 { 310 const void *blob = gd->fdt_blob; 311 struct rk_nand *rknand = dev_get_priv(dev); 312 struct mtd_info *mtd = dev_get_uclass_priv(dev); 313 fdt_addr_t regs; 314 int ret = -ENODEV; 315 int node; 316 317 g_rk_nand = rknand; 318 rknand->dev = dev; 319 320 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 321 322 if (node < 0) { 323 printf("Nand node not found\n"); 324 return -ENODEV; 325 } 326 327 if (!fdtdec_get_is_enabled(blob, node)) { 328 debug("Nand disabled in device tree\n"); 329 return -ENODEV; 330 } 331 332 regs = fdt_get_base_address(blob, node); 333 if (!regs) { 334 debug("Nand address not found\n"); 335 return -ENODEV; 336 } 337 338 rknand->regs = (void *)regs; 339 340 nandc_init(g_rk_nand); 341 read_flash_id(g_rk_nand, g_rk_nand->id); 342 343 if (g_rk_nand->id[0] == g_rk_nand->id[1]) 344 return -ENODEV; 345 346 if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 || 347 g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA || 348 g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC || 349 g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 || 350 g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 || 351 g_rk_nand->id[1] == 0x48) { 352 g_rk_nand->chipnr = 1; 353 g_rk_nand->databuf = kzalloc(CONFIG_SYS_NAND_PAGE_SIZE, 354 GFP_KERNEL); 355 if (!g_rk_nand) 356 return -ENOMEM; 357 mtd->_block_isbad = spl_nand_block_isbad; 358 mtd->_read = spl_nand_read_page; 359 mtd->size = CONFIG_SYS_NAND_SIZE; 360 mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; 361 mtd->type = MTD_NANDFLASH; 362 mtd->dev = rknand->dev; 363 mtd->priv = rknand; 364 add_mtd_device(mtd); 365 mtd->name = "rk-nand"; 366 rknand->mtd = mtd; 367 ret = 0; 368 } 369 370 return ret; 371 } 372 373 static int rockchip_nandc_bind(struct udevice *udev) 374 { 375 int ret = 0; 376 377 #ifdef CONFIG_MTD_BLK 378 struct udevice *bdev; 379 380 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD, 381 BLK_MTD_NAND, 512, 0, &bdev); 382 if (ret) 383 printf("Cannot create block device\n"); 384 #endif 385 return ret; 386 } 387 388 U_BOOT_DRIVER(rk_nandc_v6) = { 389 .name = "rk_nandc_v6", 390 .id = UCLASS_MTD, 391 .of_match = rockchip_nandc_ids, 392 .bind = rockchip_nandc_bind, 393 .probe = rockchip_nandc_probe, 394 .priv_auto_alloc_size = sizeof(struct rk_nand), 395 }; 396 397 void board_nand_init(void) 398 { 399 struct udevice *dev; 400 int ret; 401 402 ret = uclass_get_device_by_driver(UCLASS_MTD, 403 DM_GET_DRIVER(rk_nandc_v6), 404 &dev); 405 if (ret && ret != -ENODEV) 406 pr_err("Failed to initialize NAND controller. (error %d)\n", 407 ret); 408 } 409 410 int nand_spl_load_image(u32 offs, u32 size, void *buf) 411 { 412 return -EIO; 413 } 414 415 void nand_init(void){}; 416 417 int rk_nand_init(void) 418 { 419 return -ENODEV; 420 } 421 422 #else 423 void board_nand_init(void) 424 { 425 const void *blob = gd->fdt_blob; 426 static int initialized; 427 fdt_addr_t regs; 428 int node; 429 430 if (initialized) 431 return; 432 433 initialized = 1; 434 435 if (g_rk_nand) 436 return; 437 438 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 439 440 if (node < 0) { 441 printf("Nand node not found\n"); 442 return; 443 } 444 445 if (!fdtdec_get_is_enabled(blob, node)) { 446 debug("Nand disabled in device tree\n"); 447 return; 448 } 449 450 regs = fdt_get_base_address(blob, node); 451 if (!regs) { 452 debug("Nand address not found\n"); 453 return; 454 } 455 456 g_rk_nand = kzalloc(sizeof(*g_rk_nand), GFP_KERNEL); 457 g_rk_nand->regs = (void *)regs; 458 g_rk_nand->databuf = kzalloc(CONFIG_SYS_NAND_PAGE_SIZE, GFP_KERNEL); 459 nandc_init(g_rk_nand); 460 read_flash_id(g_rk_nand, g_rk_nand->id); 461 462 if (g_rk_nand->id[0] == g_rk_nand->id[1]) 463 goto err; 464 465 if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 || 466 g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA || 467 g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC || 468 g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 || 469 g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 || 470 g_rk_nand->id[1] == 0x48) { 471 g_rk_nand->chipnr = 1; 472 return; 473 } 474 475 err: 476 kfree(g_rk_nand->databuf); 477 kfree(g_rk_nand); 478 g_rk_nand = NULL; 479 } 480 481 int nand_spl_load_image(u32 offs, u32 size, void *buf) 482 { 483 int i; 484 unsigned int page; 485 unsigned int maxpages = CONFIG_SYS_NAND_SIZE / 486 CONFIG_SYS_NAND_PAGE_SIZE; 487 488 /* Convert to page number */ 489 page = offs / CONFIG_SYS_NAND_PAGE_SIZE; 490 i = 0; 491 492 size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE); 493 while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) { 494 /* 495 * Check if we have crossed a block boundary, and if so 496 * check for bad block. 497 */ 498 if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { 499 /* 500 * Yes, new block. See if this block is good. If not, 501 * loop until we find a good block. 502 */ 503 while (is_badblock(page)) { 504 page = page + CONFIG_SYS_NAND_PAGE_COUNT; 505 /* Check i we've reached the end of flash. */ 506 if (page >= maxpages) 507 return -EIO; 508 } 509 } 510 511 if (nandc_read_page(page, buf) < 0) 512 return -EIO; 513 514 page++; 515 i++; 516 buf = buf + CONFIG_SYS_NAND_PAGE_SIZE; 517 } 518 return 0; 519 } 520 521 void nand_init(void) 522 { 523 board_nand_init(); 524 } 525 526 int rk_nand_init(void) 527 { 528 board_nand_init(); 529 if (g_rk_nand && g_rk_nand->chipnr) 530 return 0; 531 else 532 return -ENODEV; 533 } 534 #endif 535 536 void nand_deselect(void) {} 537 538