1 /* 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com> 3 * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <inttypes.h> 12 #include <nand.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/kernel.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/rawnand.h> 18 #include <linux/mtd/partitions.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define NANDC_V6_BOOTROM_ECC 24 23 #define NANDC_V6_NUM_BANKS 8 24 #define NANDC_V6_DEF_TIMEOUT 20000 25 #define NANDC_V6_READ 0 26 #define NANDC_V6_WRITE 1 27 28 #define NANDC_REG_V6_FMCTL 0x00 29 #define NANDC_REG_V6_FMWAIT 0x04 30 #define NANDC_REG_V6_FLCTL 0x08 31 #define NANDC_REG_V6_BCHCTL 0x0c 32 #define NANDC_REG_V6_DMA_CFG 0x10 33 #define NANDC_REG_V6_DMA_BUF0 0x14 34 #define NANDC_REG_V6_DMA_BUF1 0x18 35 #define NANDC_REG_V6_DMA_ST 0x1C 36 #define NANDC_REG_V6_BCHST 0x20 37 #define NANDC_REG_V6_RANDMZ 0x150 38 #define NANDC_REG_V6_VER 0x160 39 #define NANDC_REG_V6_INTEN 0x16C 40 #define NANDC_REG_V6_INTCLR 0x170 41 #define NANDC_REG_V6_INTST 0x174 42 #define NANDC_REG_V6_SPARE0 0x200 43 #define NANDC_REG_V6_SPARE1 0x230 44 #define NANDC_REG_V6_BANK0 0x800 45 #define NANDC_REG_V6_SRAM0 0x1000 46 #define NANDC_REG_V6_SRAM_SIZE 0x400 47 48 #define NANDC_REG_V6_DATA 0x00 49 #define NANDC_REG_V6_ADDR 0x04 50 #define NANDC_REG_V6_CMD 0x08 51 52 /* FMCTL */ 53 #define NANDC_V6_FM_WP BIT(8) 54 #define NANDC_V6_FM_CE_SEL_M 0xFF 55 #define NANDC_V6_FM_CE_SEL(x) (1 << (x)) 56 #define NANDC_V6_FM_FREADY BIT(9) 57 58 /* FLCTL */ 59 #define NANDC_V6_FL_RST BIT(0) 60 #define NANDC_V6_FL_DIR_S 0x1 61 #define NANDC_V6_FL_XFER_START BIT(2) 62 #define NANDC_V6_FL_XFER_EN BIT(3) 63 #define NANDC_V6_FL_ST_BUF_S 0x4 64 #define NANDC_V6_FL_XFER_COUNT BIT(5) 65 #define NANDC_V6_FL_ACORRECT BIT(10) 66 #define NANDC_V6_FL_XFER_READY BIT(20) 67 68 /* BCHCTL */ 69 #define NAND_V6_BCH_REGION_S 0x5 70 #define NAND_V6_BCH_REGION_M 0x7 71 72 /* BCHST */ 73 #define NANDC_V6_BCH0_ST_ERR BIT(2) 74 #define NANDC_V6_BCH1_ST_ERR BIT(15) 75 #define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \ 76 | ((x & (1 << 27)) >> 22)) & 0x3F) 77 #define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \ 78 | ((x & (1 << 29)) >> 24)) & 0x3F) 79 80 struct rk_nand { 81 uint32_t banks[NANDC_V6_NUM_BANKS]; 82 struct nand_hw_control controller; 83 uint32_t ecc_strength; 84 struct mtd_info mtd; 85 bool bootromblocks; 86 void __iomem *regs; 87 int selected_bank; 88 struct udevice *dev; 89 }; 90 91 static struct nand_ecclayout nand_oob_fix = { 92 .eccbytes = 24, 93 .eccpos = { 94 4, 5, 6, 7, 8, 9, 10}, 95 .oobfree = { 96 {.offset = 0, 97 .length = 4} } 98 }; 99 100 static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl) 101 { 102 return container_of(ctrl, struct rk_nand, controller); 103 } 104 105 static void rockchip_nand_init(struct rk_nand *rknand) 106 { 107 writel(0, rknand->regs + NANDC_REG_V6_RANDMZ); 108 writel(0, rknand->regs + NANDC_REG_V6_DMA_CFG); 109 writel(0, rknand->regs + NANDC_REG_V6_BCHCTL); 110 writel(NANDC_V6_FM_WP, rknand->regs + NANDC_REG_V6_FMCTL); 111 writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT); 112 } 113 114 static void rockchip_nand_select_chip(struct mtd_info *mtd, int chipnr) 115 { 116 struct nand_chip *chip = mtd_to_nand(mtd); 117 struct rk_nand *rknand = to_rknand(chip->controller); 118 void __iomem *bank_base; 119 uint32_t reg; 120 int banknr; 121 122 reg = readl(rknand->regs + NANDC_REG_V6_FMCTL); 123 reg &= ~NANDC_V6_FM_CE_SEL_M; 124 125 if (chipnr == -1) { 126 banknr = -1; 127 } else { 128 banknr = rknand->banks[chipnr]; 129 bank_base = rknand->regs + NANDC_REG_V6_BANK0 + banknr * 0x100; 130 131 chip->IO_ADDR_R = bank_base; 132 chip->IO_ADDR_W = bank_base; 133 134 reg |= 1 << banknr; 135 } 136 writel(reg, rknand->regs + NANDC_REG_V6_FMCTL); 137 138 rknand->selected_bank = banknr; 139 } 140 141 static void rockchip_nand_cmd_ctrl(struct mtd_info *mtd, 142 int dat, 143 unsigned int ctrl) 144 { 145 struct nand_chip *chip = mtd_to_nand(mtd); 146 struct rk_nand *rknand = to_rknand(chip->controller); 147 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0 148 + rknand->selected_bank * 0x100; 149 150 if (ctrl & NAND_CTRL_CHANGE) { 151 if (ctrl & NAND_ALE) 152 bank_base += NANDC_REG_V6_ADDR; 153 else if (ctrl & NAND_CLE) 154 bank_base += NANDC_REG_V6_CMD; 155 chip->IO_ADDR_W = bank_base; 156 } 157 158 if (dat != NAND_CMD_NONE) 159 writeb(dat & 0xFF, chip->IO_ADDR_W); 160 } 161 162 static void rockchip_nand_read_buf(struct mtd_info *mtd, 163 uint8_t *buf, 164 int len) 165 { 166 struct nand_chip *chip = mtd_to_nand(mtd); 167 struct rk_nand *rknand = to_rknand(chip->controller); 168 int offs = 0; 169 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0 170 + rknand->selected_bank * 0x100; 171 172 for (offs = 0; offs < len; offs++) 173 buf[offs] = readb(bank_base); 174 } 175 176 static void rockchip_nand_write_buf(struct mtd_info *mtd, 177 const uint8_t *buf, 178 int len) 179 { 180 struct nand_chip *chip = mtd_to_nand(mtd); 181 struct rk_nand *rknand = to_rknand(chip->controller); 182 int offs = 0; 183 void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0 184 + rknand->selected_bank * 0x100; 185 186 for (offs = 0; offs < len; offs++) 187 writeb(buf[offs], bank_base); 188 } 189 190 static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) 191 { 192 uint8_t ret; 193 194 rockchip_nand_read_buf(mtd, &ret, 1); 195 196 return ret; 197 } 198 199 static int rockchip_nand_dev_ready(struct mtd_info *mtd) 200 { 201 struct nand_chip *chip = mtd_to_nand(mtd); 202 struct rk_nand *rknand = to_rknand(chip->controller); 203 204 if (readl(rknand->regs + NANDC_REG_V6_FMCTL) & NANDC_V6_FM_FREADY) 205 return 1; 206 207 return 0; 208 } 209 210 static int rockchip_nand_hw_ecc_setup(struct mtd_info *mtd, 211 struct nand_ecc_ctrl *ecc, 212 uint32_t strength) 213 { 214 struct nand_chip *chip = mtd_to_nand(mtd); 215 struct rk_nand *rknand = to_rknand(chip->controller); 216 u32 reg; 217 218 ecc->strength = strength; 219 ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8); 220 ecc->bytes = ALIGN(ecc->bytes, 2); 221 222 switch (ecc->strength) { 223 case 60: 224 reg = 0x00040010; 225 break; 226 case 40: 227 reg = 0x00040000; 228 break; 229 case 24: 230 reg = 0x00000010; 231 break; 232 case 16: 233 reg = 0x00000000; 234 break; 235 default: 236 return -EINVAL; 237 } 238 writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); 239 240 return 0; 241 } 242 243 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, 244 u8 dir, 245 u8 st_buf) 246 { 247 u32 reg; 248 249 reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL); 250 reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S))) | 251 (rknand->selected_bank << NAND_V6_BCH_REGION_S); 252 writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); 253 254 reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) | 255 NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT | 256 NANDC_V6_FL_ACORRECT; 257 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 258 259 reg |= NANDC_V6_FL_XFER_START; 260 writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); 261 } 262 263 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) 264 { 265 int timeout = NANDC_V6_DEF_TIMEOUT; 266 int reg; 267 268 while (timeout--) { 269 reg = readl(rknand->regs + NANDC_REG_V6_FLCTL); 270 271 if ((reg & NANDC_V6_FL_XFER_READY) != 0) 272 break; 273 274 udelay(1); 275 } 276 277 if (timeout == 0) 278 return -1; 279 280 return 0; 281 } 282 283 static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob) 284 { 285 struct nand_chip *chip = mtd_to_nand(mtd); 286 struct nand_ecc_ctrl *ecc = &chip->ecc; 287 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); 288 int len = mtd->oobsize - offset; 289 290 if (len <= 0) 291 return; 292 293 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1); 294 295 rockchip_nand_read_buf(mtd, oob + offset, len); 296 } 297 298 static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8 *oob) 299 { 300 struct nand_chip *chip = mtd_to_nand(mtd); 301 struct nand_ecc_ctrl *ecc = &chip->ecc; 302 int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); 303 int len = mtd->oobsize - offset; 304 305 if (len <= 0) 306 return; 307 308 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1); 309 310 rockchip_nand_write_buf(mtd, oob + offset, len); 311 } 312 313 static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info *mtd, 314 struct nand_chip *chip, 315 uint8_t *buf, 316 int oob_required, 317 int page) 318 { 319 struct rk_nand *rknand = to_rknand(chip->controller); 320 struct nand_ecc_ctrl *ecc = &chip->ecc; 321 void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0; 322 unsigned int max_bitflips = 0; 323 int ret, step, bch_st; 324 int offset = page * mtd->writesize; 325 326 if (rknand->bootromblocks && (offset < (7 * mtd->erasesize))) 327 rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC); 328 329 rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ, 0); 330 331 for (step = 0; step < ecc->steps; step++) { 332 int data_off = step * ecc->size; 333 int oob_off = step * (ecc->bytes + ecc->prepad); 334 u8 *data = buf + data_off; 335 u8 *oob = chip->oob_poi + oob_off; 336 337 ret = rockchip_nand_wait_pio_xfer_done(rknand); 338 if (ret) 339 return ret; 340 341 bch_st = readl(rknand->regs + NANDC_REG_V6_BCHST); 342 343 if (bch_st & NANDC_V6_BCH0_ST_ERR) { 344 mtd->ecc_stats.failed++; 345 max_bitflips = -1; 346 } else { 347 ret = NANDC_V6_ECC_ERR_CNT0(bch_st); 348 mtd->ecc_stats.corrected += ret; 349 max_bitflips = max_t(unsigned int, max_bitflips, ret); 350 } 351 352 if ((step + 1) < ecc->steps) 353 rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ, 354 (step + 1) & 0x1); 355 356 memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE * 357 (step & 1), ecc->size); 358 359 if (step & 1) 360 memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE1, 4); 361 else 362 memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE0, 4); 363 } 364 365 rockchip_nand_read_extra_oob(mtd, chip->oob_poi); 366 367 if (rknand->bootromblocks) 368 rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); 369 370 return max_bitflips; 371 } 372 373 static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd, 374 int page, 375 const u8 *oob, 376 bool bootromblocks) 377 { 378 int pages_per_block = mtd->erasesize / mtd->writesize; 379 int offset = page * mtd->writesize; 380 381 if ((offset < (2 * mtd->erasesize)) || !(page % 2) || 382 (offset >= (7 * mtd->erasesize)) || !bootromblocks) 383 return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] << 24); 384 385 return (page % pages_per_block + 1) * 4; 386 } 387 388 static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info *mtd, 389 struct nand_chip *chip, 390 const uint8_t *buf, 391 int oob_required, 392 int page) 393 { 394 struct rk_nand *rknand = to_rknand(chip->controller); 395 struct nand_ecc_ctrl *ecc = &chip->ecc; 396 void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0; 397 int ret, index, step = 0; 398 int offset = page * mtd->writesize; 399 int data_off = step * ecc->size; 400 int oob_off = step * (ecc->bytes + ecc->prepad); 401 const u8 *data = buf + data_off; 402 const u8 *oob = chip->oob_poi + oob_off; 403 404 if (rknand->bootromblocks && (offset < (7 * mtd->erasesize))) 405 rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC); 406 407 index = rockchip_nand_make_bootrom_compat(mtd, page, oob, 408 rknand->bootromblocks); 409 410 memcpy_toio(sram_base, data, ecc->size); 411 memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0, &index, ecc->prepad); 412 413 for (step = 1; step <= ecc->steps; step++) { 414 rockchip_nand_pio_xfer_start(rknand, NANDC_V6_WRITE, 415 (step - 1) & 0x1); 416 417 data_off = step * ecc->size; 418 oob_off = step * (ecc->bytes + ecc->prepad); 419 data = buf + data_off; 420 oob = chip->oob_poi + oob_off; 421 422 if (step < ecc->steps) { 423 memcpy_toio(sram_base + NANDC_REG_V6_SRAM_SIZE * 424 (step & 1), data, ecc->size); 425 if (step & 1) 426 memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE1, 427 oob, ecc->prepad); 428 else 429 memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0, 430 oob, ecc->prepad); 431 } 432 433 ret = rockchip_nand_wait_pio_xfer_done(rknand); 434 if (ret) 435 return ret; 436 } 437 438 rockchip_nand_write_extra_oob(mtd, chip->oob_poi); 439 440 rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); 441 442 return 0; 443 } 444 445 static const u8 strengths[] = {60, 40, 24, 16}; 446 447 static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd, 448 struct nand_ecc_ctrl *ecc) 449 { 450 uint32_t max_strength, index; 451 452 max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 / 14; 453 454 for (index = 0; index < ARRAY_SIZE(strengths); index++) 455 if (max_strength >= strengths[index]) 456 break; 457 458 if (index >= ARRAY_SIZE(strengths)) 459 return -ENOTSUPP; 460 461 return strengths[index]; 462 } 463 464 static bool rockchip_nand_strength_is_valid(int strength) 465 { 466 uint32_t index; 467 468 for (index = 0; index < ARRAY_SIZE(strengths); index++) 469 if (strength == strengths[index]) 470 break; 471 472 if (index == ARRAY_SIZE(strengths)) 473 return false; 474 475 return true; 476 } 477 478 static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 479 struct nand_ecc_ctrl *ecc) 480 { 481 struct nand_chip *chip = mtd_to_nand(mtd); 482 struct rk_nand *rknand = to_rknand(chip->controller); 483 uint32_t strength; 484 int index; 485 486 ecc->prepad = 4; 487 ecc->steps = mtd->writesize / ecc->size; 488 489 if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node, 490 "rockchip,protect-bootrom-blocks")) 491 rknand->bootromblocks = true; 492 else 493 rknand->bootromblocks = false; 494 495 if (rockchip_nand_strength_is_valid(ecc->strength)) 496 strength = ecc->strength; 497 else 498 strength = rockchip_nand_ecc_max_strength(mtd, ecc); 499 500 rockchip_nand_hw_ecc_setup(mtd, ecc, strength); 501 502 rknand->ecc_strength = ecc->strength; 503 504 nand_oob_fix.eccbytes = ecc->bytes * ecc->steps; 505 for (index = 0; index < ecc->bytes; index++) 506 nand_oob_fix.eccpos[index] = index + ecc->prepad; 507 ecc->layout = &nand_oob_fix; 508 509 if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) { 510 return -EINVAL; 511 } 512 513 return 0; 514 } 515 516 static int rockchip_nand_ecc_init(struct mtd_info *mtd, 517 struct nand_ecc_ctrl *ecc) 518 { 519 int ret; 520 521 switch (ecc->mode) { 522 case NAND_ECC_HW: 523 case NAND_ECC_HW_SYNDROME: 524 ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc); 525 if (ret) 526 return ret; 527 ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page; 528 ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page; 529 break; 530 case NAND_ECC_SOFT_BCH: 531 case NAND_ECC_NONE: 532 case NAND_ECC_SOFT: 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 return 0; 539 } 540 541 static int rockchip_nand_block_bad(struct mtd_info *mtd, loff_t ofs) 542 { 543 int page, res = 0; 544 struct nand_chip *chip = mtd_to_nand(mtd); 545 u16 bad = 0xff; 546 int chipnr = (int)(ofs >> chip->chip_shift); 547 548 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 549 chip->select_chip(mtd, chipnr); 550 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 551 if(rockchip_nand_hw_syndrome_pio_read_page(mtd, 552 chip, chip->buffers->databuf, 0, page) == -1) { 553 /* first page of the block*/ 554 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 555 bad = chip->read_byte(mtd); 556 if (bad != 0xFF) 557 res = 1; 558 /* second page of the block*/ 559 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, 560 page + 1); 561 bad = chip->read_byte(mtd); 562 if (bad != 0xFF) 563 res = 1; 564 /* last page of the block */ 565 page += ((mtd->erasesize - mtd->writesize) >> chip->chip_shift); 566 page--; 567 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 568 bad = chip->read_byte(mtd); 569 if (bad != 0xFF) 570 res = 1; 571 } 572 chip->select_chip(mtd, -1); 573 if (res) 574 printf("%s 0x%x %x %x\n", __func__, page, res, bad); 575 return res; 576 } 577 578 static int rockchip_nand_chip_init(int node, struct rk_nand *rknand, int devnum) 579 { 580 const void *blob = gd->fdt_blob; 581 struct nand_chip *chip; 582 struct mtd_info *mtd; 583 int ret; 584 585 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 586 587 chip->chip_delay = 50; 588 chip->flash_node = node; 589 chip->select_chip = rockchip_nand_select_chip; 590 chip->cmd_ctrl = rockchip_nand_cmd_ctrl; 591 chip->read_buf = rockchip_nand_read_buf; 592 chip->write_buf = rockchip_nand_write_buf; 593 chip->read_byte = rockchip_nand_read_byte; 594 chip->dev_ready = rockchip_nand_dev_ready; 595 chip->controller = &rknand->controller; 596 chip->block_bad = rockchip_nand_block_bad; 597 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 598 chip->options = NAND_NO_SUBPAGE_WRITE; 599 600 rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1); 601 602 if (rknand->banks[devnum] < 0) 603 return -EINVAL; 604 605 mtd = nand_to_mtd(chip); 606 mtd->dev = rknand->dev; 607 if (rknand->dev) 608 rknand->dev->priv = mtd; 609 610 ret = nand_scan_ident(mtd, 1, NULL); 611 if (ret) 612 return ret; 613 614 ret = rockchip_nand_ecc_init(mtd, &chip->ecc); 615 if (ret) { 616 debug("rockchip_nand_ecc_init failed: %d\n", ret); 617 return ret; 618 } 619 620 ret = nand_scan_tail(mtd); 621 if (ret) { 622 debug("nand_scan_tail failed: %d\n", ret); 623 return ret; 624 } 625 626 ret = nand_register(devnum, mtd); 627 if (ret) { 628 debug("Failed to register mtd device: %d\n", ret); 629 return ret; 630 } 631 memcpy(&rknand->mtd, mtd, sizeof(struct mtd_info)); 632 633 return 0; 634 } 635 636 static int rockchip_nand_chips_init(int node, struct rk_nand *rknand) 637 { 638 const void *blob = gd->fdt_blob; 639 int nand_node; 640 int ret, i = 0; 641 642 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0; 643 nand_node = fdt_next_subnode(blob, nand_node)) { 644 ret = rockchip_nand_chip_init(nand_node, rknand, i++); 645 if (ret) 646 return ret; 647 } 648 649 return 0; 650 } 651 652 #ifdef CONFIG_NAND_ROCKCHIP_DT 653 static const struct udevice_id rockchip_nandc_ids[] = { 654 { .compatible = "rockchip,rk-nandc" }, 655 { } 656 }; 657 658 static int rockchip_nandc_probe(struct udevice *dev) 659 { 660 const void *blob = gd->fdt_blob; 661 struct rk_nand *rknand = dev_get_priv(dev); 662 struct mtd_info *mtd = dev_get_uclass_priv(dev); 663 fdt_addr_t regs; 664 int ret = 0, node; 665 666 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 667 668 rknand->dev = dev; 669 670 regs = dev_read_addr(dev); 671 if (regs == FDT_ADDR_T_NONE) { 672 debug("Nand address not found\n"); 673 return ret; 674 } 675 676 rknand->regs = (void *)regs; 677 678 spin_lock_init(&rknand->controller.lock); 679 init_waitqueue_head(&rknand->controller.wq); 680 681 rockchip_nand_init(rknand); 682 683 ret = rockchip_nand_chips_init(node, rknand); 684 if (ret) 685 debug("Failed to init nand chips\n"); 686 687 memcpy(mtd, &rknand->mtd, sizeof(struct mtd_info)); 688 689 return ret; 690 } 691 692 static int rockchip_nandc_bind(struct udevice *udev) 693 { 694 int ret = 0; 695 696 #ifdef CONFIG_MTD_BLK 697 struct udevice *bdev; 698 699 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD, 700 BLK_MTD_NAND, 512, 0, &bdev); 701 if (ret) 702 printf("Cannot create block device\n"); 703 #endif 704 return ret; 705 } 706 707 U_BOOT_DRIVER(rk_nandc_v6) = { 708 .name = "rk_nandc_v6", 709 .id = UCLASS_MTD, 710 .of_match = rockchip_nandc_ids, 711 .bind = rockchip_nandc_bind, 712 .probe = rockchip_nandc_probe, 713 .priv_auto_alloc_size = sizeof(struct rk_nand), 714 }; 715 716 void board_nand_init(void) 717 { 718 struct udevice *dev; 719 int ret; 720 721 ret = uclass_get_device_by_driver(UCLASS_MTD, 722 DM_GET_DRIVER(rk_nandc_v6), 723 &dev); 724 if (ret && ret != -ENODEV) 725 pr_err("Failed to initialize NAND controller. (error %d)\n", 726 ret); 727 } 728 #else 729 730 void board_nand_init(void) 731 { 732 const void *blob = gd->fdt_blob; 733 struct rk_nand *rknand; 734 fdt_addr_t regs; 735 int node; 736 int ret; 737 738 rknand = kzalloc(sizeof(*rknand), GFP_KERNEL); 739 740 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); 741 742 if (node < 0) { 743 debug("Nand node not found\n"); 744 goto err; 745 } 746 747 if (!fdtdec_get_is_enabled(blob, node)) { 748 debug("Nand disabled in device tree\n"); 749 goto err; 750 } 751 752 regs = fdt_get_base_address(blob, node); 753 if (regs == FDT_ADDR_T_NONE) { 754 debug("Nand address not found\n"); 755 goto err; 756 } 757 758 rknand->regs = (void *)regs; 759 760 spin_lock_init(&rknand->controller.lock); 761 init_waitqueue_head(&rknand->controller.wq); 762 763 rockchip_nand_init(rknand); 764 765 ret = rockchip_nand_chips_init(node, rknand); 766 if (ret) { 767 debug("Failed to init nand chips\n"); 768 goto err; 769 } 770 771 return; 772 err: 773 kfree(rknand); 774 } 775 776 #endif 777 778 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) 779 { 780 struct mtd_info *mtd; 781 size_t length = size; 782 783 mtd = get_nand_dev_by_index(0); 784 return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst); 785 } 786 787 void nand_deselect(void) {} 788