nand_spl_load_image(uint32_t offs,unsigned int size,void * dst)1*cfcc706cSMiquel Raynal int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
2*cfcc706cSMiquel Raynal {
3*cfcc706cSMiquel Raynal unsigned int block, lastblock;
4*cfcc706cSMiquel Raynal unsigned int page, page_offset;
5*cfcc706cSMiquel Raynal
6*cfcc706cSMiquel Raynal /* offs has to be aligned to a page address! */
7*cfcc706cSMiquel Raynal block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
8*cfcc706cSMiquel Raynal lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
9*cfcc706cSMiquel Raynal page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
10*cfcc706cSMiquel Raynal page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
11*cfcc706cSMiquel Raynal
12*cfcc706cSMiquel Raynal while (block <= lastblock) {
13*cfcc706cSMiquel Raynal if (!nand_is_bad_block(block)) {
14*cfcc706cSMiquel Raynal /* Skip bad blocks */
15*cfcc706cSMiquel Raynal while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
16*cfcc706cSMiquel Raynal nand_read_page(block, page, dst);
17*cfcc706cSMiquel Raynal /*
18*cfcc706cSMiquel Raynal * When offs is not aligned to page address the
19*cfcc706cSMiquel Raynal * extra offset is copied to dst as well. Copy
20*cfcc706cSMiquel Raynal * the image such that its first byte will be
21*cfcc706cSMiquel Raynal * at the dst.
22*cfcc706cSMiquel Raynal */
23*cfcc706cSMiquel Raynal if (unlikely(page_offset)) {
24*cfcc706cSMiquel Raynal memmove(dst, dst + page_offset,
25*cfcc706cSMiquel Raynal CONFIG_SYS_NAND_PAGE_SIZE);
26*cfcc706cSMiquel Raynal dst = (void *)((int)dst - page_offset);
27*cfcc706cSMiquel Raynal page_offset = 0;
28*cfcc706cSMiquel Raynal }
29*cfcc706cSMiquel Raynal dst += CONFIG_SYS_NAND_PAGE_SIZE;
30*cfcc706cSMiquel Raynal page++;
31*cfcc706cSMiquel Raynal }
32*cfcc706cSMiquel Raynal
33*cfcc706cSMiquel Raynal page = 0;
34*cfcc706cSMiquel Raynal } else {
35*cfcc706cSMiquel Raynal lastblock++;
36*cfcc706cSMiquel Raynal }
37*cfcc706cSMiquel Raynal
38*cfcc706cSMiquel Raynal block++;
39*cfcc706cSMiquel Raynal }
40*cfcc706cSMiquel Raynal
41*cfcc706cSMiquel Raynal return 0;
42*cfcc706cSMiquel Raynal }
43*cfcc706cSMiquel Raynal
44*cfcc706cSMiquel Raynal #ifdef CONFIG_SPL_UBI
45*cfcc706cSMiquel Raynal /*
46*cfcc706cSMiquel Raynal * Temporary storage for non NAND page aligned and non NAND page sized
47*cfcc706cSMiquel Raynal * reads. Note: This does not support runtime detected FLASH yet, but
48*cfcc706cSMiquel Raynal * that should be reasonably easy to fix by making the buffer large
49*cfcc706cSMiquel Raynal * enough :)
50*cfcc706cSMiquel Raynal */
51*cfcc706cSMiquel Raynal static u8 scratch_buf[CONFIG_SYS_NAND_PAGE_SIZE];
52*cfcc706cSMiquel Raynal
53*cfcc706cSMiquel Raynal /**
54*cfcc706cSMiquel Raynal * nand_spl_read_block - Read data from physical eraseblock into a buffer
55*cfcc706cSMiquel Raynal * @block: Number of the physical eraseblock
56*cfcc706cSMiquel Raynal * @offset: Data offset from the start of @peb
57*cfcc706cSMiquel Raynal * @len: Data size to read
58*cfcc706cSMiquel Raynal * @dst: Address of the destination buffer
59*cfcc706cSMiquel Raynal *
60*cfcc706cSMiquel Raynal * This could be further optimized if we'd have a subpage read
61*cfcc706cSMiquel Raynal * function in the simple code. On NAND which allows subpage reads
62*cfcc706cSMiquel Raynal * this would spare quite some time to readout e.g. the VID header of
63*cfcc706cSMiquel Raynal * UBI.
64*cfcc706cSMiquel Raynal *
65*cfcc706cSMiquel Raynal * Notes:
66*cfcc706cSMiquel Raynal * @offset + @len are not allowed to be larger than a physical
67*cfcc706cSMiquel Raynal * erase block. No sanity check done for simplicity reasons.
68*cfcc706cSMiquel Raynal *
69*cfcc706cSMiquel Raynal * To support runtime detected flash this needs to be extended by
70*cfcc706cSMiquel Raynal * information about the actual flash geometry, but thats beyond the
71*cfcc706cSMiquel Raynal * scope of this effort and for most applications where fast boot is
72*cfcc706cSMiquel Raynal * required it is not an issue anyway.
73*cfcc706cSMiquel Raynal */
nand_spl_read_block(int block,int offset,int len,void * dst)74*cfcc706cSMiquel Raynal int nand_spl_read_block(int block, int offset, int len, void *dst)
75*cfcc706cSMiquel Raynal {
76*cfcc706cSMiquel Raynal int page, read;
77*cfcc706cSMiquel Raynal
78*cfcc706cSMiquel Raynal /* Calculate the page number */
79*cfcc706cSMiquel Raynal page = offset / CONFIG_SYS_NAND_PAGE_SIZE;
80*cfcc706cSMiquel Raynal
81*cfcc706cSMiquel Raynal /* Offset to the start of a flash page */
82*cfcc706cSMiquel Raynal offset = offset % CONFIG_SYS_NAND_PAGE_SIZE;
83*cfcc706cSMiquel Raynal
84*cfcc706cSMiquel Raynal while (len) {
85*cfcc706cSMiquel Raynal /*
86*cfcc706cSMiquel Raynal * Non page aligned reads go to the scratch buffer.
87*cfcc706cSMiquel Raynal * Page aligned reads go directly to the destination.
88*cfcc706cSMiquel Raynal */
89*cfcc706cSMiquel Raynal if (offset || len < CONFIG_SYS_NAND_PAGE_SIZE) {
90*cfcc706cSMiquel Raynal nand_read_page(block, page, scratch_buf);
91*cfcc706cSMiquel Raynal read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset);
92*cfcc706cSMiquel Raynal memcpy(dst, scratch_buf + offset, read);
93*cfcc706cSMiquel Raynal offset = 0;
94*cfcc706cSMiquel Raynal } else {
95*cfcc706cSMiquel Raynal nand_read_page(block, page, dst);
96*cfcc706cSMiquel Raynal read = CONFIG_SYS_NAND_PAGE_SIZE;
97*cfcc706cSMiquel Raynal }
98*cfcc706cSMiquel Raynal page++;
99*cfcc706cSMiquel Raynal len -= read;
100*cfcc706cSMiquel Raynal dst += read;
101*cfcc706cSMiquel Raynal }
102*cfcc706cSMiquel Raynal return 0;
103*cfcc706cSMiquel Raynal }
104*cfcc706cSMiquel Raynal #endif
105