1*cfcc706cSMiquel Raynal /* 2*cfcc706cSMiquel Raynal * Genericish driver for memory mapped NAND devices 3*cfcc706cSMiquel Raynal * 4*cfcc706cSMiquel Raynal * Copyright (c) 2006-2009 Analog Devices Inc. 5*cfcc706cSMiquel Raynal * Licensed under the GPL-2 or later. 6*cfcc706cSMiquel Raynal */ 7*cfcc706cSMiquel Raynal 8*cfcc706cSMiquel Raynal /* Your board must implement the following macros: 9*cfcc706cSMiquel Raynal * NAND_PLAT_WRITE_CMD(chip, cmd) 10*cfcc706cSMiquel Raynal * NAND_PLAT_WRITE_ADR(chip, cmd) 11*cfcc706cSMiquel Raynal * NAND_PLAT_INIT() 12*cfcc706cSMiquel Raynal * 13*cfcc706cSMiquel Raynal * It may also implement the following: 14*cfcc706cSMiquel Raynal * NAND_PLAT_DEV_READY(chip) 15*cfcc706cSMiquel Raynal */ 16*cfcc706cSMiquel Raynal 17*cfcc706cSMiquel Raynal #include <common.h> 18*cfcc706cSMiquel Raynal #include <asm/io.h> 19*cfcc706cSMiquel Raynal #ifdef NAND_PLAT_GPIO_DEV_READY 20*cfcc706cSMiquel Raynal # include <asm/gpio.h> 21*cfcc706cSMiquel Raynal # define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY) 22*cfcc706cSMiquel Raynal #endif 23*cfcc706cSMiquel Raynal 24*cfcc706cSMiquel Raynal #include <nand.h> 25*cfcc706cSMiquel Raynal plat_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)26*cfcc706cSMiquel Raynalstatic void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 27*cfcc706cSMiquel Raynal { 28*cfcc706cSMiquel Raynal struct nand_chip *this = mtd_to_nand(mtd); 29*cfcc706cSMiquel Raynal 30*cfcc706cSMiquel Raynal if (cmd == NAND_CMD_NONE) 31*cfcc706cSMiquel Raynal return; 32*cfcc706cSMiquel Raynal 33*cfcc706cSMiquel Raynal if (ctrl & NAND_CLE) 34*cfcc706cSMiquel Raynal NAND_PLAT_WRITE_CMD(this, cmd); 35*cfcc706cSMiquel Raynal else 36*cfcc706cSMiquel Raynal NAND_PLAT_WRITE_ADR(this, cmd); 37*cfcc706cSMiquel Raynal } 38*cfcc706cSMiquel Raynal 39*cfcc706cSMiquel Raynal #ifdef NAND_PLAT_DEV_READY plat_dev_ready(struct mtd_info * mtd)40*cfcc706cSMiquel Raynalstatic int plat_dev_ready(struct mtd_info *mtd) 41*cfcc706cSMiquel Raynal { 42*cfcc706cSMiquel Raynal return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd)); 43*cfcc706cSMiquel Raynal } 44*cfcc706cSMiquel Raynal #else 45*cfcc706cSMiquel Raynal # define plat_dev_ready NULL 46*cfcc706cSMiquel Raynal #endif 47*cfcc706cSMiquel Raynal board_nand_init(struct nand_chip * nand)48*cfcc706cSMiquel Raynalint board_nand_init(struct nand_chip *nand) 49*cfcc706cSMiquel Raynal { 50*cfcc706cSMiquel Raynal #ifdef NAND_PLAT_GPIO_DEV_READY 51*cfcc706cSMiquel Raynal gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat"); 52*cfcc706cSMiquel Raynal gpio_direction_input(NAND_PLAT_GPIO_DEV_READY); 53*cfcc706cSMiquel Raynal #endif 54*cfcc706cSMiquel Raynal 55*cfcc706cSMiquel Raynal #ifdef NAND_PLAT_INIT 56*cfcc706cSMiquel Raynal NAND_PLAT_INIT(); 57*cfcc706cSMiquel Raynal #endif 58*cfcc706cSMiquel Raynal 59*cfcc706cSMiquel Raynal nand->cmd_ctrl = plat_cmd_ctrl; 60*cfcc706cSMiquel Raynal nand->dev_ready = plat_dev_ready; 61*cfcc706cSMiquel Raynal nand->ecc.mode = NAND_ECC_SOFT; 62*cfcc706cSMiquel Raynal 63*cfcc706cSMiquel Raynal return 0; 64*cfcc706cSMiquel Raynal } 65