1 /* 2 * Copyright (C) 2014 Panasonic Corporation 3 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com> 4 * Copyright (C) 2009-2010, Intel Corporation and its suppliers. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <dm.h> 10 #include <nand.h> 11 #include <linux/bitfield.h> 12 #include <linux/dma-direction.h> 13 #include <linux/errno.h> 14 #include <linux/io.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/rawnand.h> 17 18 #include "denali.h" 19 20 static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size, 21 enum dma_data_direction dir) 22 { 23 unsigned long addr = (unsigned long)ptr; 24 25 size = ALIGN(size, ARCH_DMA_MINALIGN); 26 27 if (dir == DMA_FROM_DEVICE) 28 invalidate_dcache_range(addr, addr + size); 29 else 30 flush_dcache_range(addr, addr + size); 31 32 return addr; 33 } 34 35 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size, 36 enum dma_data_direction dir) 37 { 38 size = ALIGN(size, ARCH_DMA_MINALIGN); 39 40 if (dir != DMA_TO_DEVICE) 41 invalidate_dcache_range(addr, addr + size); 42 } 43 44 static int dma_mapping_error(void *dev, dma_addr_t addr) 45 { 46 return 0; 47 } 48 49 #define DENALI_NAND_NAME "denali-nand" 50 51 /* for Indexed Addressing */ 52 #define DENALI_INDEXED_CTRL 0x00 53 #define DENALI_INDEXED_DATA 0x10 54 55 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */ 56 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ 57 #define DENALI_MAP10 (2 << 26) /* high-level control plane */ 58 #define DENALI_MAP11 (3 << 26) /* direct controller access */ 59 60 /* MAP11 access cycle type */ 61 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */ 62 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */ 63 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */ 64 65 /* MAP10 commands */ 66 #define DENALI_ERASE 0x01 67 68 #define DENALI_BANK(denali) ((denali)->active_bank << 24) 69 70 #define DENALI_INVALID_BANK -1 71 #define DENALI_NR_BANKS 4 72 73 /* 74 * The bus interface clock, clk_x, is phase aligned with the core clock. The 75 * clk_x is an integral multiple N of the core clk. The value N is configured 76 * at IP delivery time, and its available value is 4, 5, or 6. We need to align 77 * to the largest value to make it work with any possible configuration. 78 */ 79 #define DENALI_CLK_X_MULT 6 80 81 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) 82 { 83 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); 84 } 85 86 /* 87 * Direct Addressing - the slave address forms the control information (command 88 * type, bank, block, and page address). The slave data is the actual data to 89 * be transferred. This mode requires 28 bits of address region allocated. 90 */ 91 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr) 92 { 93 return ioread32(denali->host + addr); 94 } 95 96 static void denali_direct_write(struct denali_nand_info *denali, u32 addr, 97 u32 data) 98 { 99 iowrite32(data, denali->host + addr); 100 } 101 102 /* 103 * Indexed Addressing - address translation module intervenes in passing the 104 * control information. This mode reduces the required address range. The 105 * control information and transferred data are latched by the registers in 106 * the translation module. 107 */ 108 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr) 109 { 110 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 111 return ioread32(denali->host + DENALI_INDEXED_DATA); 112 } 113 114 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr, 115 u32 data) 116 { 117 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 118 iowrite32(data, denali->host + DENALI_INDEXED_DATA); 119 } 120 121 /* 122 * Use the configuration feature register to determine the maximum number of 123 * banks that the hardware supports. 124 */ 125 static void denali_detect_max_banks(struct denali_nand_info *denali) 126 { 127 uint32_t features = ioread32(denali->reg + FEATURES); 128 129 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); 130 131 /* the encoding changed from rev 5.0 to 5.1 */ 132 if (denali->revision < 0x0501) 133 denali->max_banks <<= 1; 134 } 135 136 static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali) 137 { 138 int i; 139 140 for (i = 0; i < DENALI_NR_BANKS; i++) 141 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); 142 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); 143 } 144 145 static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali) 146 { 147 int i; 148 149 for (i = 0; i < DENALI_NR_BANKS; i++) 150 iowrite32(0, denali->reg + INTR_EN(i)); 151 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); 152 } 153 154 static void denali_clear_irq(struct denali_nand_info *denali, 155 int bank, uint32_t irq_status) 156 { 157 /* write one to clear bits */ 158 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); 159 } 160 161 static void denali_clear_irq_all(struct denali_nand_info *denali) 162 { 163 int i; 164 165 for (i = 0; i < DENALI_NR_BANKS; i++) 166 denali_clear_irq(denali, i, U32_MAX); 167 } 168 169 static void __denali_check_irq(struct denali_nand_info *denali) 170 { 171 uint32_t irq_status; 172 int i; 173 174 for (i = 0; i < DENALI_NR_BANKS; i++) { 175 irq_status = ioread32(denali->reg + INTR_STATUS(i)); 176 denali_clear_irq(denali, i, irq_status); 177 178 if (i != denali->active_bank) 179 continue; 180 181 denali->irq_status |= irq_status; 182 } 183 } 184 185 static void denali_reset_irq(struct denali_nand_info *denali) 186 { 187 denali->irq_status = 0; 188 denali->irq_mask = 0; 189 } 190 191 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, 192 uint32_t irq_mask) 193 { 194 unsigned long time_left = 1000000; 195 196 while (time_left) { 197 __denali_check_irq(denali); 198 199 if (irq_mask & denali->irq_status) 200 return denali->irq_status; 201 udelay(1); 202 time_left--; 203 } 204 205 if (!time_left) { 206 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", 207 irq_mask); 208 return 0; 209 } 210 211 return denali->irq_status; 212 } 213 214 static uint32_t denali_check_irq(struct denali_nand_info *denali) 215 { 216 __denali_check_irq(denali); 217 218 return denali->irq_status; 219 } 220 221 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 222 { 223 struct denali_nand_info *denali = mtd_to_denali(mtd); 224 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 225 int i; 226 227 for (i = 0; i < len; i++) 228 buf[i] = denali->host_read(denali, addr); 229 } 230 231 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 232 { 233 struct denali_nand_info *denali = mtd_to_denali(mtd); 234 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 235 int i; 236 237 for (i = 0; i < len; i++) 238 denali->host_write(denali, addr, buf[i]); 239 } 240 241 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 242 { 243 struct denali_nand_info *denali = mtd_to_denali(mtd); 244 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 245 uint16_t *buf16 = (uint16_t *)buf; 246 int i; 247 248 for (i = 0; i < len / 2; i++) 249 buf16[i] = denali->host_read(denali, addr); 250 } 251 252 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf, 253 int len) 254 { 255 struct denali_nand_info *denali = mtd_to_denali(mtd); 256 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 257 const uint16_t *buf16 = (const uint16_t *)buf; 258 int i; 259 260 for (i = 0; i < len / 2; i++) 261 denali->host_write(denali, addr, buf16[i]); 262 } 263 264 static uint8_t denali_read_byte(struct mtd_info *mtd) 265 { 266 uint8_t byte; 267 268 denali_read_buf(mtd, &byte, 1); 269 270 return byte; 271 } 272 273 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte) 274 { 275 denali_write_buf(mtd, &byte, 1); 276 } 277 278 static uint16_t denali_read_word(struct mtd_info *mtd) 279 { 280 uint16_t word; 281 282 denali_read_buf16(mtd, (uint8_t *)&word, 2); 283 284 return word; 285 } 286 287 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) 288 { 289 struct denali_nand_info *denali = mtd_to_denali(mtd); 290 uint32_t type; 291 292 if (ctrl & NAND_CLE) 293 type = DENALI_MAP11_CMD; 294 else if (ctrl & NAND_ALE) 295 type = DENALI_MAP11_ADDR; 296 else 297 return; 298 299 /* 300 * Some commands are followed by chip->dev_ready or chip->waitfunc. 301 * irq_status must be cleared here to catch the R/B# interrupt later. 302 */ 303 if (ctrl & NAND_CTRL_CHANGE) 304 denali_reset_irq(denali); 305 306 denali->host_write(denali, DENALI_BANK(denali) | type, dat); 307 } 308 309 static int denali_dev_ready(struct mtd_info *mtd) 310 { 311 struct denali_nand_info *denali = mtd_to_denali(mtd); 312 313 return !!(denali_check_irq(denali) & INTR__INT_ACT); 314 } 315 316 static int denali_check_erased_page(struct mtd_info *mtd, 317 struct nand_chip *chip, uint8_t *buf, 318 unsigned long uncor_ecc_flags, 319 unsigned int max_bitflips) 320 { 321 uint8_t *ecc_code = chip->buffers->ecccode; 322 int ecc_steps = chip->ecc.steps; 323 int ecc_size = chip->ecc.size; 324 int ecc_bytes = chip->ecc.bytes; 325 int i, ret, stat; 326 327 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 328 chip->ecc.total); 329 if (ret) 330 return ret; 331 332 for (i = 0; i < ecc_steps; i++) { 333 if (!(uncor_ecc_flags & BIT(i))) 334 continue; 335 336 stat = nand_check_erased_ecc_chunk(buf, ecc_size, 337 ecc_code, ecc_bytes, 338 NULL, 0, 339 chip->ecc.strength); 340 if (stat < 0) { 341 mtd->ecc_stats.failed++; 342 } else { 343 mtd->ecc_stats.corrected += stat; 344 max_bitflips = max_t(unsigned int, max_bitflips, stat); 345 } 346 347 buf += ecc_size; 348 ecc_code += ecc_bytes; 349 } 350 351 return max_bitflips; 352 } 353 354 static int denali_hw_ecc_fixup(struct mtd_info *mtd, 355 struct denali_nand_info *denali, 356 unsigned long *uncor_ecc_flags) 357 { 358 struct nand_chip *chip = mtd_to_nand(mtd); 359 int bank = denali->active_bank; 360 uint32_t ecc_cor; 361 unsigned int max_bitflips; 362 363 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); 364 ecc_cor >>= ECC_COR_INFO__SHIFT(bank); 365 366 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) { 367 /* 368 * This flag is set when uncorrectable error occurs at least in 369 * one ECC sector. We can not know "how many sectors", or 370 * "which sector(s)". We need erase-page check for all sectors. 371 */ 372 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); 373 return 0; 374 } 375 376 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor); 377 378 /* 379 * The register holds the maximum of per-sector corrected bitflips. 380 * This is suitable for the return value of the ->read_page() callback. 381 * Unfortunately, we can not know the total number of corrected bits in 382 * the page. Increase the stats by max_bitflips. (compromised solution) 383 */ 384 mtd->ecc_stats.corrected += max_bitflips; 385 386 return max_bitflips; 387 } 388 389 static int denali_sw_ecc_fixup(struct mtd_info *mtd, 390 struct denali_nand_info *denali, 391 unsigned long *uncor_ecc_flags, uint8_t *buf) 392 { 393 unsigned int ecc_size = denali->nand.ecc.size; 394 unsigned int bitflips = 0; 395 unsigned int max_bitflips = 0; 396 uint32_t err_addr, err_cor_info; 397 unsigned int err_byte, err_sector, err_device; 398 uint8_t err_cor_value; 399 unsigned int prev_sector = 0; 400 uint32_t irq_status; 401 402 denali_reset_irq(denali); 403 404 do { 405 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); 406 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr); 407 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr); 408 409 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); 410 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE, 411 err_cor_info); 412 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE, 413 err_cor_info); 414 415 /* reset the bitflip counter when crossing ECC sector */ 416 if (err_sector != prev_sector) 417 bitflips = 0; 418 419 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) { 420 /* 421 * Check later if this is a real ECC error, or 422 * an erased sector. 423 */ 424 *uncor_ecc_flags |= BIT(err_sector); 425 } else if (err_byte < ecc_size) { 426 /* 427 * If err_byte is larger than ecc_size, means error 428 * happened in OOB, so we ignore it. It's no need for 429 * us to correct it err_device is represented the NAND 430 * error bits are happened in if there are more than 431 * one NAND connected. 432 */ 433 int offset; 434 unsigned int flips_in_byte; 435 436 offset = (err_sector * ecc_size + err_byte) * 437 denali->devs_per_cs + err_device; 438 439 /* correct the ECC error */ 440 flips_in_byte = hweight8(buf[offset] ^ err_cor_value); 441 buf[offset] ^= err_cor_value; 442 mtd->ecc_stats.corrected += flips_in_byte; 443 bitflips += flips_in_byte; 444 445 max_bitflips = max(max_bitflips, bitflips); 446 } 447 448 prev_sector = err_sector; 449 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR)); 450 451 /* 452 * Once handle all ECC errors, controller will trigger an 453 * ECC_TRANSACTION_DONE interrupt. 454 */ 455 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); 456 if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) 457 return -EIO; 458 459 return max_bitflips; 460 } 461 462 static void denali_setup_dma64(struct denali_nand_info *denali, 463 dma_addr_t dma_addr, int page, int write) 464 { 465 uint32_t mode; 466 const int page_count = 1; 467 468 mode = DENALI_MAP10 | DENALI_BANK(denali) | page; 469 470 /* DMA is a three step process */ 471 472 /* 473 * 1. setup transfer type, interrupt when complete, 474 * burst len = 64 bytes, the number of pages 475 */ 476 denali->host_write(denali, mode, 477 0x01002000 | (64 << 16) | (write << 8) | page_count); 478 479 /* 2. set memory low address */ 480 denali->host_write(denali, mode, lower_32_bits(dma_addr)); 481 482 /* 3. set memory high address */ 483 denali->host_write(denali, mode, upper_32_bits(dma_addr)); 484 } 485 486 static void denali_setup_dma32(struct denali_nand_info *denali, 487 dma_addr_t dma_addr, int page, int write) 488 { 489 uint32_t mode; 490 const int page_count = 1; 491 492 mode = DENALI_MAP10 | DENALI_BANK(denali); 493 494 /* DMA is a four step process */ 495 496 /* 1. setup transfer type and # of pages */ 497 denali->host_write(denali, mode | page, 498 0x2000 | (write << 8) | page_count); 499 500 /* 2. set memory high address bits 23:8 */ 501 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); 502 503 /* 3. set memory low address bits 23:8 */ 504 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); 505 506 /* 4. interrupt when complete, burst len = 64 bytes */ 507 denali->host_write(denali, mode | 0x14000, 0x2400); 508 } 509 510 static int denali_pio_read(struct denali_nand_info *denali, void *buf, 511 size_t size, int page, int raw) 512 { 513 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 514 uint32_t *buf32 = (uint32_t *)buf; 515 uint32_t irq_status, ecc_err_mask; 516 int i; 517 518 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 519 ecc_err_mask = INTR__ECC_UNCOR_ERR; 520 else 521 ecc_err_mask = INTR__ECC_ERR; 522 523 denali_reset_irq(denali); 524 525 for (i = 0; i < size / 4; i++) 526 *buf32++ = denali->host_read(denali, addr); 527 528 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); 529 if (!(irq_status & INTR__PAGE_XFER_INC)) 530 return -EIO; 531 532 if (irq_status & INTR__ERASED_PAGE) 533 memset(buf, 0xff, size); 534 535 return irq_status & ecc_err_mask ? -EBADMSG : 0; 536 } 537 538 static int denali_pio_write(struct denali_nand_info *denali, 539 const void *buf, size_t size, int page, int raw) 540 { 541 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 542 const uint32_t *buf32 = (uint32_t *)buf; 543 uint32_t irq_status; 544 int i; 545 546 denali_reset_irq(denali); 547 548 for (i = 0; i < size / 4; i++) 549 denali->host_write(denali, addr, *buf32++); 550 551 irq_status = denali_wait_for_irq(denali, 552 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); 553 if (!(irq_status & INTR__PROGRAM_COMP)) 554 return -EIO; 555 556 return 0; 557 } 558 559 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, 560 size_t size, int page, int raw, int write) 561 { 562 if (write) 563 return denali_pio_write(denali, buf, size, page, raw); 564 else 565 return denali_pio_read(denali, buf, size, page, raw); 566 } 567 568 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, 569 size_t size, int page, int raw, int write) 570 { 571 dma_addr_t dma_addr; 572 uint32_t irq_mask, irq_status, ecc_err_mask; 573 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 574 int ret = 0; 575 576 dma_addr = dma_map_single(denali->dev, buf, size, dir); 577 if (dma_mapping_error(denali->dev, dma_addr)) { 578 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); 579 return denali_pio_xfer(denali, buf, size, page, raw, write); 580 } 581 582 if (write) { 583 /* 584 * INTR__PROGRAM_COMP is never asserted for the DMA transfer. 585 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted 586 * when the page program is completed. 587 */ 588 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL; 589 ecc_err_mask = 0; 590 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { 591 irq_mask = INTR__DMA_CMD_COMP; 592 ecc_err_mask = INTR__ECC_UNCOR_ERR; 593 } else { 594 irq_mask = INTR__DMA_CMD_COMP; 595 ecc_err_mask = INTR__ECC_ERR; 596 } 597 598 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); 599 600 denali_reset_irq(denali); 601 denali->setup_dma(denali, dma_addr, page, write); 602 603 irq_status = denali_wait_for_irq(denali, irq_mask); 604 if (!(irq_status & INTR__DMA_CMD_COMP)) 605 ret = -EIO; 606 else if (irq_status & ecc_err_mask) 607 ret = -EBADMSG; 608 609 iowrite32(0, denali->reg + DMA_ENABLE); 610 611 dma_unmap_single(denali->dev, dma_addr, size, dir); 612 613 if (irq_status & INTR__ERASED_PAGE) 614 memset(buf, 0xff, size); 615 616 return ret; 617 } 618 619 static int denali_data_xfer(struct denali_nand_info *denali, void *buf, 620 size_t size, int page, int raw, int write) 621 { 622 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); 623 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0, 624 denali->reg + TRANSFER_SPARE_REG); 625 626 if (denali->dma_avail) 627 return denali_dma_xfer(denali, buf, size, page, raw, write); 628 else 629 return denali_pio_xfer(denali, buf, size, page, raw, write); 630 } 631 632 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip, 633 int page, int write) 634 { 635 struct denali_nand_info *denali = mtd_to_denali(mtd); 636 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0; 637 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT; 638 int writesize = mtd->writesize; 639 int oobsize = mtd->oobsize; 640 uint8_t *bufpoi = chip->oob_poi; 641 int ecc_steps = chip->ecc.steps; 642 int ecc_size = chip->ecc.size; 643 int ecc_bytes = chip->ecc.bytes; 644 int oob_skip = denali->oob_skip_bytes; 645 size_t size = writesize + oobsize; 646 int i, pos, len; 647 648 /* BBM at the beginning of the OOB area */ 649 chip->cmdfunc(mtd, start_cmd, writesize, page); 650 if (write) 651 chip->write_buf(mtd, bufpoi, oob_skip); 652 else 653 chip->read_buf(mtd, bufpoi, oob_skip); 654 bufpoi += oob_skip; 655 656 /* OOB ECC */ 657 for (i = 0; i < ecc_steps; i++) { 658 pos = ecc_size + i * (ecc_size + ecc_bytes); 659 len = ecc_bytes; 660 661 if (pos >= writesize) 662 pos += oob_skip; 663 else if (pos + len > writesize) 664 len = writesize - pos; 665 666 chip->cmdfunc(mtd, rnd_cmd, pos, -1); 667 if (write) 668 chip->write_buf(mtd, bufpoi, len); 669 else 670 chip->read_buf(mtd, bufpoi, len); 671 bufpoi += len; 672 if (len < ecc_bytes) { 673 len = ecc_bytes - len; 674 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1); 675 if (write) 676 chip->write_buf(mtd, bufpoi, len); 677 else 678 chip->read_buf(mtd, bufpoi, len); 679 bufpoi += len; 680 } 681 } 682 683 /* OOB free */ 684 len = oobsize - (bufpoi - chip->oob_poi); 685 chip->cmdfunc(mtd, rnd_cmd, size - len, -1); 686 if (write) 687 chip->write_buf(mtd, bufpoi, len); 688 else 689 chip->read_buf(mtd, bufpoi, len); 690 } 691 692 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 693 uint8_t *buf, int oob_required, int page) 694 { 695 struct denali_nand_info *denali = mtd_to_denali(mtd); 696 int writesize = mtd->writesize; 697 int oobsize = mtd->oobsize; 698 int ecc_steps = chip->ecc.steps; 699 int ecc_size = chip->ecc.size; 700 int ecc_bytes = chip->ecc.bytes; 701 void *tmp_buf = denali->buf; 702 int oob_skip = denali->oob_skip_bytes; 703 size_t size = writesize + oobsize; 704 int ret, i, pos, len; 705 706 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0); 707 if (ret) 708 return ret; 709 710 /* Arrange the buffer for syndrome payload/ecc layout */ 711 if (buf) { 712 for (i = 0; i < ecc_steps; i++) { 713 pos = i * (ecc_size + ecc_bytes); 714 len = ecc_size; 715 716 if (pos >= writesize) 717 pos += oob_skip; 718 else if (pos + len > writesize) 719 len = writesize - pos; 720 721 memcpy(buf, tmp_buf + pos, len); 722 buf += len; 723 if (len < ecc_size) { 724 len = ecc_size - len; 725 memcpy(buf, tmp_buf + writesize + oob_skip, 726 len); 727 buf += len; 728 } 729 } 730 } 731 732 if (oob_required) { 733 uint8_t *oob = chip->oob_poi; 734 735 /* BBM at the beginning of the OOB area */ 736 memcpy(oob, tmp_buf + writesize, oob_skip); 737 oob += oob_skip; 738 739 /* OOB ECC */ 740 for (i = 0; i < ecc_steps; i++) { 741 pos = ecc_size + i * (ecc_size + ecc_bytes); 742 len = ecc_bytes; 743 744 if (pos >= writesize) 745 pos += oob_skip; 746 else if (pos + len > writesize) 747 len = writesize - pos; 748 749 memcpy(oob, tmp_buf + pos, len); 750 oob += len; 751 if (len < ecc_bytes) { 752 len = ecc_bytes - len; 753 memcpy(oob, tmp_buf + writesize + oob_skip, 754 len); 755 oob += len; 756 } 757 } 758 759 /* OOB free */ 760 len = oobsize - (oob - chip->oob_poi); 761 memcpy(oob, tmp_buf + size - len, len); 762 } 763 764 return 0; 765 } 766 767 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 768 int page) 769 { 770 denali_oob_xfer(mtd, chip, page, 0); 771 772 return 0; 773 } 774 775 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 776 int page) 777 { 778 struct denali_nand_info *denali = mtd_to_denali(mtd); 779 int status; 780 781 denali_reset_irq(denali); 782 783 denali_oob_xfer(mtd, chip, page, 1); 784 785 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 786 status = chip->waitfunc(mtd, chip); 787 788 return status & NAND_STATUS_FAIL ? -EIO : 0; 789 } 790 791 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, 792 uint8_t *buf, int oob_required, int page) 793 { 794 struct denali_nand_info *denali = mtd_to_denali(mtd); 795 unsigned long uncor_ecc_flags = 0; 796 int stat = 0; 797 int ret; 798 799 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0); 800 if (ret && ret != -EBADMSG) 801 return ret; 802 803 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 804 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags); 805 else if (ret == -EBADMSG) 806 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf); 807 808 if (stat < 0) 809 return stat; 810 811 if (uncor_ecc_flags) { 812 ret = denali_read_oob(mtd, chip, page); 813 if (ret) 814 return ret; 815 816 stat = denali_check_erased_page(mtd, chip, buf, 817 uncor_ecc_flags, stat); 818 } 819 820 return stat; 821 } 822 823 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 824 const uint8_t *buf, int oob_required, int page) 825 { 826 struct denali_nand_info *denali = mtd_to_denali(mtd); 827 int writesize = mtd->writesize; 828 int oobsize = mtd->oobsize; 829 int ecc_steps = chip->ecc.steps; 830 int ecc_size = chip->ecc.size; 831 int ecc_bytes = chip->ecc.bytes; 832 void *tmp_buf = denali->buf; 833 int oob_skip = denali->oob_skip_bytes; 834 size_t size = writesize + oobsize; 835 int i, pos, len; 836 837 /* 838 * Fill the buffer with 0xff first except the full page transfer. 839 * This simplifies the logic. 840 */ 841 if (!buf || !oob_required) 842 memset(tmp_buf, 0xff, size); 843 844 /* Arrange the buffer for syndrome payload/ecc layout */ 845 if (buf) { 846 for (i = 0; i < ecc_steps; i++) { 847 pos = i * (ecc_size + ecc_bytes); 848 len = ecc_size; 849 850 if (pos >= writesize) 851 pos += oob_skip; 852 else if (pos + len > writesize) 853 len = writesize - pos; 854 855 memcpy(tmp_buf + pos, buf, len); 856 buf += len; 857 if (len < ecc_size) { 858 len = ecc_size - len; 859 memcpy(tmp_buf + writesize + oob_skip, buf, 860 len); 861 buf += len; 862 } 863 } 864 } 865 866 if (oob_required) { 867 const uint8_t *oob = chip->oob_poi; 868 869 /* BBM at the beginning of the OOB area */ 870 memcpy(tmp_buf + writesize, oob, oob_skip); 871 oob += oob_skip; 872 873 /* OOB ECC */ 874 for (i = 0; i < ecc_steps; i++) { 875 pos = ecc_size + i * (ecc_size + ecc_bytes); 876 len = ecc_bytes; 877 878 if (pos >= writesize) 879 pos += oob_skip; 880 else if (pos + len > writesize) 881 len = writesize - pos; 882 883 memcpy(tmp_buf + pos, oob, len); 884 oob += len; 885 if (len < ecc_bytes) { 886 len = ecc_bytes - len; 887 memcpy(tmp_buf + writesize + oob_skip, oob, 888 len); 889 oob += len; 890 } 891 } 892 893 /* OOB free */ 894 len = oobsize - (oob - chip->oob_poi); 895 memcpy(tmp_buf + size - len, oob, len); 896 } 897 898 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1); 899 } 900 901 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, 902 const uint8_t *buf, int oob_required, int page) 903 { 904 struct denali_nand_info *denali = mtd_to_denali(mtd); 905 906 return denali_data_xfer(denali, (void *)buf, mtd->writesize, 907 page, 0, 1); 908 } 909 910 static void denali_select_chip(struct mtd_info *mtd, int chip) 911 { 912 struct denali_nand_info *denali = mtd_to_denali(mtd); 913 914 denali->active_bank = chip; 915 } 916 917 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) 918 { 919 struct denali_nand_info *denali = mtd_to_denali(mtd); 920 uint32_t irq_status; 921 922 /* R/B# pin transitioned from low to high? */ 923 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); 924 925 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL; 926 } 927 928 static int denali_erase(struct mtd_info *mtd, int page) 929 { 930 struct denali_nand_info *denali = mtd_to_denali(mtd); 931 uint32_t irq_status; 932 933 denali_reset_irq(denali); 934 935 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, 936 DENALI_ERASE); 937 938 /* wait for erase to complete or failure to occur */ 939 irq_status = denali_wait_for_irq(denali, 940 INTR__ERASE_COMP | INTR__ERASE_FAIL); 941 942 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL; 943 } 944 945 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, 946 const struct nand_data_interface *conf) 947 { 948 struct denali_nand_info *denali = mtd_to_denali(mtd); 949 const struct nand_sdr_timings *timings; 950 unsigned long t_clk; 951 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; 952 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; 953 int addr_2_data_mask; 954 uint32_t tmp; 955 956 timings = nand_get_sdr_timings(conf); 957 if (IS_ERR(timings)) 958 return PTR_ERR(timings); 959 960 /* clk_x period in picoseconds */ 961 t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); 962 if (!t_clk) 963 return -EINVAL; 964 965 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 966 return 0; 967 968 /* tREA -> ACC_CLKS */ 969 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); 970 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); 971 972 tmp = ioread32(denali->reg + ACC_CLKS); 973 tmp &= ~ACC_CLKS__VALUE; 974 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); 975 iowrite32(tmp, denali->reg + ACC_CLKS); 976 977 /* tRWH -> RE_2_WE */ 978 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); 979 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); 980 981 tmp = ioread32(denali->reg + RE_2_WE); 982 tmp &= ~RE_2_WE__VALUE; 983 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); 984 iowrite32(tmp, denali->reg + RE_2_WE); 985 986 /* tRHZ -> RE_2_RE */ 987 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); 988 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); 989 990 tmp = ioread32(denali->reg + RE_2_RE); 991 tmp &= ~RE_2_RE__VALUE; 992 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); 993 iowrite32(tmp, denali->reg + RE_2_RE); 994 995 /* 996 * tCCS, tWHR -> WE_2_RE 997 * 998 * With WE_2_RE properly set, the Denali controller automatically takes 999 * care of the delay; the driver need not set NAND_WAIT_TCCS. 1000 */ 1001 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), 1002 t_clk); 1003 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); 1004 1005 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); 1006 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; 1007 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); 1008 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); 1009 1010 /* tADL -> ADDR_2_DATA */ 1011 1012 /* for older versions, ADDR_2_DATA is only 6 bit wide */ 1013 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 1014 if (denali->revision < 0x0501) 1015 addr_2_data_mask >>= 1; 1016 1017 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); 1018 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); 1019 1020 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); 1021 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 1022 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); 1023 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); 1024 1025 /* tREH, tWH -> RDWR_EN_HI_CNT */ 1026 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), 1027 t_clk); 1028 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); 1029 1030 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); 1031 tmp &= ~RDWR_EN_HI_CNT__VALUE; 1032 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); 1033 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); 1034 1035 /* tRP, tWP -> RDWR_EN_LO_CNT */ 1036 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), 1037 t_clk); 1038 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), 1039 t_clk); 1040 rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); 1041 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); 1042 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); 1043 1044 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); 1045 tmp &= ~RDWR_EN_LO_CNT__VALUE; 1046 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); 1047 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); 1048 1049 /* tCS, tCEA -> CS_SETUP_CNT */ 1050 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, 1051 (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, 1052 0); 1053 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); 1054 1055 tmp = ioread32(denali->reg + CS_SETUP_CNT); 1056 tmp &= ~CS_SETUP_CNT__VALUE; 1057 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); 1058 iowrite32(tmp, denali->reg + CS_SETUP_CNT); 1059 1060 return 0; 1061 } 1062 1063 static void denali_reset_banks(struct denali_nand_info *denali) 1064 { 1065 u32 irq_status; 1066 int i; 1067 1068 for (i = 0; i < denali->max_banks; i++) { 1069 denali->active_bank = i; 1070 1071 denali_reset_irq(denali); 1072 1073 iowrite32(DEVICE_RESET__BANK(i), 1074 denali->reg + DEVICE_RESET); 1075 1076 irq_status = denali_wait_for_irq(denali, 1077 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT); 1078 if (!(irq_status & INTR__INT_ACT)) 1079 break; 1080 } 1081 1082 dev_dbg(denali->dev, "%d chips connected\n", i); 1083 denali->max_banks = i; 1084 } 1085 1086 static void denali_hw_init(struct denali_nand_info *denali) 1087 { 1088 /* 1089 * The REVISION register may not be reliable. Platforms are allowed to 1090 * override it. 1091 */ 1092 if (!denali->revision) 1093 denali->revision = swab16(ioread32(denali->reg + REVISION)); 1094 1095 /* 1096 * tell driver how many bit controller will skip before writing 1097 * ECC code in OOB. This is normally used for bad block marker 1098 */ 1099 denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES; 1100 iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES); 1101 denali_detect_max_banks(denali); 1102 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); 1103 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); 1104 1105 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); 1106 } 1107 1108 int denali_calc_ecc_bytes(int step_size, int strength) 1109 { 1110 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */ 1111 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2; 1112 } 1113 EXPORT_SYMBOL(denali_calc_ecc_bytes); 1114 1115 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, 1116 struct denali_nand_info *denali) 1117 { 1118 int oobavail = mtd->oobsize - denali->oob_skip_bytes; 1119 int ret; 1120 1121 /* 1122 * If .size and .strength are already set (usually by DT), 1123 * check if they are supported by this controller. 1124 */ 1125 if (chip->ecc.size && chip->ecc.strength) 1126 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail); 1127 1128 /* 1129 * We want .size and .strength closest to the chip's requirement 1130 * unless NAND_ECC_MAXIMIZE is requested. 1131 */ 1132 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) { 1133 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail); 1134 if (!ret) 1135 return 0; 1136 } 1137 1138 /* Max ECC strength is the last thing we can do */ 1139 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail); 1140 } 1141 1142 static struct nand_ecclayout nand_oob; 1143 1144 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, 1145 struct mtd_oob_region *oobregion) 1146 { 1147 struct denali_nand_info *denali = mtd_to_denali(mtd); 1148 struct nand_chip *chip = mtd_to_nand(mtd); 1149 1150 if (section) 1151 return -ERANGE; 1152 1153 oobregion->offset = denali->oob_skip_bytes; 1154 oobregion->length = chip->ecc.total; 1155 1156 return 0; 1157 } 1158 1159 static int denali_ooblayout_free(struct mtd_info *mtd, int section, 1160 struct mtd_oob_region *oobregion) 1161 { 1162 struct denali_nand_info *denali = mtd_to_denali(mtd); 1163 struct nand_chip *chip = mtd_to_nand(mtd); 1164 1165 if (section) 1166 return -ERANGE; 1167 1168 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; 1169 oobregion->length = mtd->oobsize - oobregion->offset; 1170 1171 return 0; 1172 } 1173 1174 static const struct mtd_ooblayout_ops denali_ooblayout_ops = { 1175 .ecc = denali_ooblayout_ecc, 1176 .free = denali_ooblayout_free, 1177 }; 1178 1179 static int denali_multidev_fixup(struct denali_nand_info *denali) 1180 { 1181 struct nand_chip *chip = &denali->nand; 1182 struct mtd_info *mtd = nand_to_mtd(chip); 1183 1184 /* 1185 * Support for multi device: 1186 * When the IP configuration is x16 capable and two x8 chips are 1187 * connected in parallel, DEVICES_CONNECTED should be set to 2. 1188 * In this case, the core framework knows nothing about this fact, 1189 * so we should tell it the _logical_ pagesize and anything necessary. 1190 */ 1191 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); 1192 1193 /* 1194 * On some SoCs, DEVICES_CONNECTED is not auto-detected. 1195 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. 1196 */ 1197 if (denali->devs_per_cs == 0) { 1198 denali->devs_per_cs = 1; 1199 iowrite32(1, denali->reg + DEVICES_CONNECTED); 1200 } 1201 1202 if (denali->devs_per_cs == 1) 1203 return 0; 1204 1205 if (denali->devs_per_cs != 2) { 1206 dev_err(denali->dev, "unsupported number of devices %d\n", 1207 denali->devs_per_cs); 1208 return -EINVAL; 1209 } 1210 1211 /* 2 chips in parallel */ 1212 mtd->size <<= 1; 1213 mtd->erasesize <<= 1; 1214 mtd->writesize <<= 1; 1215 mtd->oobsize <<= 1; 1216 chip->chipsize <<= 1; 1217 chip->page_shift += 1; 1218 chip->phys_erase_shift += 1; 1219 chip->bbt_erase_shift += 1; 1220 chip->chip_shift += 1; 1221 chip->pagemask <<= 1; 1222 chip->ecc.size <<= 1; 1223 chip->ecc.bytes <<= 1; 1224 chip->ecc.strength <<= 1; 1225 denali->oob_skip_bytes <<= 1; 1226 1227 return 0; 1228 } 1229 1230 int denali_init(struct denali_nand_info *denali) 1231 { 1232 struct nand_chip *chip = &denali->nand; 1233 struct mtd_info *mtd = nand_to_mtd(chip); 1234 u32 features = ioread32(denali->reg + FEATURES); 1235 int ret; 1236 1237 denali_hw_init(denali); 1238 1239 denali_clear_irq_all(denali); 1240 1241 denali_reset_banks(denali); 1242 1243 denali->active_bank = DENALI_INVALID_BANK; 1244 1245 chip->flash_node = dev_of_offset(denali->dev); 1246 /* Fallback to the default name if DT did not give "label" property */ 1247 if (!mtd->name) 1248 mtd->name = "denali-nand"; 1249 1250 chip->select_chip = denali_select_chip; 1251 chip->read_byte = denali_read_byte; 1252 chip->write_byte = denali_write_byte; 1253 chip->read_word = denali_read_word; 1254 chip->cmd_ctrl = denali_cmd_ctrl; 1255 chip->dev_ready = denali_dev_ready; 1256 chip->waitfunc = denali_waitfunc; 1257 1258 if (features & FEATURES__INDEX_ADDR) { 1259 denali->host_read = denali_indexed_read; 1260 denali->host_write = denali_indexed_write; 1261 } else { 1262 denali->host_read = denali_direct_read; 1263 denali->host_write = denali_direct_write; 1264 } 1265 1266 /* clk rate info is needed for setup_data_interface */ 1267 if (denali->clk_x_rate) 1268 chip->setup_data_interface = denali_setup_data_interface; 1269 1270 ret = nand_scan_ident(mtd, denali->max_banks, NULL); 1271 if (ret) 1272 return ret; 1273 1274 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) 1275 denali->dma_avail = 1; 1276 1277 if (denali->dma_avail) { 1278 chip->buf_align = ARCH_DMA_MINALIGN; 1279 if (denali->caps & DENALI_CAP_DMA_64BIT) 1280 denali->setup_dma = denali_setup_dma64; 1281 else 1282 denali->setup_dma = denali_setup_dma32; 1283 } else { 1284 chip->buf_align = 4; 1285 } 1286 1287 chip->options |= NAND_USE_BOUNCE_BUFFER; 1288 chip->bbt_options |= NAND_BBT_USE_FLASH; 1289 chip->bbt_options |= NAND_BBT_NO_OOB; 1290 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 1291 1292 /* no subpage writes on denali */ 1293 chip->options |= NAND_NO_SUBPAGE_WRITE; 1294 1295 ret = denali_ecc_setup(mtd, chip, denali); 1296 if (ret) { 1297 dev_err(denali->dev, "Failed to setup ECC settings.\n"); 1298 return ret; 1299 } 1300 1301 dev_dbg(denali->dev, 1302 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", 1303 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); 1304 1305 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | 1306 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), 1307 denali->reg + ECC_CORRECTION); 1308 iowrite32(mtd->erasesize / mtd->writesize, 1309 denali->reg + PAGES_PER_BLOCK); 1310 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, 1311 denali->reg + DEVICE_WIDTH); 1312 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, 1313 denali->reg + TWO_ROW_ADDR_CYCLES); 1314 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); 1315 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); 1316 1317 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); 1318 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); 1319 /* chip->ecc.steps is set by nand_scan_tail(); not available here */ 1320 iowrite32(mtd->writesize / chip->ecc.size, 1321 denali->reg + CFG_NUM_DATA_BLOCKS); 1322 1323 mtd_set_ooblayout(mtd, &denali_ooblayout_ops); 1324 1325 nand_oob.eccbytes = denali->nand.ecc.bytes; 1326 denali->nand.ecc.layout = &nand_oob; 1327 1328 if (chip->options & NAND_BUSWIDTH_16) { 1329 chip->read_buf = denali_read_buf16; 1330 chip->write_buf = denali_write_buf16; 1331 } else { 1332 chip->read_buf = denali_read_buf; 1333 chip->write_buf = denali_write_buf; 1334 } 1335 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; 1336 chip->ecc.read_page = denali_read_page; 1337 chip->ecc.read_page_raw = denali_read_page_raw; 1338 chip->ecc.write_page = denali_write_page; 1339 chip->ecc.write_page_raw = denali_write_page_raw; 1340 chip->ecc.read_oob = denali_read_oob; 1341 chip->ecc.write_oob = denali_write_oob; 1342 chip->erase = denali_erase; 1343 1344 ret = denali_multidev_fixup(denali); 1345 if (ret) 1346 return ret; 1347 1348 /* 1349 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not 1350 * use devm_kmalloc() because the memory allocated by devm_ does not 1351 * guarantee DMA-safe alignment. 1352 */ 1353 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); 1354 if (!denali->buf) 1355 return -ENOMEM; 1356 1357 ret = nand_scan_tail(mtd); 1358 if (ret) 1359 goto free_buf; 1360 1361 ret = nand_register(0, mtd); 1362 if (ret) { 1363 dev_err(denali->dev, "Failed to register MTD: %d\n", ret); 1364 goto free_buf; 1365 } 1366 return 0; 1367 1368 free_buf: 1369 kfree(denali->buf); 1370 1371 return ret; 1372 } 1373