1 2menuconfig NAND 3 bool "Raw NAND Device Support" 4if NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SYS_NAND_DRIVER_ECC_LAYOUT 13 bool 14 help 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 17 18config NAND_ATMEL 19 bool "Support Atmel NAND controller" 20 imply SYS_NAND_USE_FLASH_BBT 21 help 22 Enable this driver for NAND flash platforms using an Atmel NAND 23 controller. 24 25if NAND_ATMEL 26 27config ATMEL_NAND_HWECC 28 bool "Atmel Hardware ECC" 29 default n 30 31config ATMEL_NAND_HW_PMECC 32 bool "Atmel Programmable Multibit ECC (PMECC)" 33 select ATMEL_NAND_HWECC 34 default n 35 help 36 The Programmable Multibit ECC (PMECC) controller is a programmable 37 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. 38 39config PMECC_CAP 40 int "PMECC Correctable ECC Bits" 41 depends on ATMEL_NAND_HW_PMECC 42 default 2 43 help 44 Correctable ECC bits, can be 2, 4, 8, 12, and 24. 45 46config PMECC_SECTOR_SIZE 47 int "PMECC Sector Size" 48 depends on ATMEL_NAND_HW_PMECC 49 default 512 50 help 51 Sector size, in bytes, can be 512 or 1024. 52 53config SPL_GENERATE_ATMEL_PMECC_HEADER 54 bool "Atmel PMECC Header Generation" 55 select ATMEL_NAND_HWECC 56 select ATMEL_NAND_HW_PMECC 57 default n 58 help 59 Generate Programmable Multibit ECC (PMECC) header for SPL image. 60 61endif 62 63config NAND_DAVINCI 64 bool "Support TI Davinci NAND controller" 65 help 66 Enable this driver for NAND flash controllers available in TI Davinci 67 and Keystone2 platforms 68 69config NAND_DENALI 70 bool 71 select SYS_NAND_SELF_INIT 72 imply CMD_NAND 73 74config NAND_DENALI_DT 75 bool "Support Denali NAND controller as a DT device" 76 select NAND_DENALI 77 depends on OF_CONTROL && DM 78 help 79 Enable the driver for NAND flash on platforms using a Denali NAND 80 controller as a DT device. 81 82config NAND_DENALI_SPARE_AREA_SKIP_BYTES 83 int "Number of bytes skipped in OOB area" 84 depends on NAND_DENALI 85 range 0 63 86 help 87 This option specifies the number of bytes to skip from the beginning 88 of OOB area before last ECC sector data starts. This is potentially 89 used to preserve the bad block marker in the OOB area. 90 91config NAND_LPC32XX_SLC 92 bool "Support LPC32XX_SLC controller" 93 help 94 Enable the LPC32XX SLC NAND controller. 95 96config NAND_OMAP_GPMC 97 bool "Support OMAP GPMC NAND controller" 98 depends on ARCH_OMAP2PLUS 99 help 100 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 101 GPMC controller is used for parallel NAND flash devices, and can 102 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 103 and BCH16 ECC algorithms. 104 105config NAND_OMAP_GPMC_PREFETCH 106 bool "Enable GPMC Prefetch" 107 depends on NAND_OMAP_GPMC 108 default y 109 help 110 On OMAP platforms that use the GPMC controller 111 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 112 uses the prefetch mode to speed up read operations. 113 114config NAND_OMAP_ELM 115 bool "Enable ELM driver for OMAPxx and AMxx platforms." 116 depends on NAND_OMAP_GPMC && !OMAP34XX 117 help 118 ELM controller is used for ECC error detection (not ECC calculation) 119 of BCH4, BCH8 and BCH16 ECC algorithms. 120 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 121 thus such SoC platforms need to depend on software library for ECC error 122 detection. However ECC calculation on such plaforms would still be 123 done by GPMC controller. 124 125config NAND_VF610_NFC 126 bool "Support for Freescale NFC for VF610" 127 select SYS_NAND_SELF_INIT 128 select SYS_NAND_DRIVER_ECC_LAYOUT 129 imply CMD_NAND 130 help 131 Enables support for NAND Flash Controller on some Freescale 132 processors like the VF610, MCF54418 or Kinetis K70. 133 The driver supports a maximum 2k page size. The driver 134 currently does not support hardware ECC. 135 136if NAND_VF610_NFC 137 138config NAND_VF610_NFC_DT 139 bool "Support Vybrid's vf610 NAND controller as a DT device" 140 depends on OF_CONTROL && MTD 141 help 142 Enable the driver for Vybrid's vf610 NAND flash on platforms 143 using device tree. 144 145choice 146 prompt "Hardware ECC strength" 147 depends on NAND_VF610_NFC 148 default SYS_NAND_VF610_NFC_45_ECC_BYTES 149 help 150 Select the ECC strength used in the hardware BCH ECC block. 151 152config SYS_NAND_VF610_NFC_45_ECC_BYTES 153 bool "24-error correction (45 ECC bytes)" 154 155config SYS_NAND_VF610_NFC_60_ECC_BYTES 156 bool "32-error correction (60 ECC bytes)" 157 158endchoice 159 160endif 161 162config NAND_PXA3XX 163 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 164 select SYS_NAND_SELF_INIT 165 imply CMD_NAND 166 help 167 This enables the driver for the NAND flash device found on 168 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 169 170config NAND_SUNXI 171 bool "Support for NAND on Allwinner SoCs" 172 default ARCH_SUNXI 173 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 174 select SYS_NAND_SELF_INIT 175 select SYS_NAND_U_BOOT_LOCATIONS 176 select SPL_NAND_SUPPORT 177 imply CMD_NAND 178 ---help--- 179 Enable support for NAND. This option enables the standard and 180 SPL drivers. 181 The SPL driver only supports reading from the NAND using DMA 182 transfers. 183 184if NAND_SUNXI 185 186config NAND_SUNXI_SPL_ECC_STRENGTH 187 int "Allwinner NAND SPL ECC Strength" 188 default 64 189 190config NAND_SUNXI_SPL_ECC_SIZE 191 int "Allwinner NAND SPL ECC Step Size" 192 default 1024 193 194config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 195 int "Allwinner NAND SPL Usable Page Size" 196 default 1024 197 198endif 199 200config NAND_ARASAN 201 bool "Configure Arasan Nand" 202 select SYS_NAND_SELF_INIT 203 imply CMD_NAND 204 help 205 This enables Nand driver support for Arasan nand flash 206 controller. This uses the hardware ECC for read and 207 write operations. 208 209config NAND_MXC 210 bool "MXC NAND support" 211 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 212 imply CMD_NAND 213 help 214 This enables the NAND driver for the NAND flash controller on the 215 i.MX27 / i.MX31 / i.MX5 rocessors. 216 217config NAND_MXS 218 bool "MXS NAND support" 219 depends on MX23 || MX28 || MX6 || MX7 220 select SYS_NAND_SELF_INIT 221 imply CMD_NAND 222 select APBH_DMA 223 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 224 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 225 help 226 This enables NAND driver for the NAND flash controller on the 227 MXS processors. 228 229if NAND_MXS 230 231config NAND_MXS_DT 232 bool "Support MXS NAND controller as a DT device" 233 depends on OF_CONTROL && MTD 234 help 235 Enable the driver for MXS NAND flash on platforms using 236 device tree. 237 238config NAND_MXS_USE_MINIMUM_ECC 239 bool "Use minimum ECC strength supported by the controller" 240 default false 241 242endif 243 244config NAND_ZYNQ 245 bool "Support for Zynq Nand controller" 246 select SYS_NAND_SELF_INIT 247 imply CMD_NAND 248 help 249 This enables Nand driver support for Nand flash controller 250 found on Zynq SoC. 251 252config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 253 bool "Enable use of 1st stage bootloader timing for NAND" 254 depends on NAND_ZYNQ 255 help 256 This flag prevent U-boot reconfigure NAND flash controller and reuse 257 the NAND timing from 1st stage bootloader. 258 259config NAND_STM32_FMC2 260 bool "Support for NAND controller on STM32MP SoCs" 261 depends on ARCH_STM32MP 262 select SYS_NAND_SELF_INIT 263 imply CMD_NAND 264 help 265 Enables support for NAND Flash chips on SoCs containing the FMC2 266 NAND controller. This controller is found on STM32MP SoCs. 267 The controller supports a maximum 8k page size and supports 268 a maximum 8-bit correction error per sector of 512 bytes. 269 270comment "Generic NAND options" 271 272config SYS_NAND_BLOCK_SIZE 273 hex "NAND chip eraseblock size" 274 depends on ARCH_SUNXI 275 help 276 Number of data bytes in one eraseblock for the NAND chip on the 277 board. This is the multiple of NAND_PAGE_SIZE and the number of 278 pages. 279 280config SYS_NAND_PAGE_SIZE 281 hex "NAND chip page size" 282 depends on ARCH_SUNXI 283 help 284 Number of data bytes in one page for the NAND chip on the 285 board, not including the OOB area. 286 287config SYS_NAND_OOBSIZE 288 hex "NAND chip OOB size" 289 depends on ARCH_SUNXI 290 help 291 Number of bytes in the Out-Of-Band area for the NAND chip on 292 the board. 293 294# Enhance depends when converting drivers to Kconfig which use this config 295# option (mxc_nand, ndfc, omap_gpmc). 296config SYS_NAND_BUSWIDTH_16BIT 297 bool "Use 16-bit NAND interface" 298 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 299 help 300 Indicates that NAND device has 16-bit wide data-bus. In absence of this 301 config, bus-width of NAND device is assumed to be either 8-bit and later 302 determined by reading ONFI params. 303 Above config is useful when NAND device's bus-width information cannot 304 be determined from on-chip ONFI params, like in following scenarios: 305 - SPL boot does not support reading of ONFI parameters. This is done to 306 keep SPL code foot-print small. 307 - In current U-Boot flow using nand_init(), driver initialization 308 happens in board_nand_init() which is called before any device probe 309 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 310 not available while configuring controller. So a static CONFIG_NAND_xx 311 is needed to know the device's bus-width in advance. 312 313config SYS_NAND_MAX_CHIPS 314 int "NAND max chips" 315 default 1 316 depends on NAND_ARASAN 317 help 318 The maximum number of NAND chips per device to be supported. 319 320if SPL 321 322config SYS_NAND_U_BOOT_LOCATIONS 323 bool "Define U-boot binaries locations in NAND" 324 help 325 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 326 This option should not be enabled when compiling U-boot for boards 327 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 328 file. 329 330config SYS_NAND_U_BOOT_OFFS 331 hex "Location in NAND to read U-Boot from" 332 default 0x800000 if NAND_SUNXI 333 depends on SYS_NAND_U_BOOT_LOCATIONS 334 help 335 Set the offset from the start of the nand where u-boot should be 336 loaded from. 337 338config SYS_NAND_U_BOOT_OFFS_REDUND 339 hex "Location in NAND to read U-Boot from" 340 default SYS_NAND_U_BOOT_OFFS 341 depends on SYS_NAND_U_BOOT_LOCATIONS 342 help 343 Set the offset from the start of the nand where the redundant u-boot 344 should be loaded from. 345 346config SPL_NAND_AM33XX_BCH 347 bool "Enables SPL-NAND driver which supports ELM based" 348 depends on NAND_OMAP_GPMC && !OMAP34XX 349 default y 350 help 351 Hardware ECC correction. This is useful for platforms which have ELM 352 hardware engine and use NAND boot mode. 353 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 354 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 355 SPL-NAND driver with software ECC correction support. 356 357config SPL_NAND_DENALI 358 bool "Support Denali NAND controller for SPL" 359 help 360 This is a small implementation of the Denali NAND controller 361 for use on SPL. 362 363config SPL_NAND_SIMPLE 364 bool "Use simple SPL NAND driver" 365 depends on !SPL_NAND_AM33XX_BCH 366 help 367 Support for NAND boot using simple NAND drivers that 368 expose the cmd_ctrl() interface. 369endif 370 371endif # if NAND 372