1 2menuconfig NAND 3 bool "Raw NAND Device Support" 4if NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SYS_NAND_DRIVER_ECC_LAYOUT 13 bool 14 help 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 17 18config NAND_ATMEL 19 bool "Support Atmel NAND controller" 20 imply SYS_NAND_USE_FLASH_BBT 21 help 22 Enable this driver for NAND flash platforms using an Atmel NAND 23 controller. 24 25if NAND_ATMEL 26 27config ATMEL_NAND_HWECC 28 bool "Atmel Hardware ECC" 29 default n 30 31config ATMEL_NAND_HW_PMECC 32 bool "Atmel Programmable Multibit ECC (PMECC)" 33 select ATMEL_NAND_HWECC 34 default n 35 help 36 The Programmable Multibit ECC (PMECC) controller is a programmable 37 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. 38 39config PMECC_CAP 40 int "PMECC Correctable ECC Bits" 41 depends on ATMEL_NAND_HW_PMECC 42 default 2 43 help 44 Correctable ECC bits, can be 2, 4, 8, 12, and 24. 45 46config PMECC_SECTOR_SIZE 47 int "PMECC Sector Size" 48 depends on ATMEL_NAND_HW_PMECC 49 default 512 50 help 51 Sector size, in bytes, can be 512 or 1024. 52 53config SPL_GENERATE_ATMEL_PMECC_HEADER 54 bool "Atmel PMECC Header Generation" 55 select ATMEL_NAND_HWECC 56 select ATMEL_NAND_HW_PMECC 57 default n 58 help 59 Generate Programmable Multibit ECC (PMECC) header for SPL image. 60 61endif 62 63config NAND_BRCMNAND 64 bool "Support Broadcom NAND controller" 65 depends on OF_CONTROL && DM && MTD 66 help 67 Enable the driver for NAND flash on platforms using a Broadcom NAND 68 controller. 69 70config NAND_BRCMNAND_6838 71 bool "Support Broadcom NAND controller on bcm6838" 72 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 73 help 74 Enable support for broadcom nand driver on bcm6838. 75 76config NAND_BRCMNAND_6858 77 bool "Support Broadcom NAND controller on bcm6858" 78 depends on NAND_BRCMNAND && ARCH_BCM6858 79 help 80 Enable support for broadcom nand driver on bcm6858. 81 82config NAND_BRCMNAND_63158 83 bool "Support Broadcom NAND controller on bcm63158" 84 depends on NAND_BRCMNAND && ARCH_BCM63158 85 help 86 Enable support for broadcom nand driver on bcm63158. 87 88config NAND_DAVINCI 89 bool "Support TI Davinci NAND controller" 90 help 91 Enable this driver for NAND flash controllers available in TI Davinci 92 and Keystone2 platforms 93 94config NAND_DENALI 95 bool 96 select SYS_NAND_SELF_INIT 97 imply CMD_NAND 98 99config NAND_DENALI_DT 100 bool "Support Denali NAND controller as a DT device" 101 select NAND_DENALI 102 depends on OF_CONTROL && DM 103 help 104 Enable the driver for NAND flash on platforms using a Denali NAND 105 controller as a DT device. 106 107config NAND_DENALI_SPARE_AREA_SKIP_BYTES 108 int "Number of bytes skipped in OOB area" 109 depends on NAND_DENALI 110 range 0 63 111 help 112 This option specifies the number of bytes to skip from the beginning 113 of OOB area before last ECC sector data starts. This is potentially 114 used to preserve the bad block marker in the OOB area. 115 116config NAND_LPC32XX_SLC 117 bool "Support LPC32XX_SLC controller" 118 help 119 Enable the LPC32XX SLC NAND controller. 120 121config NAND_OMAP_GPMC 122 bool "Support OMAP GPMC NAND controller" 123 depends on ARCH_OMAP2PLUS 124 help 125 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 126 GPMC controller is used for parallel NAND flash devices, and can 127 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 128 and BCH16 ECC algorithms. 129 130config NAND_OMAP_GPMC_PREFETCH 131 bool "Enable GPMC Prefetch" 132 depends on NAND_OMAP_GPMC 133 default y 134 help 135 On OMAP platforms that use the GPMC controller 136 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 137 uses the prefetch mode to speed up read operations. 138 139config NAND_OMAP_ELM 140 bool "Enable ELM driver for OMAPxx and AMxx platforms." 141 depends on NAND_OMAP_GPMC && !OMAP34XX 142 help 143 ELM controller is used for ECC error detection (not ECC calculation) 144 of BCH4, BCH8 and BCH16 ECC algorithms. 145 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 146 thus such SoC platforms need to depend on software library for ECC error 147 detection. However ECC calculation on such plaforms would still be 148 done by GPMC controller. 149 150config NAND_VF610_NFC 151 bool "Support for Freescale NFC for VF610" 152 select SYS_NAND_SELF_INIT 153 select SYS_NAND_DRIVER_ECC_LAYOUT 154 imply CMD_NAND 155 help 156 Enables support for NAND Flash Controller on some Freescale 157 processors like the VF610, MCF54418 or Kinetis K70. 158 The driver supports a maximum 2k page size. The driver 159 currently does not support hardware ECC. 160 161if NAND_VF610_NFC 162 163config NAND_VF610_NFC_DT 164 bool "Support Vybrid's vf610 NAND controller as a DT device" 165 depends on OF_CONTROL && MTD 166 help 167 Enable the driver for Vybrid's vf610 NAND flash on platforms 168 using device tree. 169 170choice 171 prompt "Hardware ECC strength" 172 depends on NAND_VF610_NFC 173 default SYS_NAND_VF610_NFC_45_ECC_BYTES 174 help 175 Select the ECC strength used in the hardware BCH ECC block. 176 177config SYS_NAND_VF610_NFC_45_ECC_BYTES 178 bool "24-error correction (45 ECC bytes)" 179 180config SYS_NAND_VF610_NFC_60_ECC_BYTES 181 bool "32-error correction (60 ECC bytes)" 182 183endchoice 184 185endif 186 187config NAND_PXA3XX 188 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 189 select SYS_NAND_SELF_INIT 190 imply CMD_NAND 191 help 192 This enables the driver for the NAND flash device found on 193 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 194 195config NAND_SUNXI 196 bool "Support for NAND on Allwinner SoCs" 197 default ARCH_SUNXI 198 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 199 select SYS_NAND_SELF_INIT 200 select SYS_NAND_U_BOOT_LOCATIONS 201 select SPL_NAND_SUPPORT 202 imply CMD_NAND 203 ---help--- 204 Enable support for NAND. This option enables the standard and 205 SPL drivers. 206 The SPL driver only supports reading from the NAND using DMA 207 transfers. 208 209if NAND_SUNXI 210 211config NAND_SUNXI_SPL_ECC_STRENGTH 212 int "Allwinner NAND SPL ECC Strength" 213 default 64 214 215config NAND_SUNXI_SPL_ECC_SIZE 216 int "Allwinner NAND SPL ECC Step Size" 217 default 1024 218 219config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 220 int "Allwinner NAND SPL Usable Page Size" 221 default 1024 222 223endif 224 225config NAND_ARASAN 226 bool "Configure Arasan Nand" 227 select SYS_NAND_SELF_INIT 228 imply CMD_NAND 229 help 230 This enables Nand driver support for Arasan nand flash 231 controller. This uses the hardware ECC for read and 232 write operations. 233 234config NAND_MXC 235 bool "MXC NAND support" 236 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 237 imply CMD_NAND 238 help 239 This enables the NAND driver for the NAND flash controller on the 240 i.MX27 / i.MX31 / i.MX5 rocessors. 241 242config NAND_MXS 243 bool "MXS NAND support" 244 depends on MX23 || MX28 || MX6 || MX7 245 select SYS_NAND_SELF_INIT 246 imply CMD_NAND 247 select APBH_DMA 248 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 249 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 250 help 251 This enables NAND driver for the NAND flash controller on the 252 MXS processors. 253 254if NAND_MXS 255 256config NAND_MXS_DT 257 bool "Support MXS NAND controller as a DT device" 258 depends on OF_CONTROL && MTD 259 help 260 Enable the driver for MXS NAND flash on platforms using 261 device tree. 262 263config NAND_MXS_USE_MINIMUM_ECC 264 bool "Use minimum ECC strength supported by the controller" 265 default false 266 267endif 268 269config NAND_ZYNQ 270 bool "Support for Zynq Nand controller" 271 select SYS_NAND_SELF_INIT 272 imply CMD_NAND 273 help 274 This enables Nand driver support for Nand flash controller 275 found on Zynq SoC. 276 277config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 278 bool "Enable use of 1st stage bootloader timing for NAND" 279 depends on NAND_ZYNQ 280 help 281 This flag prevent U-boot reconfigure NAND flash controller and reuse 282 the NAND timing from 1st stage bootloader. 283 284config NAND_STM32_FMC2 285 bool "Support for NAND controller on STM32MP SoCs" 286 depends on ARCH_STM32MP 287 select SYS_NAND_SELF_INIT 288 imply CMD_NAND 289 help 290 Enables support for NAND Flash chips on SoCs containing the FMC2 291 NAND controller. This controller is found on STM32MP SoCs. 292 The controller supports a maximum 8k page size and supports 293 a maximum 8-bit correction error per sector of 512 bytes. 294 295comment "Generic NAND options" 296 297config SYS_NAND_BLOCK_SIZE 298 hex "NAND chip eraseblock size" 299 depends on ARCH_SUNXI 300 help 301 Number of data bytes in one eraseblock for the NAND chip on the 302 board. This is the multiple of NAND_PAGE_SIZE and the number of 303 pages. 304 305config SYS_NAND_PAGE_SIZE 306 hex "NAND chip page size" 307 depends on ARCH_SUNXI 308 help 309 Number of data bytes in one page for the NAND chip on the 310 board, not including the OOB area. 311 312config SYS_NAND_OOBSIZE 313 hex "NAND chip OOB size" 314 depends on ARCH_SUNXI 315 help 316 Number of bytes in the Out-Of-Band area for the NAND chip on 317 the board. 318 319# Enhance depends when converting drivers to Kconfig which use this config 320# option (mxc_nand, ndfc, omap_gpmc). 321config SYS_NAND_BUSWIDTH_16BIT 322 bool "Use 16-bit NAND interface" 323 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 324 help 325 Indicates that NAND device has 16-bit wide data-bus. In absence of this 326 config, bus-width of NAND device is assumed to be either 8-bit and later 327 determined by reading ONFI params. 328 Above config is useful when NAND device's bus-width information cannot 329 be determined from on-chip ONFI params, like in following scenarios: 330 - SPL boot does not support reading of ONFI parameters. This is done to 331 keep SPL code foot-print small. 332 - In current U-Boot flow using nand_init(), driver initialization 333 happens in board_nand_init() which is called before any device probe 334 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 335 not available while configuring controller. So a static CONFIG_NAND_xx 336 is needed to know the device's bus-width in advance. 337 338config SYS_NAND_MAX_CHIPS 339 int "NAND max chips" 340 default 1 341 depends on NAND_ARASAN 342 help 343 The maximum number of NAND chips per device to be supported. 344 345if SPL 346 347config SYS_NAND_U_BOOT_LOCATIONS 348 bool "Define U-boot binaries locations in NAND" 349 help 350 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 351 This option should not be enabled when compiling U-boot for boards 352 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 353 file. 354 355config SYS_NAND_U_BOOT_OFFS 356 hex "Location in NAND to read U-Boot from" 357 default 0x800000 if NAND_SUNXI 358 depends on SYS_NAND_U_BOOT_LOCATIONS 359 help 360 Set the offset from the start of the nand where u-boot should be 361 loaded from. 362 363config SYS_NAND_U_BOOT_OFFS_REDUND 364 hex "Location in NAND to read U-Boot from" 365 default SYS_NAND_U_BOOT_OFFS 366 depends on SYS_NAND_U_BOOT_LOCATIONS 367 help 368 Set the offset from the start of the nand where the redundant u-boot 369 should be loaded from. 370 371config SPL_NAND_AM33XX_BCH 372 bool "Enables SPL-NAND driver which supports ELM based" 373 depends on NAND_OMAP_GPMC && !OMAP34XX 374 default y 375 help 376 Hardware ECC correction. This is useful for platforms which have ELM 377 hardware engine and use NAND boot mode. 378 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 379 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 380 SPL-NAND driver with software ECC correction support. 381 382config SPL_NAND_DENALI 383 bool "Support Denali NAND controller for SPL" 384 help 385 This is a small implementation of the Denali NAND controller 386 for use on SPL. 387 388config SPL_NAND_SIMPLE 389 bool "Use simple SPL NAND driver" 390 depends on !SPL_NAND_AM33XX_BCH 391 help 392 Support for NAND boot using simple NAND drivers that 393 expose the cmd_ctrl() interface. 394endif 395 396endif # if NAND 397