1 2menuconfig NAND 3 bool "NAND Device Support" 4if NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config NAND_DENALI 13 bool 14 select SYS_NAND_SELF_INIT 15 imply CMD_NAND 16 17config NAND_DENALI_DT 18 bool "Support Denali NAND controller as a DT device" 19 select NAND_DENALI 20 depends on OF_CONTROL && DM 21 help 22 Enable the driver for NAND flash on platforms using a Denali NAND 23 controller as a DT device. 24 25config NAND_DENALI_SPARE_AREA_SKIP_BYTES 26 int "Number of bytes skipped in OOB area" 27 depends on NAND_DENALI 28 range 0 63 29 help 30 This option specifies the number of bytes to skip from the beginning 31 of OOB area before last ECC sector data starts. This is potentially 32 used to preserve the bad block marker in the OOB area. 33 34config NAND_LPC32XX_SLC 35 bool "Support LPC32XX_SLC controller" 36 help 37 Enable the LPC32XX SLC NAND controller. 38 39config NAND_OMAP_GPMC 40 bool "Support OMAP GPMC NAND controller" 41 depends on ARCH_OMAP2PLUS 42 help 43 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 44 GPMC controller is used for parallel NAND flash devices, and can 45 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 46 and BCH16 ECC algorithms. 47 48config NAND_OMAP_GPMC_PREFETCH 49 bool "Enable GPMC Prefetch" 50 depends on NAND_OMAP_GPMC 51 default y 52 help 53 On OMAP platforms that use the GPMC controller 54 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 55 uses the prefetch mode to speed up read operations. 56 57config NAND_OMAP_ELM 58 bool "Enable ELM driver for OMAPxx and AMxx platforms." 59 depends on NAND_OMAP_GPMC && !OMAP34XX 60 help 61 ELM controller is used for ECC error detection (not ECC calculation) 62 of BCH4, BCH8 and BCH16 ECC algorithms. 63 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 64 thus such SoC platforms need to depend on software library for ECC error 65 detection. However ECC calculation on such plaforms would still be 66 done by GPMC controller. 67 68config NAND_VF610_NFC 69 bool "Support for Freescale NFC for VF610" 70 select SYS_NAND_SELF_INIT 71 imply CMD_NAND 72 help 73 Enables support for NAND Flash Controller on some Freescale 74 processors like the VF610, MCF54418 or Kinetis K70. 75 The driver supports a maximum 2k page size. The driver 76 currently does not support hardware ECC. 77 78choice 79 prompt "Hardware ECC strength" 80 depends on NAND_VF610_NFC 81 default SYS_NAND_VF610_NFC_45_ECC_BYTES 82 help 83 Select the ECC strength used in the hardware BCH ECC block. 84 85config SYS_NAND_VF610_NFC_45_ECC_BYTES 86 bool "24-error correction (45 ECC bytes)" 87 88config SYS_NAND_VF610_NFC_60_ECC_BYTES 89 bool "32-error correction (60 ECC bytes)" 90 91endchoice 92 93config NAND_PXA3XX 94 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 95 select SYS_NAND_SELF_INIT 96 imply CMD_NAND 97 help 98 This enables the driver for the NAND flash device found on 99 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 100 101config NAND_ROCKCHIP 102 bool "Support for NAND on Rockchip SoCs" 103 select SYS_NAND_SELF_INIT 104 default n 105 ---help--- 106 Enable support for Rockchip nand. 107 108config NAND_ROCKCHIP_V9 109 bool "Support for NAND V9 on Rockchip SoCs" 110 select SYS_NAND_SELF_INIT 111 default n 112 ---help--- 113 Enable support for Rockchip nand v9. 114 115if NAND_ROCKCHIP || NAND_ROCKCHIP_V9 116config NAND_ROCKCHIP_DT 117 bool "Support Rockchip NAND controller as a DT device" 118 default y 119 help 120 Enable the driver for Rockchip NAND flash on platforms 121 using device tree. 122endif 123 124config NAND_SUNXI 125 bool "Support for NAND on Allwinner SoCs" 126 default ARCH_SUNXI 127 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 128 select SYS_NAND_SELF_INIT 129 select SYS_NAND_U_BOOT_LOCATIONS 130 select SPL_NAND_SUPPORT 131 imply CMD_NAND 132 ---help--- 133 Enable support for NAND. This option enables the standard and 134 SPL drivers. 135 The SPL driver only supports reading from the NAND using DMA 136 transfers. 137 138if NAND_SUNXI 139 140config NAND_SUNXI_SPL_ECC_STRENGTH 141 int "Allwinner NAND SPL ECC Strength" 142 default 64 143 144config NAND_SUNXI_SPL_ECC_SIZE 145 int "Allwinner NAND SPL ECC Step Size" 146 default 1024 147 148config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 149 int "Allwinner NAND SPL Usable Page Size" 150 default 1024 151 152endif 153 154config NAND_ARASAN 155 bool "Configure Arasan Nand" 156 select SYS_NAND_SELF_INIT 157 imply CMD_NAND 158 help 159 This enables Nand driver support for Arasan nand flash 160 controller. This uses the hardware ECC for read and 161 write operations. 162 163config NAND_MXC 164 bool "MXC NAND support" 165 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 166 imply CMD_NAND 167 help 168 This enables the NAND driver for the NAND flash controller on the 169 i.MX27 / i.MX31 / i.MX5 rocessors. 170 171config NAND_MXS 172 bool "MXS NAND support" 173 depends on MX23 || MX28 || MX6 || MX7 174 select SYS_NAND_SELF_INIT 175 imply CMD_NAND 176 select APBH_DMA 177 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 178 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 179 help 180 This enables NAND driver for the NAND flash controller on the 181 MXS processors. 182 183if NAND_MXS 184 185config NAND_MXS_DT 186 bool "Support MXS NAND controller as a DT device" 187 depends on OF_CONTROL && MTD 188 help 189 Enable the driver for MXS NAND flash on platforms using 190 device tree. 191 192config NAND_MXS_USE_MINIMUM_ECC 193 bool "Use minimum ECC strength supported by the controller" 194 default false 195 196endif 197 198config NAND_ZYNQ 199 bool "Support for Zynq Nand controller" 200 select SYS_NAND_SELF_INIT 201 imply CMD_NAND 202 help 203 This enables Nand driver support for Nand flash controller 204 found on Zynq SoC. 205 206config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 207 bool "Enable use of 1st stage bootloader timing for NAND" 208 depends on NAND_ZYNQ 209 help 210 This flag prevent U-boot reconfigure NAND flash controller and reuse 211 the NAND timing from 1st stage bootloader. 212 213comment "Generic NAND options" 214 215config SYS_NAND_BLOCK_SIZE 216 hex "NAND chip eraseblock size" 217 depends on ARCH_SUNXI 218 help 219 Number of data bytes in one eraseblock for the NAND chip on the 220 board. This is the multiple of NAND_PAGE_SIZE and the number of 221 pages. 222 223config SYS_NAND_PAGE_SIZE 224 hex "NAND chip page size" 225 depends on ARCH_SUNXI 226 help 227 Number of data bytes in one page for the NAND chip on the 228 board, not including the OOB area. 229 230config SYS_NAND_OOBSIZE 231 hex "NAND chip OOB size" 232 depends on ARCH_SUNXI 233 help 234 Number of bytes in the Out-Of-Band area for the NAND chip on 235 the board. 236 237# Enhance depends when converting drivers to Kconfig which use this config 238# option (mxc_nand, ndfc, omap_gpmc). 239config SYS_NAND_BUSWIDTH_16BIT 240 bool "Use 16-bit NAND interface" 241 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 242 help 243 Indicates that NAND device has 16-bit wide data-bus. In absence of this 244 config, bus-width of NAND device is assumed to be either 8-bit and later 245 determined by reading ONFI params. 246 Above config is useful when NAND device's bus-width information cannot 247 be determined from on-chip ONFI params, like in following scenarios: 248 - SPL boot does not support reading of ONFI parameters. This is done to 249 keep SPL code foot-print small. 250 - In current U-Boot flow using nand_init(), driver initialization 251 happens in board_nand_init() which is called before any device probe 252 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 253 not available while configuring controller. So a static CONFIG_NAND_xx 254 is needed to know the device's bus-width in advance. 255 256if SPL 257 258config SYS_NAND_U_BOOT_LOCATIONS 259 bool "Define U-boot binaries locations in NAND" 260 help 261 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 262 This option should not be enabled when compiling U-boot for boards 263 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 264 file. 265 266config SYS_NAND_U_BOOT_OFFS 267 hex "Location in NAND to read U-Boot from" 268 default 0x800000 if NAND_SUNXI 269 depends on SYS_NAND_U_BOOT_LOCATIONS 270 help 271 Set the offset from the start of the nand where u-boot should be 272 loaded from. 273 274config SYS_NAND_U_BOOT_OFFS_REDUND 275 hex "Location in NAND to read U-Boot from" 276 default SYS_NAND_U_BOOT_OFFS 277 depends on SYS_NAND_U_BOOT_LOCATIONS 278 help 279 Set the offset from the start of the nand where the redundant u-boot 280 should be loaded from. 281 282config SPL_NAND_AM33XX_BCH 283 bool "Enables SPL-NAND driver which supports ELM based" 284 depends on NAND_OMAP_GPMC && !OMAP34XX 285 default y 286 help 287 Hardware ECC correction. This is useful for platforms which have ELM 288 hardware engine and use NAND boot mode. 289 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 290 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 291 SPL-NAND driver with software ECC correction support. 292 293config SPL_NAND_DENALI 294 bool "Support Denali NAND controller for SPL" 295 help 296 This is a small implementation of the Denali NAND controller 297 for use on SPL. 298 299config SPL_NAND_SIMPLE 300 bool "Use simple SPL NAND driver" 301 depends on !SPL_NAND_AM33XX_BCH 302 help 303 Support for NAND boot using simple NAND drivers that 304 expose the cmd_ctrl() interface. 305endif 306 307endif # if NAND 308