1 /* 2 * (C) Copyright 2002-2004 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com 4 * 5 * Copyright (C) 2003 Arabella Software Ltd. 6 * Yuli Barcohen <yuli@arabellasw.com> 7 * 8 * Copyright (C) 2004 9 * Ed Okerson 10 * 11 * Copyright (C) 2006 12 * Tolunay Orkun <listmember@orkun.us> 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 * 32 */ 33 34 /* The DEBUG define must be before common to enable debugging */ 35 /* #define DEBUG */ 36 37 #include <common.h> 38 #include <asm/processor.h> 39 #include <asm/io.h> 40 #include <asm/byteorder.h> 41 #include <environment.h> 42 43 /* 44 * This file implements a Common Flash Interface (CFI) driver for 45 * U-Boot. 46 * 47 * The width of the port and the width of the chips are determined at 48 * initialization. These widths are used to calculate the address for 49 * access CFI data structures. 50 * 51 * References 52 * JEDEC Standard JESD68 - Common Flash Interface (CFI) 53 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes 54 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets 55 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet 56 * AMD CFI Specification, Release 2.0 December 1, 2001 57 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte 58 * Device IDs, Publication Number 25538 Revision A, November 8, 2001 59 * 60 * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between 61 * reading and writing ... (yes there is such a Hardware). 62 */ 63 64 #ifndef CFG_FLASH_BANKS_LIST 65 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } 66 #endif 67 68 #define FLASH_CMD_CFI 0x98 69 #define FLASH_CMD_READ_ID 0x90 70 #define FLASH_CMD_RESET 0xff 71 #define FLASH_CMD_BLOCK_ERASE 0x20 72 #define FLASH_CMD_ERASE_CONFIRM 0xD0 73 #define FLASH_CMD_WRITE 0x40 74 #define FLASH_CMD_PROTECT 0x60 75 #define FLASH_CMD_PROTECT_SET 0x01 76 #define FLASH_CMD_PROTECT_CLEAR 0xD0 77 #define FLASH_CMD_CLEAR_STATUS 0x50 78 #define FLASH_CMD_READ_STATUS 0x70 79 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 80 #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 81 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 82 83 #define FLASH_STATUS_DONE 0x80 84 #define FLASH_STATUS_ESS 0x40 85 #define FLASH_STATUS_ECLBS 0x20 86 #define FLASH_STATUS_PSLBS 0x10 87 #define FLASH_STATUS_VPENS 0x08 88 #define FLASH_STATUS_PSS 0x04 89 #define FLASH_STATUS_DPS 0x02 90 #define FLASH_STATUS_R 0x01 91 #define FLASH_STATUS_PROTECT 0x01 92 93 #define AMD_CMD_RESET 0xF0 94 #define AMD_CMD_WRITE 0xA0 95 #define AMD_CMD_ERASE_START 0x80 96 #define AMD_CMD_ERASE_SECTOR 0x30 97 #define AMD_CMD_UNLOCK_START 0xAA 98 #define AMD_CMD_UNLOCK_ACK 0x55 99 #define AMD_CMD_WRITE_TO_BUFFER 0x25 100 #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 101 102 #define AMD_STATUS_TOGGLE 0x40 103 #define AMD_STATUS_ERROR 0x20 104 105 #define ATM_CMD_UNLOCK_SECT 0x70 106 #define ATM_CMD_SOFTLOCK_START 0x80 107 #define ATM_CMD_LOCK_SECT 0x40 108 109 #define FLASH_OFFSET_MANUFACTURER_ID 0x00 110 #define FLASH_OFFSET_DEVICE_ID 0x01 111 #define FLASH_OFFSET_DEVICE_ID2 0x0E 112 #define FLASH_OFFSET_DEVICE_ID3 0x0F 113 #define FLASH_OFFSET_CFI 0x55 114 #define FLASH_OFFSET_CFI_ALT 0x555 115 #define FLASH_OFFSET_CFI_RESP 0x10 116 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 117 /* extended query table primary address */ 118 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 119 #define FLASH_OFFSET_WTOUT 0x1F 120 #define FLASH_OFFSET_WBTOUT 0x20 121 #define FLASH_OFFSET_ETOUT 0x21 122 #define FLASH_OFFSET_CETOUT 0x22 123 #define FLASH_OFFSET_WMAX_TOUT 0x23 124 #define FLASH_OFFSET_WBMAX_TOUT 0x24 125 #define FLASH_OFFSET_EMAX_TOUT 0x25 126 #define FLASH_OFFSET_CEMAX_TOUT 0x26 127 #define FLASH_OFFSET_SIZE 0x27 128 #define FLASH_OFFSET_INTERFACE 0x28 129 #define FLASH_OFFSET_BUFFER_SIZE 0x2A 130 #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C 131 #define FLASH_OFFSET_ERASE_REGIONS 0x2D 132 #define FLASH_OFFSET_PROTECT 0x02 133 #define FLASH_OFFSET_USER_PROTECTION 0x85 134 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 135 136 #define CFI_CMDSET_NONE 0 137 #define CFI_CMDSET_INTEL_EXTENDED 1 138 #define CFI_CMDSET_AMD_STANDARD 2 139 #define CFI_CMDSET_INTEL_STANDARD 3 140 #define CFI_CMDSET_AMD_EXTENDED 4 141 #define CFI_CMDSET_MITSU_STANDARD 256 142 #define CFI_CMDSET_MITSU_EXTENDED 257 143 #define CFI_CMDSET_SST 258 144 #define CFI_CMDSET_INTEL_PROG_REGIONS 512 145 146 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ 147 # undef FLASH_CMD_RESET 148 # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ 149 #endif 150 151 typedef union { 152 unsigned char c; 153 unsigned short w; 154 unsigned long l; 155 unsigned long long ll; 156 } cfiword_t; 157 158 #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ 159 160 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; 161 162 /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ 163 #ifdef CFG_MAX_FLASH_BANKS_DETECT 164 # define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS_DETECT 165 #else 166 # define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS 167 #endif 168 169 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ 170 171 /* 172 * Check if chip width is defined. If not, start detecting with 8bit. 173 */ 174 #ifndef CFG_FLASH_CFI_WIDTH 175 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT 176 #endif 177 178 typedef unsigned long flash_sect_t; 179 180 /* CFI standard query structure */ 181 struct cfi_qry { 182 u8 qry[3]; 183 u16 p_id; 184 u16 p_adr; 185 u16 a_id; 186 u16 a_adr; 187 u8 vcc_min; 188 u8 vcc_max; 189 u8 vpp_min; 190 u8 vpp_max; 191 u8 word_write_timeout_typ; 192 u8 buf_write_timeout_typ; 193 u8 block_erase_timeout_typ; 194 u8 chip_erase_timeout_typ; 195 u8 word_write_timeout_max; 196 u8 buf_write_timeout_max; 197 u8 block_erase_timeout_max; 198 u8 chip_erase_timeout_max; 199 u8 dev_size; 200 u16 interface_desc; 201 u16 max_buf_write_size; 202 u8 num_erase_regions; 203 u32 erase_region_info[NUM_ERASE_REGIONS]; 204 } __attribute__((packed)); 205 206 struct cfi_pri_hdr { 207 u8 pri[3]; 208 u8 major_version; 209 u8 minor_version; 210 } __attribute__((packed)); 211 212 static void flash_write8(u8 value, void *addr) 213 { 214 __raw_writeb(value, addr); 215 } 216 217 static void flash_write16(u16 value, void *addr) 218 { 219 __raw_writew(value, addr); 220 } 221 222 static void flash_write32(u32 value, void *addr) 223 { 224 __raw_writel(value, addr); 225 } 226 227 static void flash_write64(u64 value, void *addr) 228 { 229 /* No architectures currently implement __raw_writeq() */ 230 *(volatile u64 *)addr = value; 231 } 232 233 static u8 flash_read8(void *addr) 234 { 235 return __raw_readb(addr); 236 } 237 238 static u16 flash_read16(void *addr) 239 { 240 return __raw_readw(addr); 241 } 242 243 static u32 flash_read32(void *addr) 244 { 245 return __raw_readl(addr); 246 } 247 248 static u64 __flash_read64(void *addr) 249 { 250 /* No architectures currently implement __raw_readq() */ 251 return *(volatile u64 *)addr; 252 } 253 254 u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); 255 256 /*----------------------------------------------------------------------- 257 */ 258 #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) 259 static flash_info_t *flash_get_info(ulong base) 260 { 261 int i; 262 flash_info_t * info = 0; 263 264 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { 265 info = & flash_info[i]; 266 if (info->size && info->start[0] <= base && 267 base <= info->start[0] + info->size - 1) 268 break; 269 } 270 271 return i == CFG_MAX_FLASH_BANKS ? 0 : info; 272 } 273 #endif 274 275 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) 276 { 277 if (sect != (info->sector_count - 1)) 278 return info->start[sect + 1] - info->start[sect]; 279 else 280 return info->start[0] + info->size - info->start[sect]; 281 } 282 283 /*----------------------------------------------------------------------- 284 * create an address based on the offset and the port width 285 */ 286 static inline void * 287 flash_map (flash_info_t * info, flash_sect_t sect, uint offset) 288 { 289 unsigned int byte_offset = offset * info->portwidth; 290 291 return map_physmem(info->start[sect] + byte_offset, 292 flash_sector_size(info, sect) - byte_offset, 293 MAP_NOCACHE); 294 } 295 296 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, 297 unsigned int offset, void *addr) 298 { 299 unsigned int byte_offset = offset * info->portwidth; 300 301 unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset); 302 } 303 304 /*----------------------------------------------------------------------- 305 * make a proper sized command based on the port and chip widths 306 */ 307 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) 308 { 309 int i; 310 int cword_offset; 311 int cp_offset; 312 #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) 313 u32 cmd_le = cpu_to_le32(cmd); 314 #endif 315 uchar val; 316 uchar *cp = (uchar *) cmdbuf; 317 318 for (i = info->portwidth; i > 0; i--){ 319 cword_offset = (info->portwidth-i)%info->chipwidth; 320 #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) 321 cp_offset = info->portwidth - i; 322 val = *((uchar*)&cmd_le + cword_offset); 323 #else 324 cp_offset = i - 1; 325 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); 326 #endif 327 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; 328 } 329 } 330 331 #ifdef DEBUG 332 /*----------------------------------------------------------------------- 333 * Debug support 334 */ 335 static void print_longlong (char *str, unsigned long long data) 336 { 337 int i; 338 char *cp; 339 340 cp = (unsigned char *) &data; 341 for (i = 0; i < 8; i++) 342 sprintf (&str[i * 2], "%2.2x", *cp++); 343 } 344 345 static void flash_printqry (struct cfi_qry *qry) 346 { 347 u8 *p = (u8 *)qry; 348 int x, y; 349 350 for (x = 0; x < sizeof(struct cfi_qry); x += 16) { 351 debug("%02x : ", x); 352 for (y = 0; y < 16; y++) 353 debug("%2.2x ", p[x + y]); 354 debug(" "); 355 for (y = 0; y < 16; y++) { 356 unsigned char c = p[x + y]; 357 if (c >= 0x20 && c <= 0x7e) 358 debug("%c", c); 359 else 360 debug("."); 361 } 362 debug("\n"); 363 } 364 } 365 #endif 366 367 368 /*----------------------------------------------------------------------- 369 * read a character at a port width address 370 */ 371 static inline uchar flash_read_uchar (flash_info_t * info, uint offset) 372 { 373 uchar *cp; 374 uchar retval; 375 376 cp = flash_map (info, 0, offset); 377 #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) 378 retval = flash_read8(cp); 379 #else 380 retval = flash_read8(cp + info->portwidth - 1); 381 #endif 382 flash_unmap (info, 0, offset, cp); 383 return retval; 384 } 385 386 /*----------------------------------------------------------------------- 387 * read a word at a port width address, assume 16bit bus 388 */ 389 static inline ushort flash_read_word (flash_info_t * info, uint offset) 390 { 391 ushort *addr, retval; 392 393 addr = flash_map (info, 0, offset); 394 retval = flash_read16 (addr); 395 flash_unmap (info, 0, offset, addr); 396 return retval; 397 } 398 399 400 /*----------------------------------------------------------------------- 401 * read a long word by picking the least significant byte of each maximum 402 * port size word. Swap for ppc format. 403 */ 404 static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, 405 uint offset) 406 { 407 uchar *addr; 408 ulong retval; 409 410 #ifdef DEBUG 411 int x; 412 #endif 413 addr = flash_map (info, sect, offset); 414 415 #ifdef DEBUG 416 debug ("long addr is at %p info->portwidth = %d\n", addr, 417 info->portwidth); 418 for (x = 0; x < 4 * info->portwidth; x++) { 419 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); 420 } 421 #endif 422 #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) 423 retval = ((flash_read8(addr) << 16) | 424 (flash_read8(addr + info->portwidth) << 24) | 425 (flash_read8(addr + 2 * info->portwidth)) | 426 (flash_read8(addr + 3 * info->portwidth) << 8)); 427 #else 428 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | 429 (flash_read8(addr + info->portwidth - 1) << 16) | 430 (flash_read8(addr + 4 * info->portwidth - 1) << 8) | 431 (flash_read8(addr + 3 * info->portwidth - 1))); 432 #endif 433 flash_unmap(info, sect, offset, addr); 434 435 return retval; 436 } 437 438 /* 439 * Write a proper sized command to the correct address 440 */ 441 static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, 442 uint offset, u32 cmd) 443 { 444 445 void *addr; 446 cfiword_t cword; 447 448 addr = flash_map (info, sect, offset); 449 flash_make_cmd (info, cmd, &cword); 450 switch (info->portwidth) { 451 case FLASH_CFI_8BIT: 452 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, 453 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 454 flash_write8(cword.c, addr); 455 break; 456 case FLASH_CFI_16BIT: 457 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, 458 cmd, cword.w, 459 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 460 flash_write16(cword.w, addr); 461 break; 462 case FLASH_CFI_32BIT: 463 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, 464 cmd, cword.l, 465 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 466 flash_write32(cword.l, addr); 467 break; 468 case FLASH_CFI_64BIT: 469 #ifdef DEBUG 470 { 471 char str[20]; 472 473 print_longlong (str, cword.ll); 474 475 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", 476 addr, cmd, str, 477 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 478 } 479 #endif 480 flash_write64(cword.ll, addr); 481 break; 482 } 483 484 /* Ensure all the instructions are fully finished */ 485 sync(); 486 487 flash_unmap(info, sect, offset, addr); 488 } 489 490 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) 491 { 492 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); 493 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); 494 } 495 496 /*----------------------------------------------------------------------- 497 */ 498 static int flash_isequal (flash_info_t * info, flash_sect_t sect, 499 uint offset, uchar cmd) 500 { 501 void *addr; 502 cfiword_t cword; 503 int retval; 504 505 addr = flash_map (info, sect, offset); 506 flash_make_cmd (info, cmd, &cword); 507 508 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); 509 switch (info->portwidth) { 510 case FLASH_CFI_8BIT: 511 debug ("is= %x %x\n", flash_read8(addr), cword.c); 512 retval = (flash_read8(addr) == cword.c); 513 break; 514 case FLASH_CFI_16BIT: 515 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); 516 retval = (flash_read16(addr) == cword.w); 517 break; 518 case FLASH_CFI_32BIT: 519 debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l); 520 retval = (flash_read32(addr) == cword.l); 521 break; 522 case FLASH_CFI_64BIT: 523 #ifdef DEBUG 524 { 525 char str1[20]; 526 char str2[20]; 527 528 print_longlong (str1, flash_read64(addr)); 529 print_longlong (str2, cword.ll); 530 debug ("is= %s %s\n", str1, str2); 531 } 532 #endif 533 retval = (flash_read64(addr) == cword.ll); 534 break; 535 default: 536 retval = 0; 537 break; 538 } 539 flash_unmap(info, sect, offset, addr); 540 541 return retval; 542 } 543 544 /*----------------------------------------------------------------------- 545 */ 546 static int flash_isset (flash_info_t * info, flash_sect_t sect, 547 uint offset, uchar cmd) 548 { 549 void *addr; 550 cfiword_t cword; 551 int retval; 552 553 addr = flash_map (info, sect, offset); 554 flash_make_cmd (info, cmd, &cword); 555 switch (info->portwidth) { 556 case FLASH_CFI_8BIT: 557 retval = ((flash_read8(addr) & cword.c) == cword.c); 558 break; 559 case FLASH_CFI_16BIT: 560 retval = ((flash_read16(addr) & cword.w) == cword.w); 561 break; 562 case FLASH_CFI_32BIT: 563 retval = ((flash_read32(addr) & cword.l) == cword.l); 564 break; 565 case FLASH_CFI_64BIT: 566 retval = ((flash_read64(addr) & cword.ll) == cword.ll); 567 break; 568 default: 569 retval = 0; 570 break; 571 } 572 flash_unmap(info, sect, offset, addr); 573 574 return retval; 575 } 576 577 /*----------------------------------------------------------------------- 578 */ 579 static int flash_toggle (flash_info_t * info, flash_sect_t sect, 580 uint offset, uchar cmd) 581 { 582 void *addr; 583 cfiword_t cword; 584 int retval; 585 586 addr = flash_map (info, sect, offset); 587 flash_make_cmd (info, cmd, &cword); 588 switch (info->portwidth) { 589 case FLASH_CFI_8BIT: 590 retval = flash_read8(addr) != flash_read8(addr); 591 break; 592 case FLASH_CFI_16BIT: 593 retval = flash_read16(addr) != flash_read16(addr); 594 break; 595 case FLASH_CFI_32BIT: 596 retval = flash_read32(addr) != flash_read32(addr); 597 break; 598 case FLASH_CFI_64BIT: 599 retval = flash_read64(addr) != flash_read64(addr); 600 break; 601 default: 602 retval = 0; 603 break; 604 } 605 flash_unmap(info, sect, offset, addr); 606 607 return retval; 608 } 609 610 /* 611 * flash_is_busy - check to see if the flash is busy 612 * 613 * This routine checks the status of the chip and returns true if the 614 * chip is busy. 615 */ 616 static int flash_is_busy (flash_info_t * info, flash_sect_t sect) 617 { 618 int retval; 619 620 switch (info->vendor) { 621 case CFI_CMDSET_INTEL_PROG_REGIONS: 622 case CFI_CMDSET_INTEL_STANDARD: 623 case CFI_CMDSET_INTEL_EXTENDED: 624 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); 625 break; 626 case CFI_CMDSET_AMD_STANDARD: 627 case CFI_CMDSET_AMD_EXTENDED: 628 #ifdef CONFIG_FLASH_CFI_LEGACY 629 case CFI_CMDSET_AMD_LEGACY: 630 #endif 631 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); 632 break; 633 default: 634 retval = 0; 635 } 636 debug ("flash_is_busy: %d\n", retval); 637 return retval; 638 } 639 640 /*----------------------------------------------------------------------- 641 * wait for XSR.7 to be set. Time out with an error if it does not. 642 * This routine does not set the flash to read-array mode. 643 */ 644 static int flash_status_check (flash_info_t * info, flash_sect_t sector, 645 ulong tout, char *prompt) 646 { 647 ulong start; 648 649 #if CFG_HZ != 1000 650 tout *= CFG_HZ/1000; 651 #endif 652 653 /* Wait for command completion */ 654 start = get_timer (0); 655 while (flash_is_busy (info, sector)) { 656 if (get_timer (start) > tout) { 657 printf ("Flash %s timeout at address %lx data %lx\n", 658 prompt, info->start[sector], 659 flash_read_long (info, sector, 0)); 660 flash_write_cmd (info, sector, 0, info->cmd_reset); 661 return ERR_TIMOUT; 662 } 663 udelay (1); /* also triggers watchdog */ 664 } 665 return ERR_OK; 666 } 667 668 /*----------------------------------------------------------------------- 669 * Wait for XSR.7 to be set, if it times out print an error, otherwise 670 * do a full status check. 671 * 672 * This routine sets the flash to read-array mode. 673 */ 674 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, 675 ulong tout, char *prompt) 676 { 677 int retcode; 678 679 retcode = flash_status_check (info, sector, tout, prompt); 680 switch (info->vendor) { 681 case CFI_CMDSET_INTEL_PROG_REGIONS: 682 case CFI_CMDSET_INTEL_EXTENDED: 683 case CFI_CMDSET_INTEL_STANDARD: 684 if ((retcode == ERR_OK) 685 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { 686 retcode = ERR_INVAL; 687 printf ("Flash %s error at address %lx\n", prompt, 688 info->start[sector]); 689 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | 690 FLASH_STATUS_PSLBS)) { 691 puts ("Command Sequence Error.\n"); 692 } else if (flash_isset (info, sector, 0, 693 FLASH_STATUS_ECLBS)) { 694 puts ("Block Erase Error.\n"); 695 retcode = ERR_NOT_ERASED; 696 } else if (flash_isset (info, sector, 0, 697 FLASH_STATUS_PSLBS)) { 698 puts ("Locking Error\n"); 699 } 700 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { 701 puts ("Block locked.\n"); 702 retcode = ERR_PROTECTED; 703 } 704 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) 705 puts ("Vpp Low Error.\n"); 706 } 707 flash_write_cmd (info, sector, 0, info->cmd_reset); 708 break; 709 default: 710 break; 711 } 712 return retcode; 713 } 714 715 /*----------------------------------------------------------------------- 716 */ 717 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) 718 { 719 #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) 720 unsigned short w; 721 unsigned int l; 722 unsigned long long ll; 723 #endif 724 725 switch (info->portwidth) { 726 case FLASH_CFI_8BIT: 727 cword->c = c; 728 break; 729 case FLASH_CFI_16BIT: 730 #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) 731 w = c; 732 w <<= 8; 733 cword->w = (cword->w >> 8) | w; 734 #else 735 cword->w = (cword->w << 8) | c; 736 #endif 737 break; 738 case FLASH_CFI_32BIT: 739 #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) 740 l = c; 741 l <<= 24; 742 cword->l = (cword->l >> 8) | l; 743 #else 744 cword->l = (cword->l << 8) | c; 745 #endif 746 break; 747 case FLASH_CFI_64BIT: 748 #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) 749 ll = c; 750 ll <<= 56; 751 cword->ll = (cword->ll >> 8) | ll; 752 #else 753 cword->ll = (cword->ll << 8) | c; 754 #endif 755 break; 756 } 757 } 758 759 /* loop through the sectors from the highest address when the passed 760 * address is greater or equal to the sector address we have a match 761 */ 762 static flash_sect_t find_sector (flash_info_t * info, ulong addr) 763 { 764 flash_sect_t sector; 765 766 for (sector = info->sector_count - 1; sector >= 0; sector--) { 767 if (addr >= info->start[sector]) 768 break; 769 } 770 return sector; 771 } 772 773 /*----------------------------------------------------------------------- 774 */ 775 static int flash_write_cfiword (flash_info_t * info, ulong dest, 776 cfiword_t cword) 777 { 778 void *dstaddr; 779 int flag; 780 781 dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE); 782 783 /* Check if Flash is (sufficiently) erased */ 784 switch (info->portwidth) { 785 case FLASH_CFI_8BIT: 786 flag = ((flash_read8(dstaddr) & cword.c) == cword.c); 787 break; 788 case FLASH_CFI_16BIT: 789 flag = ((flash_read16(dstaddr) & cword.w) == cword.w); 790 break; 791 case FLASH_CFI_32BIT: 792 flag = ((flash_read32(dstaddr) & cword.l) == cword.l); 793 break; 794 case FLASH_CFI_64BIT: 795 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); 796 break; 797 default: 798 flag = 0; 799 break; 800 } 801 if (!flag) { 802 unmap_physmem(dstaddr, info->portwidth); 803 return ERR_NOT_ERASED; 804 } 805 806 /* Disable interrupts which might cause a timeout here */ 807 flag = disable_interrupts (); 808 809 switch (info->vendor) { 810 case CFI_CMDSET_INTEL_PROG_REGIONS: 811 case CFI_CMDSET_INTEL_EXTENDED: 812 case CFI_CMDSET_INTEL_STANDARD: 813 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); 814 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); 815 break; 816 case CFI_CMDSET_AMD_EXTENDED: 817 case CFI_CMDSET_AMD_STANDARD: 818 #ifdef CONFIG_FLASH_CFI_LEGACY 819 case CFI_CMDSET_AMD_LEGACY: 820 #endif 821 flash_unlock_seq (info, 0); 822 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); 823 break; 824 } 825 826 switch (info->portwidth) { 827 case FLASH_CFI_8BIT: 828 flash_write8(cword.c, dstaddr); 829 break; 830 case FLASH_CFI_16BIT: 831 flash_write16(cword.w, dstaddr); 832 break; 833 case FLASH_CFI_32BIT: 834 flash_write32(cword.l, dstaddr); 835 break; 836 case FLASH_CFI_64BIT: 837 flash_write64(cword.ll, dstaddr); 838 break; 839 } 840 841 /* re-enable interrupts if necessary */ 842 if (flag) 843 enable_interrupts (); 844 845 unmap_physmem(dstaddr, info->portwidth); 846 847 return flash_full_status_check (info, find_sector (info, dest), 848 info->write_tout, "write"); 849 } 850 851 #ifdef CFG_FLASH_USE_BUFFER_WRITE 852 853 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, 854 int len) 855 { 856 flash_sect_t sector; 857 int cnt; 858 int retcode; 859 void *src = cp; 860 void *dst = map_physmem(dest, len, MAP_NOCACHE); 861 void *dst2 = dst; 862 int flag = 0; 863 uint offset = 0; 864 unsigned int shift; 865 uchar write_cmd; 866 867 switch (info->portwidth) { 868 case FLASH_CFI_8BIT: 869 shift = 0; 870 break; 871 case FLASH_CFI_16BIT: 872 shift = 1; 873 break; 874 case FLASH_CFI_32BIT: 875 shift = 2; 876 break; 877 case FLASH_CFI_64BIT: 878 shift = 3; 879 break; 880 default: 881 retcode = ERR_INVAL; 882 goto out_unmap; 883 } 884 885 cnt = len >> shift; 886 887 while ((cnt-- > 0) && (flag == 0)) { 888 switch (info->portwidth) { 889 case FLASH_CFI_8BIT: 890 flag = ((flash_read8(dst2) & flash_read8(src)) == 891 flash_read8(src)); 892 src += 1, dst2 += 1; 893 break; 894 case FLASH_CFI_16BIT: 895 flag = ((flash_read16(dst2) & flash_read16(src)) == 896 flash_read16(src)); 897 src += 2, dst2 += 2; 898 break; 899 case FLASH_CFI_32BIT: 900 flag = ((flash_read32(dst2) & flash_read32(src)) == 901 flash_read32(src)); 902 src += 4, dst2 += 4; 903 break; 904 case FLASH_CFI_64BIT: 905 flag = ((flash_read64(dst2) & flash_read64(src)) == 906 flash_read64(src)); 907 src += 8, dst2 += 8; 908 break; 909 } 910 } 911 if (!flag) { 912 retcode = ERR_NOT_ERASED; 913 goto out_unmap; 914 } 915 916 src = cp; 917 sector = find_sector (info, dest); 918 919 switch (info->vendor) { 920 case CFI_CMDSET_INTEL_PROG_REGIONS: 921 case CFI_CMDSET_INTEL_STANDARD: 922 case CFI_CMDSET_INTEL_EXTENDED: 923 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? 924 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; 925 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); 926 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); 927 flash_write_cmd (info, sector, 0, write_cmd); 928 retcode = flash_status_check (info, sector, 929 info->buffer_write_tout, 930 "write to buffer"); 931 if (retcode == ERR_OK) { 932 /* reduce the number of loops by the width of 933 * the port */ 934 cnt = len >> shift; 935 flash_write_cmd (info, sector, 0, cnt - 1); 936 while (cnt-- > 0) { 937 switch (info->portwidth) { 938 case FLASH_CFI_8BIT: 939 flash_write8(flash_read8(src), dst); 940 src += 1, dst += 1; 941 break; 942 case FLASH_CFI_16BIT: 943 flash_write16(flash_read16(src), dst); 944 src += 2, dst += 2; 945 break; 946 case FLASH_CFI_32BIT: 947 flash_write32(flash_read32(src), dst); 948 src += 4, dst += 4; 949 break; 950 case FLASH_CFI_64BIT: 951 flash_write64(flash_read64(src), dst); 952 src += 8, dst += 8; 953 break; 954 default: 955 retcode = ERR_INVAL; 956 goto out_unmap; 957 } 958 } 959 flash_write_cmd (info, sector, 0, 960 FLASH_CMD_WRITE_BUFFER_CONFIRM); 961 retcode = flash_full_status_check ( 962 info, sector, info->buffer_write_tout, 963 "buffer write"); 964 } 965 966 break; 967 968 case CFI_CMDSET_AMD_STANDARD: 969 case CFI_CMDSET_AMD_EXTENDED: 970 flash_unlock_seq(info,0); 971 972 #ifdef CONFIG_FLASH_SPANSION_S29WS_N 973 offset = ((unsigned long)dst - info->start[sector]) >> shift; 974 #endif 975 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); 976 cnt = len >> shift; 977 flash_write_cmd(info, sector, offset, (uchar)cnt - 1); 978 979 switch (info->portwidth) { 980 case FLASH_CFI_8BIT: 981 while (cnt-- > 0) { 982 flash_write8(flash_read8(src), dst); 983 src += 1, dst += 1; 984 } 985 break; 986 case FLASH_CFI_16BIT: 987 while (cnt-- > 0) { 988 flash_write16(flash_read16(src), dst); 989 src += 2, dst += 2; 990 } 991 break; 992 case FLASH_CFI_32BIT: 993 while (cnt-- > 0) { 994 flash_write32(flash_read32(src), dst); 995 src += 4, dst += 4; 996 } 997 break; 998 case FLASH_CFI_64BIT: 999 while (cnt-- > 0) { 1000 flash_write64(flash_read64(src), dst); 1001 src += 8, dst += 8; 1002 } 1003 break; 1004 default: 1005 retcode = ERR_INVAL; 1006 goto out_unmap; 1007 } 1008 1009 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); 1010 retcode = flash_full_status_check (info, sector, 1011 info->buffer_write_tout, 1012 "buffer write"); 1013 break; 1014 1015 default: 1016 debug ("Unknown Command Set\n"); 1017 retcode = ERR_INVAL; 1018 break; 1019 } 1020 1021 out_unmap: 1022 unmap_physmem(dst, len); 1023 return retcode; 1024 } 1025 #endif /* CFG_FLASH_USE_BUFFER_WRITE */ 1026 1027 1028 /*----------------------------------------------------------------------- 1029 */ 1030 int flash_erase (flash_info_t * info, int s_first, int s_last) 1031 { 1032 int rcode = 0; 1033 int prot; 1034 flash_sect_t sect; 1035 1036 if (info->flash_id != FLASH_MAN_CFI) { 1037 puts ("Can't erase unknown flash type - aborted\n"); 1038 return 1; 1039 } 1040 if ((s_first < 0) || (s_first > s_last)) { 1041 puts ("- no sectors to erase\n"); 1042 return 1; 1043 } 1044 1045 prot = 0; 1046 for (sect = s_first; sect <= s_last; ++sect) { 1047 if (info->protect[sect]) { 1048 prot++; 1049 } 1050 } 1051 if (prot) { 1052 printf ("- Warning: %d protected sectors will not be erased!\n", 1053 prot); 1054 } else { 1055 putc ('\n'); 1056 } 1057 1058 1059 for (sect = s_first; sect <= s_last; sect++) { 1060 if (info->protect[sect] == 0) { /* not protected */ 1061 switch (info->vendor) { 1062 case CFI_CMDSET_INTEL_PROG_REGIONS: 1063 case CFI_CMDSET_INTEL_STANDARD: 1064 case CFI_CMDSET_INTEL_EXTENDED: 1065 flash_write_cmd (info, sect, 0, 1066 FLASH_CMD_CLEAR_STATUS); 1067 flash_write_cmd (info, sect, 0, 1068 FLASH_CMD_BLOCK_ERASE); 1069 flash_write_cmd (info, sect, 0, 1070 FLASH_CMD_ERASE_CONFIRM); 1071 break; 1072 case CFI_CMDSET_AMD_STANDARD: 1073 case CFI_CMDSET_AMD_EXTENDED: 1074 flash_unlock_seq (info, sect); 1075 flash_write_cmd (info, sect, 1076 info->addr_unlock1, 1077 AMD_CMD_ERASE_START); 1078 flash_unlock_seq (info, sect); 1079 flash_write_cmd (info, sect, 0, 1080 AMD_CMD_ERASE_SECTOR); 1081 break; 1082 #ifdef CONFIG_FLASH_CFI_LEGACY 1083 case CFI_CMDSET_AMD_LEGACY: 1084 flash_unlock_seq (info, 0); 1085 flash_write_cmd (info, 0, info->addr_unlock1, 1086 AMD_CMD_ERASE_START); 1087 flash_unlock_seq (info, 0); 1088 flash_write_cmd (info, sect, 0, 1089 AMD_CMD_ERASE_SECTOR); 1090 break; 1091 #endif 1092 default: 1093 debug ("Unkown flash vendor %d\n", 1094 info->vendor); 1095 break; 1096 } 1097 1098 if (flash_full_status_check 1099 (info, sect, info->erase_blk_tout, "erase")) { 1100 rcode = 1; 1101 } else 1102 putc ('.'); 1103 } 1104 } 1105 puts (" done\n"); 1106 return rcode; 1107 } 1108 1109 /*----------------------------------------------------------------------- 1110 */ 1111 void flash_print_info (flash_info_t * info) 1112 { 1113 int i; 1114 1115 if (info->flash_id != FLASH_MAN_CFI) { 1116 puts ("missing or unknown FLASH type\n"); 1117 return; 1118 } 1119 1120 printf ("%s FLASH (%d x %d)", 1121 info->name, 1122 (info->portwidth << 3), (info->chipwidth << 3)); 1123 if (info->size < 1024*1024) 1124 printf (" Size: %ld kB in %d Sectors\n", 1125 info->size >> 10, info->sector_count); 1126 else 1127 printf (" Size: %ld MB in %d Sectors\n", 1128 info->size >> 20, info->sector_count); 1129 printf (" "); 1130 switch (info->vendor) { 1131 case CFI_CMDSET_INTEL_PROG_REGIONS: 1132 printf ("Intel Prog Regions"); 1133 break; 1134 case CFI_CMDSET_INTEL_STANDARD: 1135 printf ("Intel Standard"); 1136 break; 1137 case CFI_CMDSET_INTEL_EXTENDED: 1138 printf ("Intel Extended"); 1139 break; 1140 case CFI_CMDSET_AMD_STANDARD: 1141 printf ("AMD Standard"); 1142 break; 1143 case CFI_CMDSET_AMD_EXTENDED: 1144 printf ("AMD Extended"); 1145 break; 1146 #ifdef CONFIG_FLASH_CFI_LEGACY 1147 case CFI_CMDSET_AMD_LEGACY: 1148 printf ("AMD Legacy"); 1149 break; 1150 #endif 1151 default: 1152 printf ("Unknown (%d)", info->vendor); 1153 break; 1154 } 1155 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X", 1156 info->manufacturer_id, info->device_id); 1157 if (info->device_id == 0x7E) { 1158 printf("%04X", info->device_id2); 1159 } 1160 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", 1161 info->erase_blk_tout, 1162 info->write_tout); 1163 if (info->buffer_size > 1) { 1164 printf (" Buffer write timeout: %ld ms, " 1165 "buffer size: %d bytes\n", 1166 info->buffer_write_tout, 1167 info->buffer_size); 1168 } 1169 1170 puts ("\n Sector Start Addresses:"); 1171 for (i = 0; i < info->sector_count; ++i) { 1172 if ((i % 5) == 0) 1173 printf ("\n"); 1174 #ifdef CFG_FLASH_EMPTY_INFO 1175 int k; 1176 int size; 1177 int erased; 1178 volatile unsigned long *flash; 1179 1180 /* 1181 * Check if whole sector is erased 1182 */ 1183 size = flash_sector_size(info, i); 1184 erased = 1; 1185 flash = (volatile unsigned long *) info->start[i]; 1186 size = size >> 2; /* divide by 4 for longword access */ 1187 for (k = 0; k < size; k++) { 1188 if (*flash++ != 0xffffffff) { 1189 erased = 0; 1190 break; 1191 } 1192 } 1193 1194 /* print empty and read-only info */ 1195 printf (" %08lX %c %s ", 1196 info->start[i], 1197 erased ? 'E' : ' ', 1198 info->protect[i] ? "RO" : " "); 1199 #else /* ! CFG_FLASH_EMPTY_INFO */ 1200 printf (" %08lX %s ", 1201 info->start[i], 1202 info->protect[i] ? "RO" : " "); 1203 #endif 1204 } 1205 putc ('\n'); 1206 return; 1207 } 1208 1209 /*----------------------------------------------------------------------- 1210 * This is used in a few places in write_buf() to show programming 1211 * progress. Making it a function is nasty because it needs to do side 1212 * effect updates to digit and dots. Repeated code is nasty too, so 1213 * we define it once here. 1214 */ 1215 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1216 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ 1217 dots -= dots_sub; \ 1218 if ((scale > 0) && (dots <= 0)) { \ 1219 if ((digit % 5) == 0) \ 1220 printf ("%d", digit / 5); \ 1221 else \ 1222 putc ('.'); \ 1223 digit--; \ 1224 dots += scale; \ 1225 } 1226 #else 1227 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) 1228 #endif 1229 1230 /*----------------------------------------------------------------------- 1231 * Copy memory to flash, returns: 1232 * 0 - OK 1233 * 1 - write timeout 1234 * 2 - Flash not erased 1235 */ 1236 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) 1237 { 1238 ulong wp; 1239 uchar *p; 1240 int aln; 1241 cfiword_t cword; 1242 int i, rc; 1243 #ifdef CFG_FLASH_USE_BUFFER_WRITE 1244 int buffered_size; 1245 #endif 1246 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1247 int digit = CONFIG_FLASH_SHOW_PROGRESS; 1248 int scale = 0; 1249 int dots = 0; 1250 1251 /* 1252 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. 1253 */ 1254 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { 1255 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / 1256 CONFIG_FLASH_SHOW_PROGRESS); 1257 } 1258 #endif 1259 1260 /* get lower aligned address */ 1261 wp = (addr & ~(info->portwidth - 1)); 1262 1263 /* handle unaligned start */ 1264 if ((aln = addr - wp) != 0) { 1265 cword.l = 0; 1266 p = map_physmem(wp, info->portwidth, MAP_NOCACHE); 1267 for (i = 0; i < aln; ++i) 1268 flash_add_byte (info, &cword, flash_read8(p + i)); 1269 1270 for (; (i < info->portwidth) && (cnt > 0); i++) { 1271 flash_add_byte (info, &cword, *src++); 1272 cnt--; 1273 } 1274 for (; (cnt == 0) && (i < info->portwidth); ++i) 1275 flash_add_byte (info, &cword, flash_read8(p + i)); 1276 1277 rc = flash_write_cfiword (info, wp, cword); 1278 unmap_physmem(p, info->portwidth); 1279 if (rc != 0) 1280 return rc; 1281 1282 wp += i; 1283 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1284 } 1285 1286 /* handle the aligned part */ 1287 #ifdef CFG_FLASH_USE_BUFFER_WRITE 1288 buffered_size = (info->portwidth / info->chipwidth); 1289 buffered_size *= info->buffer_size; 1290 while (cnt >= info->portwidth) { 1291 /* prohibit buffer write when buffer_size is 1 */ 1292 if (info->buffer_size == 1) { 1293 cword.l = 0; 1294 for (i = 0; i < info->portwidth; i++) 1295 flash_add_byte (info, &cword, *src++); 1296 if ((rc = flash_write_cfiword (info, wp, cword)) != 0) 1297 return rc; 1298 wp += info->portwidth; 1299 cnt -= info->portwidth; 1300 continue; 1301 } 1302 1303 /* write buffer until next buffered_size aligned boundary */ 1304 i = buffered_size - (wp % buffered_size); 1305 if (i > cnt) 1306 i = cnt; 1307 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) 1308 return rc; 1309 i -= i & (info->portwidth - 1); 1310 wp += i; 1311 src += i; 1312 cnt -= i; 1313 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1314 } 1315 #else 1316 while (cnt >= info->portwidth) { 1317 cword.l = 0; 1318 for (i = 0; i < info->portwidth; i++) { 1319 flash_add_byte (info, &cword, *src++); 1320 } 1321 if ((rc = flash_write_cfiword (info, wp, cword)) != 0) 1322 return rc; 1323 wp += info->portwidth; 1324 cnt -= info->portwidth; 1325 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); 1326 } 1327 #endif /* CFG_FLASH_USE_BUFFER_WRITE */ 1328 1329 if (cnt == 0) { 1330 return (0); 1331 } 1332 1333 /* 1334 * handle unaligned tail bytes 1335 */ 1336 cword.l = 0; 1337 p = map_physmem(wp, info->portwidth, MAP_NOCACHE); 1338 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { 1339 flash_add_byte (info, &cword, *src++); 1340 --cnt; 1341 } 1342 for (; i < info->portwidth; ++i) 1343 flash_add_byte (info, &cword, flash_read8(p + i)); 1344 unmap_physmem(p, info->portwidth); 1345 1346 return flash_write_cfiword (info, wp, cword); 1347 } 1348 1349 /*----------------------------------------------------------------------- 1350 */ 1351 #ifdef CFG_FLASH_PROTECTION 1352 1353 int flash_real_protect (flash_info_t * info, long sector, int prot) 1354 { 1355 int retcode = 0; 1356 1357 switch (info->vendor) { 1358 case CFI_CMDSET_INTEL_PROG_REGIONS: 1359 case CFI_CMDSET_INTEL_STANDARD: 1360 flash_write_cmd (info, sector, 0, 1361 FLASH_CMD_CLEAR_STATUS); 1362 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); 1363 if (prot) 1364 flash_write_cmd (info, sector, 0, 1365 FLASH_CMD_PROTECT_SET); 1366 else 1367 flash_write_cmd (info, sector, 0, 1368 FLASH_CMD_PROTECT_CLEAR); 1369 break; 1370 case CFI_CMDSET_AMD_EXTENDED: 1371 case CFI_CMDSET_AMD_STANDARD: 1372 /* U-Boot only checks the first byte */ 1373 if (info->manufacturer_id == (uchar)ATM_MANUFACT) { 1374 if (prot) { 1375 flash_unlock_seq (info, 0); 1376 flash_write_cmd (info, 0, 1377 info->addr_unlock1, 1378 ATM_CMD_SOFTLOCK_START); 1379 flash_unlock_seq (info, 0); 1380 flash_write_cmd (info, sector, 0, 1381 ATM_CMD_LOCK_SECT); 1382 } else { 1383 flash_write_cmd (info, 0, 1384 info->addr_unlock1, 1385 AMD_CMD_UNLOCK_START); 1386 if (info->device_id == ATM_ID_BV6416) 1387 flash_write_cmd (info, sector, 1388 0, ATM_CMD_UNLOCK_SECT); 1389 } 1390 } 1391 break; 1392 #ifdef CONFIG_FLASH_CFI_LEGACY 1393 case CFI_CMDSET_AMD_LEGACY: 1394 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); 1395 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); 1396 if (prot) 1397 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); 1398 else 1399 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); 1400 #endif 1401 }; 1402 1403 if ((retcode = 1404 flash_full_status_check (info, sector, info->erase_blk_tout, 1405 prot ? "protect" : "unprotect")) == 0) { 1406 1407 info->protect[sector] = prot; 1408 1409 /* 1410 * On some of Intel's flash chips (marked via legacy_unlock) 1411 * unprotect unprotects all locking. 1412 */ 1413 if ((prot == 0) && (info->legacy_unlock)) { 1414 flash_sect_t i; 1415 1416 for (i = 0; i < info->sector_count; i++) { 1417 if (info->protect[i]) 1418 flash_real_protect (info, i, 1); 1419 } 1420 } 1421 } 1422 return retcode; 1423 } 1424 1425 /*----------------------------------------------------------------------- 1426 * flash_read_user_serial - read the OneTimeProgramming cells 1427 */ 1428 void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, 1429 int len) 1430 { 1431 uchar *src; 1432 uchar *dst; 1433 1434 dst = buffer; 1435 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); 1436 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); 1437 memcpy (dst, src + offset, len); 1438 flash_write_cmd (info, 0, 0, info->cmd_reset); 1439 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); 1440 } 1441 1442 /* 1443 * flash_read_factory_serial - read the device Id from the protection area 1444 */ 1445 void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, 1446 int len) 1447 { 1448 uchar *src; 1449 1450 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); 1451 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); 1452 memcpy (buffer, src + offset, len); 1453 flash_write_cmd (info, 0, 0, info->cmd_reset); 1454 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); 1455 } 1456 1457 #endif /* CFG_FLASH_PROTECTION */ 1458 1459 /*----------------------------------------------------------------------- 1460 * Reverse the order of the erase regions in the CFI QRY structure. 1461 * This is needed for chips that are either a) correctly detected as 1462 * top-boot, or b) buggy. 1463 */ 1464 static void cfi_reverse_geometry(struct cfi_qry *qry) 1465 { 1466 unsigned int i, j; 1467 u32 tmp; 1468 1469 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { 1470 tmp = qry->erase_region_info[i]; 1471 qry->erase_region_info[i] = qry->erase_region_info[j]; 1472 qry->erase_region_info[j] = tmp; 1473 } 1474 } 1475 1476 /*----------------------------------------------------------------------- 1477 * read jedec ids from device and set corresponding fields in info struct 1478 * 1479 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct 1480 * 1481 */ 1482 static void cmdset_intel_read_jedec_ids(flash_info_t *info) 1483 { 1484 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1485 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1486 udelay(1000); /* some flash are slow to respond */ 1487 info->manufacturer_id = flash_read_uchar (info, 1488 FLASH_OFFSET_MANUFACTURER_ID); 1489 info->device_id = flash_read_uchar (info, 1490 FLASH_OFFSET_DEVICE_ID); 1491 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1492 } 1493 1494 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) 1495 { 1496 info->cmd_reset = FLASH_CMD_RESET; 1497 1498 cmdset_intel_read_jedec_ids(info); 1499 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1500 1501 #ifdef CFG_FLASH_PROTECTION 1502 /* read legacy lock/unlock bit from intel flash */ 1503 if (info->ext_addr) { 1504 info->legacy_unlock = flash_read_uchar (info, 1505 info->ext_addr + 5) & 0x08; 1506 } 1507 #endif 1508 1509 return 0; 1510 } 1511 1512 static void cmdset_amd_read_jedec_ids(flash_info_t *info) 1513 { 1514 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1515 flash_unlock_seq(info, 0); 1516 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); 1517 udelay(1000); /* some flash are slow to respond */ 1518 1519 info->manufacturer_id = flash_read_uchar (info, 1520 FLASH_OFFSET_MANUFACTURER_ID); 1521 1522 switch (info->chipwidth){ 1523 case FLASH_CFI_8BIT: 1524 info->device_id = flash_read_uchar (info, 1525 FLASH_OFFSET_DEVICE_ID); 1526 if (info->device_id == 0x7E) { 1527 /* AMD 3-byte (expanded) device ids */ 1528 info->device_id2 = flash_read_uchar (info, 1529 FLASH_OFFSET_DEVICE_ID2); 1530 info->device_id2 <<= 8; 1531 info->device_id2 |= flash_read_uchar (info, 1532 FLASH_OFFSET_DEVICE_ID3); 1533 } 1534 break; 1535 case FLASH_CFI_16BIT: 1536 info->device_id = flash_read_word (info, 1537 FLASH_OFFSET_DEVICE_ID); 1538 break; 1539 default: 1540 break; 1541 } 1542 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1543 } 1544 1545 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) 1546 { 1547 info->cmd_reset = AMD_CMD_RESET; 1548 1549 cmdset_amd_read_jedec_ids(info); 1550 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1551 1552 return 0; 1553 } 1554 1555 #ifdef CONFIG_FLASH_CFI_LEGACY 1556 static void flash_read_jedec_ids (flash_info_t * info) 1557 { 1558 info->manufacturer_id = 0; 1559 info->device_id = 0; 1560 info->device_id2 = 0; 1561 1562 switch (info->vendor) { 1563 case CFI_CMDSET_INTEL_PROG_REGIONS: 1564 case CFI_CMDSET_INTEL_STANDARD: 1565 case CFI_CMDSET_INTEL_EXTENDED: 1566 cmdset_intel_read_jedec_ids(info); 1567 break; 1568 case CFI_CMDSET_AMD_STANDARD: 1569 case CFI_CMDSET_AMD_EXTENDED: 1570 cmdset_amd_read_jedec_ids(info); 1571 break; 1572 default: 1573 break; 1574 } 1575 } 1576 1577 /*----------------------------------------------------------------------- 1578 * Call board code to request info about non-CFI flash. 1579 * board_flash_get_legacy needs to fill in at least: 1580 * info->portwidth, info->chipwidth and info->interface for Jedec probing. 1581 */ 1582 static int flash_detect_legacy(ulong base, int banknum) 1583 { 1584 flash_info_t *info = &flash_info[banknum]; 1585 1586 if (board_flash_get_legacy(base, banknum, info)) { 1587 /* board code may have filled info completely. If not, we 1588 use JEDEC ID probing. */ 1589 if (!info->vendor) { 1590 int modes[] = { 1591 CFI_CMDSET_AMD_STANDARD, 1592 CFI_CMDSET_INTEL_STANDARD 1593 }; 1594 int i; 1595 1596 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { 1597 info->vendor = modes[i]; 1598 info->start[0] = base; 1599 if (info->portwidth == FLASH_CFI_8BIT 1600 && info->interface == FLASH_CFI_X8X16) { 1601 info->addr_unlock1 = 0x2AAA; 1602 info->addr_unlock2 = 0x5555; 1603 } else { 1604 info->addr_unlock1 = 0x5555; 1605 info->addr_unlock2 = 0x2AAA; 1606 } 1607 flash_read_jedec_ids(info); 1608 debug("JEDEC PROBE: ID %x %x %x\n", 1609 info->manufacturer_id, 1610 info->device_id, 1611 info->device_id2); 1612 if (jedec_flash_match(info, base)) 1613 break; 1614 } 1615 } 1616 1617 switch(info->vendor) { 1618 case CFI_CMDSET_INTEL_PROG_REGIONS: 1619 case CFI_CMDSET_INTEL_STANDARD: 1620 case CFI_CMDSET_INTEL_EXTENDED: 1621 info->cmd_reset = FLASH_CMD_RESET; 1622 break; 1623 case CFI_CMDSET_AMD_STANDARD: 1624 case CFI_CMDSET_AMD_EXTENDED: 1625 case CFI_CMDSET_AMD_LEGACY: 1626 info->cmd_reset = AMD_CMD_RESET; 1627 break; 1628 } 1629 info->flash_id = FLASH_MAN_CFI; 1630 return 1; 1631 } 1632 return 0; /* use CFI */ 1633 } 1634 #else 1635 static inline int flash_detect_legacy(ulong base, int banknum) 1636 { 1637 return 0; /* use CFI */ 1638 } 1639 #endif 1640 1641 /*----------------------------------------------------------------------- 1642 * detect if flash is compatible with the Common Flash Interface (CFI) 1643 * http://www.jedec.org/download/search/jesd68.pdf 1644 */ 1645 static void flash_read_cfi (flash_info_t *info, void *buf, 1646 unsigned int start, size_t len) 1647 { 1648 u8 *p = buf; 1649 unsigned int i; 1650 1651 for (i = 0; i < len; i++) 1652 p[i] = flash_read_uchar(info, start + i); 1653 } 1654 1655 static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) 1656 { 1657 int cfi_offset; 1658 1659 /* We do not yet know what kind of commandset to use, so we issue 1660 the reset command in both Intel and AMD variants, in the hope 1661 that AMD flash roms ignore the Intel command. */ 1662 flash_write_cmd (info, 0, 0, AMD_CMD_RESET); 1663 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); 1664 1665 for (cfi_offset=0; 1666 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); 1667 cfi_offset++) { 1668 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], 1669 FLASH_CMD_CFI); 1670 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') 1671 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') 1672 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { 1673 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, 1674 sizeof(struct cfi_qry)); 1675 info->interface = le16_to_cpu(qry->interface_desc); 1676 1677 info->cfi_offset = flash_offset_cfi[cfi_offset]; 1678 debug ("device interface is %d\n", 1679 info->interface); 1680 debug ("found port %d chip %d ", 1681 info->portwidth, info->chipwidth); 1682 debug ("port %d bits chip %d bits\n", 1683 info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1684 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1685 1686 /* calculate command offsets as in the Linux driver */ 1687 info->addr_unlock1 = 0x555; 1688 info->addr_unlock2 = 0x2aa; 1689 1690 /* 1691 * modify the unlock address if we are 1692 * in compatibility mode 1693 */ 1694 if ( /* x8/x16 in x8 mode */ 1695 ((info->chipwidth == FLASH_CFI_BY8) && 1696 (info->interface == FLASH_CFI_X8X16)) || 1697 /* x16/x32 in x16 mode */ 1698 ((info->chipwidth == FLASH_CFI_BY16) && 1699 (info->interface == FLASH_CFI_X16X32))) 1700 { 1701 info->addr_unlock1 = 0xaaa; 1702 info->addr_unlock2 = 0x555; 1703 } 1704 1705 info->name = "CFI conformant"; 1706 return 1; 1707 } 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) 1714 { 1715 debug ("flash detect cfi\n"); 1716 1717 for (info->portwidth = CFG_FLASH_CFI_WIDTH; 1718 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { 1719 for (info->chipwidth = FLASH_CFI_BY8; 1720 info->chipwidth <= info->portwidth; 1721 info->chipwidth <<= 1) 1722 if (__flash_detect_cfi(info, qry)) 1723 return 1; 1724 } 1725 debug ("not found\n"); 1726 return 0; 1727 } 1728 1729 /* 1730 * Manufacturer-specific quirks. Add workarounds for geometry 1731 * reversal, etc. here. 1732 */ 1733 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) 1734 { 1735 /* check if flash geometry needs reversal */ 1736 if (qry->num_erase_regions > 1) { 1737 /* reverse geometry if top boot part */ 1738 if (info->cfi_version < 0x3131) { 1739 /* CFI < 1.1, try to guess from device id */ 1740 if ((info->device_id & 0x80) != 0) 1741 cfi_reverse_geometry(qry); 1742 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1743 /* CFI >= 1.1, deduct from top/bottom flag */ 1744 /* note: ext_addr is valid since cfi_version > 0 */ 1745 cfi_reverse_geometry(qry); 1746 } 1747 } 1748 } 1749 1750 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) 1751 { 1752 int reverse_geometry = 0; 1753 1754 /* Check the "top boot" bit in the PRI */ 1755 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) 1756 reverse_geometry = 1; 1757 1758 /* AT49BV6416(T) list the erase regions in the wrong order. 1759 * However, the device ID is identical with the non-broken 1760 * AT49BV642D since u-boot only reads the low byte (they 1761 * differ in the high byte.) So leave out this fixup for now. 1762 */ 1763 #if 0 1764 if (info->device_id == 0xd6 || info->device_id == 0xd2) 1765 reverse_geometry = !reverse_geometry; 1766 #endif 1767 1768 if (reverse_geometry) 1769 cfi_reverse_geometry(qry); 1770 } 1771 1772 /* 1773 * The following code cannot be run from FLASH! 1774 * 1775 */ 1776 ulong flash_get_size (ulong base, int banknum) 1777 { 1778 flash_info_t *info = &flash_info[banknum]; 1779 int i, j; 1780 flash_sect_t sect_cnt; 1781 unsigned long sector; 1782 unsigned long tmp; 1783 int size_ratio; 1784 uchar num_erase_regions; 1785 int erase_region_size; 1786 int erase_region_count; 1787 struct cfi_qry qry; 1788 1789 memset(&qry, 0, sizeof(qry)); 1790 1791 info->ext_addr = 0; 1792 info->cfi_version = 0; 1793 #ifdef CFG_FLASH_PROTECTION 1794 info->legacy_unlock = 0; 1795 #endif 1796 1797 info->start[0] = base; 1798 1799 if (flash_detect_cfi (info, &qry)) { 1800 info->vendor = le16_to_cpu(qry.p_id); 1801 info->ext_addr = le16_to_cpu(qry.p_adr); 1802 num_erase_regions = qry.num_erase_regions; 1803 1804 if (info->ext_addr) { 1805 info->cfi_version = (ushort) flash_read_uchar (info, 1806 info->ext_addr + 3) << 8; 1807 info->cfi_version |= (ushort) flash_read_uchar (info, 1808 info->ext_addr + 4); 1809 } 1810 1811 #ifdef DEBUG 1812 flash_printqry (&qry); 1813 #endif 1814 1815 switch (info->vendor) { 1816 case CFI_CMDSET_INTEL_PROG_REGIONS: 1817 case CFI_CMDSET_INTEL_STANDARD: 1818 case CFI_CMDSET_INTEL_EXTENDED: 1819 cmdset_intel_init(info, &qry); 1820 break; 1821 case CFI_CMDSET_AMD_STANDARD: 1822 case CFI_CMDSET_AMD_EXTENDED: 1823 cmdset_amd_init(info, &qry); 1824 break; 1825 default: 1826 printf("CFI: Unknown command set 0x%x\n", 1827 info->vendor); 1828 /* 1829 * Unfortunately, this means we don't know how 1830 * to get the chip back to Read mode. Might 1831 * as well try an Intel-style reset... 1832 */ 1833 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1834 return 0; 1835 } 1836 1837 /* Do manufacturer-specific fixups */ 1838 switch (info->manufacturer_id) { 1839 case 0x0001: 1840 flash_fixup_amd(info, &qry); 1841 break; 1842 case 0x001f: 1843 flash_fixup_atmel(info, &qry); 1844 break; 1845 } 1846 1847 debug ("manufacturer is %d\n", info->vendor); 1848 debug ("manufacturer id is 0x%x\n", info->manufacturer_id); 1849 debug ("device id is 0x%x\n", info->device_id); 1850 debug ("device id2 is 0x%x\n", info->device_id2); 1851 debug ("cfi version is 0x%04x\n", info->cfi_version); 1852 1853 size_ratio = info->portwidth / info->chipwidth; 1854 /* if the chip is x8/x16 reduce the ratio by half */ 1855 if ((info->interface == FLASH_CFI_X8X16) 1856 && (info->chipwidth == FLASH_CFI_BY8)) { 1857 size_ratio >>= 1; 1858 } 1859 debug ("size_ratio %d port %d bits chip %d bits\n", 1860 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1861 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1862 debug ("found %d erase regions\n", num_erase_regions); 1863 sect_cnt = 0; 1864 sector = base; 1865 for (i = 0; i < num_erase_regions; i++) { 1866 if (i > NUM_ERASE_REGIONS) { 1867 printf ("%d erase regions found, only %d used\n", 1868 num_erase_regions, NUM_ERASE_REGIONS); 1869 break; 1870 } 1871 1872 tmp = le32_to_cpu(qry.erase_region_info[i]); 1873 debug("erase region %u: 0x%08lx\n", i, tmp); 1874 1875 erase_region_count = (tmp & 0xffff) + 1; 1876 tmp >>= 16; 1877 erase_region_size = 1878 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; 1879 debug ("erase_region_count = %d erase_region_size = %d\n", 1880 erase_region_count, erase_region_size); 1881 for (j = 0; j < erase_region_count; j++) { 1882 if (sect_cnt >= CFG_MAX_FLASH_SECT) { 1883 printf("ERROR: too many flash sectors\n"); 1884 break; 1885 } 1886 info->start[sect_cnt] = sector; 1887 sector += (erase_region_size * size_ratio); 1888 1889 /* 1890 * Only read protection status from 1891 * supported devices (intel...) 1892 */ 1893 switch (info->vendor) { 1894 case CFI_CMDSET_INTEL_PROG_REGIONS: 1895 case CFI_CMDSET_INTEL_EXTENDED: 1896 case CFI_CMDSET_INTEL_STANDARD: 1897 info->protect[sect_cnt] = 1898 flash_isset (info, sect_cnt, 1899 FLASH_OFFSET_PROTECT, 1900 FLASH_STATUS_PROTECT); 1901 break; 1902 default: 1903 /* default: not protected */ 1904 info->protect[sect_cnt] = 0; 1905 } 1906 1907 sect_cnt++; 1908 } 1909 } 1910 1911 info->sector_count = sect_cnt; 1912 info->size = 1 << qry.dev_size; 1913 /* multiply the size by the number of chips */ 1914 info->size *= size_ratio; 1915 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); 1916 tmp = 1 << qry.block_erase_timeout_typ; 1917 info->erase_blk_tout = tmp * 1918 (1 << qry.block_erase_timeout_max); 1919 tmp = (1 << qry.buf_write_timeout_typ) * 1920 (1 << qry.buf_write_timeout_max); 1921 1922 /* round up when converting to ms */ 1923 info->buffer_write_tout = (tmp + 999) / 1000; 1924 tmp = (1 << qry.word_write_timeout_typ) * 1925 (1 << qry.word_write_timeout_max); 1926 /* round up when converting to ms */ 1927 info->write_tout = (tmp + 999) / 1000; 1928 info->flash_id = FLASH_MAN_CFI; 1929 if ((info->interface == FLASH_CFI_X8X16) && 1930 (info->chipwidth == FLASH_CFI_BY8)) { 1931 /* XXX - Need to test on x8/x16 in parallel. */ 1932 info->portwidth >>= 1; 1933 } 1934 } 1935 1936 flash_write_cmd (info, 0, 0, info->cmd_reset); 1937 return (info->size); 1938 } 1939 1940 /*----------------------------------------------------------------------- 1941 */ 1942 unsigned long flash_init (void) 1943 { 1944 unsigned long size = 0; 1945 int i; 1946 #if defined(CFG_FLASH_AUTOPROTECT_LIST) 1947 struct apl_s { 1948 ulong start; 1949 ulong size; 1950 } apl[] = CFG_FLASH_AUTOPROTECT_LIST; 1951 #endif 1952 1953 #ifdef CFG_FLASH_PROTECTION 1954 char *s = getenv("unlock"); 1955 #endif 1956 1957 #define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CFG_FLASH_BANKS_LIST)[i]) 1958 1959 /* Init: no FLASHes known */ 1960 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { 1961 flash_info[i].flash_id = FLASH_UNKNOWN; 1962 1963 if (!flash_detect_legacy (BANK_BASE(i), i)) 1964 flash_get_size (BANK_BASE(i), i); 1965 size += flash_info[i].size; 1966 if (flash_info[i].flash_id == FLASH_UNKNOWN) { 1967 #ifndef CFG_FLASH_QUIET_TEST 1968 printf ("## Unknown FLASH on Bank %d " 1969 "- Size = 0x%08lx = %ld MB\n", 1970 i+1, flash_info[i].size, 1971 flash_info[i].size << 20); 1972 #endif /* CFG_FLASH_QUIET_TEST */ 1973 } 1974 #ifdef CFG_FLASH_PROTECTION 1975 else if ((s != NULL) && (strcmp(s, "yes") == 0)) { 1976 /* 1977 * Only the U-Boot image and it's environment 1978 * is protected, all other sectors are 1979 * unprotected (unlocked) if flash hardware 1980 * protection is used (CFG_FLASH_PROTECTION) 1981 * and the environment variable "unlock" is 1982 * set to "yes". 1983 */ 1984 if (flash_info[i].legacy_unlock) { 1985 int k; 1986 1987 /* 1988 * Disable legacy_unlock temporarily, 1989 * since flash_real_protect would 1990 * relock all other sectors again 1991 * otherwise. 1992 */ 1993 flash_info[i].legacy_unlock = 0; 1994 1995 /* 1996 * Legacy unlocking (e.g. Intel J3) -> 1997 * unlock only one sector. This will 1998 * unlock all sectors. 1999 */ 2000 flash_real_protect (&flash_info[i], 0, 0); 2001 2002 flash_info[i].legacy_unlock = 1; 2003 2004 /* 2005 * Manually mark other sectors as 2006 * unlocked (unprotected) 2007 */ 2008 for (k = 1; k < flash_info[i].sector_count; k++) 2009 flash_info[i].protect[k] = 0; 2010 } else { 2011 /* 2012 * No legancy unlocking -> unlock all sectors 2013 */ 2014 flash_protect (FLAG_PROTECT_CLEAR, 2015 flash_info[i].start[0], 2016 flash_info[i].start[0] 2017 + flash_info[i].size - 1, 2018 &flash_info[i]); 2019 } 2020 } 2021 #endif /* CFG_FLASH_PROTECTION */ 2022 } 2023 2024 /* Monitor protection ON by default */ 2025 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) 2026 flash_protect (FLAG_PROTECT_SET, 2027 CFG_MONITOR_BASE, 2028 CFG_MONITOR_BASE + monitor_flash_len - 1, 2029 flash_get_info(CFG_MONITOR_BASE)); 2030 #endif 2031 2032 /* Environment protection ON by default */ 2033 #ifdef CFG_ENV_IS_IN_FLASH 2034 flash_protect (FLAG_PROTECT_SET, 2035 CFG_ENV_ADDR, 2036 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, 2037 flash_get_info(CFG_ENV_ADDR)); 2038 #endif 2039 2040 /* Redundant environment protection ON by default */ 2041 #ifdef CFG_ENV_ADDR_REDUND 2042 flash_protect (FLAG_PROTECT_SET, 2043 CFG_ENV_ADDR_REDUND, 2044 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, 2045 flash_get_info(CFG_ENV_ADDR_REDUND)); 2046 #endif 2047 2048 #if defined(CFG_FLASH_AUTOPROTECT_LIST) 2049 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) { 2050 debug("autoprotecting from %08x to %08x\n", 2051 apl[i].start, apl[i].start + apl[i].size - 1); 2052 flash_protect (FLAG_PROTECT_SET, 2053 apl[i].start, 2054 apl[i].start + apl[i].size - 1, 2055 flash_get_info(apl[i].start)); 2056 } 2057 #endif 2058 return (size); 2059 } 2060