1 /* 2 * (C) Copyright 2002-2004 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com 4 * 5 * Copyright (C) 2003 Arabella Software Ltd. 6 * Yuli Barcohen <yuli@arabellasw.com> 7 * 8 * Copyright (C) 2004 9 * Ed Okerson 10 * 11 * Copyright (C) 2006 12 * Tolunay Orkun <listmember@orkun.us> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 /* The DEBUG define must be before common to enable debugging */ 18 /* #define DEBUG */ 19 20 #include <common.h> 21 #include <console.h> 22 #include <dm.h> 23 #include <errno.h> 24 #include <fdt_support.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include <asm/byteorder.h> 28 #include <asm/unaligned.h> 29 #include <environment.h> 30 #include <mtd/cfi_flash.h> 31 #include <watchdog.h> 32 33 /* 34 * This file implements a Common Flash Interface (CFI) driver for 35 * U-Boot. 36 * 37 * The width of the port and the width of the chips are determined at 38 * initialization. These widths are used to calculate the address for 39 * access CFI data structures. 40 * 41 * References 42 * JEDEC Standard JESD68 - Common Flash Interface (CFI) 43 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes 44 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets 45 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet 46 * AMD CFI Specification, Release 2.0 December 1, 2001 47 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte 48 * Device IDs, Publication Number 25538 Revision A, November 8, 2001 49 * 50 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between 51 * reading and writing ... (yes there is such a Hardware). 52 */ 53 54 DECLARE_GLOBAL_DATA_PTR; 55 56 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; 57 #ifdef CONFIG_FLASH_CFI_MTD 58 static uint flash_verbose = 1; 59 #else 60 #define flash_verbose 1 61 #endif 62 63 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ 64 65 /* 66 * Check if chip width is defined. If not, start detecting with 8bit. 67 */ 68 #ifndef CONFIG_SYS_FLASH_CFI_WIDTH 69 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 70 #endif 71 72 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 73 #define __maybe_weak __weak 74 #else 75 #define __maybe_weak static 76 #endif 77 78 /* 79 * 0xffff is an undefined value for the configuration register. When 80 * this value is returned, the configuration register shall not be 81 * written at all (default mode). 82 */ 83 static u16 cfi_flash_config_reg(int i) 84 { 85 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 86 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; 87 #else 88 return 0xffff; 89 #endif 90 } 91 92 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 93 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; 94 #endif 95 96 #ifdef CONFIG_CFI_FLASH /* for driver model */ 97 static void cfi_flash_init_dm(void) 98 { 99 struct udevice *dev; 100 101 cfi_flash_num_flash_banks = 0; 102 /* 103 * The uclass_first_device() will probe the first device and 104 * uclass_next_device() will probe the rest if they exist. So 105 * that cfi_flash_probe() will get called assigning the base 106 * addresses that are available. 107 */ 108 for (uclass_first_device(UCLASS_MTD, &dev); 109 dev; 110 uclass_next_device(&dev)) { 111 } 112 } 113 114 phys_addr_t cfi_flash_bank_addr(int i) 115 { 116 return flash_info[i].base; 117 } 118 #else 119 __weak phys_addr_t cfi_flash_bank_addr(int i) 120 { 121 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; 122 } 123 #endif 124 125 __weak unsigned long cfi_flash_bank_size(int i) 126 { 127 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES 128 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; 129 #else 130 return 0; 131 #endif 132 } 133 134 __maybe_weak void flash_write8(u8 value, void *addr) 135 { 136 __raw_writeb(value, addr); 137 } 138 139 __maybe_weak void flash_write16(u16 value, void *addr) 140 { 141 __raw_writew(value, addr); 142 } 143 144 __maybe_weak void flash_write32(u32 value, void *addr) 145 { 146 __raw_writel(value, addr); 147 } 148 149 __maybe_weak void flash_write64(u64 value, void *addr) 150 { 151 /* No architectures currently implement __raw_writeq() */ 152 *(volatile u64 *)addr = value; 153 } 154 155 __maybe_weak u8 flash_read8(void *addr) 156 { 157 return __raw_readb(addr); 158 } 159 160 __maybe_weak u16 flash_read16(void *addr) 161 { 162 return __raw_readw(addr); 163 } 164 165 __maybe_weak u32 flash_read32(void *addr) 166 { 167 return __raw_readl(addr); 168 } 169 170 __maybe_weak u64 flash_read64(void *addr) 171 { 172 /* No architectures currently implement __raw_readq() */ 173 return *(volatile u64 *)addr; 174 } 175 176 /*----------------------------------------------------------------------- 177 */ 178 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \ 179 (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) 180 static flash_info_t *flash_get_info(ulong base) 181 { 182 int i; 183 flash_info_t *info; 184 185 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { 186 info = &flash_info[i]; 187 if (info->size && info->start[0] <= base && 188 base <= info->start[0] + info->size - 1) 189 return info; 190 } 191 192 return NULL; 193 } 194 #endif 195 196 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) 197 { 198 if (sect != (info->sector_count - 1)) 199 return info->start[sect + 1] - info->start[sect]; 200 else 201 return info->start[0] + info->size - info->start[sect]; 202 } 203 204 /*----------------------------------------------------------------------- 205 * create an address based on the offset and the port width 206 */ 207 static inline void * 208 flash_map(flash_info_t *info, flash_sect_t sect, uint offset) 209 { 210 unsigned int byte_offset = offset * info->portwidth; 211 212 return (void *)(info->start[sect] + byte_offset); 213 } 214 215 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, 216 unsigned int offset, void *addr) 217 { 218 } 219 220 /*----------------------------------------------------------------------- 221 * make a proper sized command based on the port and chip widths 222 */ 223 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) 224 { 225 int i; 226 int cword_offset; 227 int cp_offset; 228 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 229 u32 cmd_le = cpu_to_le32(cmd); 230 #endif 231 uchar val; 232 uchar *cp = (uchar *) cmdbuf; 233 234 for (i = info->portwidth; i > 0; i--) { 235 cword_offset = (info->portwidth - i) % info->chipwidth; 236 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 237 cp_offset = info->portwidth - i; 238 val = *((uchar *)&cmd_le + cword_offset); 239 #else 240 cp_offset = i - 1; 241 val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1); 242 #endif 243 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; 244 } 245 } 246 247 #ifdef DEBUG 248 /*----------------------------------------------------------------------- 249 * Debug support 250 */ 251 static void print_longlong(char *str, unsigned long long data) 252 { 253 int i; 254 char *cp; 255 256 cp = (char *)&data; 257 for (i = 0; i < 8; i++) 258 sprintf(&str[i * 2], "%2.2x", *cp++); 259 } 260 261 static void flash_printqry(struct cfi_qry *qry) 262 { 263 u8 *p = (u8 *)qry; 264 int x, y; 265 266 for (x = 0; x < sizeof(struct cfi_qry); x += 16) { 267 debug("%02x : ", x); 268 for (y = 0; y < 16; y++) 269 debug("%2.2x ", p[x + y]); 270 debug(" "); 271 for (y = 0; y < 16; y++) { 272 unsigned char c = p[x + y]; 273 274 if (c >= 0x20 && c <= 0x7e) 275 debug("%c", c); 276 else 277 debug("."); 278 } 279 debug("\n"); 280 } 281 } 282 #endif 283 284 /*----------------------------------------------------------------------- 285 * read a character at a port width address 286 */ 287 static inline uchar flash_read_uchar(flash_info_t *info, uint offset) 288 { 289 uchar *cp; 290 uchar retval; 291 292 cp = flash_map(info, 0, offset); 293 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 294 retval = flash_read8(cp); 295 #else 296 retval = flash_read8(cp + info->portwidth - 1); 297 #endif 298 flash_unmap(info, 0, offset, cp); 299 return retval; 300 } 301 302 /*----------------------------------------------------------------------- 303 * read a word at a port width address, assume 16bit bus 304 */ 305 static inline ushort flash_read_word(flash_info_t *info, uint offset) 306 { 307 ushort *addr, retval; 308 309 addr = flash_map(info, 0, offset); 310 retval = flash_read16(addr); 311 flash_unmap(info, 0, offset, addr); 312 return retval; 313 } 314 315 /*----------------------------------------------------------------------- 316 * read a long word by picking the least significant byte of each maximum 317 * port size word. Swap for ppc format. 318 */ 319 static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, 320 uint offset) 321 { 322 uchar *addr; 323 ulong retval; 324 325 #ifdef DEBUG 326 int x; 327 #endif 328 addr = flash_map(info, sect, offset); 329 330 #ifdef DEBUG 331 debug("long addr is at %p info->portwidth = %d\n", addr, 332 info->portwidth); 333 for (x = 0; x < 4 * info->portwidth; x++) 334 debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); 335 #endif 336 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 337 retval = ((flash_read8(addr) << 16) | 338 (flash_read8(addr + info->portwidth) << 24) | 339 (flash_read8(addr + 2 * info->portwidth)) | 340 (flash_read8(addr + 3 * info->portwidth) << 8)); 341 #else 342 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | 343 (flash_read8(addr + info->portwidth - 1) << 16) | 344 (flash_read8(addr + 4 * info->portwidth - 1) << 8) | 345 (flash_read8(addr + 3 * info->portwidth - 1))); 346 #endif 347 flash_unmap(info, sect, offset, addr); 348 349 return retval; 350 } 351 352 /* 353 * Write a proper sized command to the correct address 354 */ 355 static void flash_write_cmd(flash_info_t *info, flash_sect_t sect, 356 uint offset, u32 cmd) 357 { 358 void *addr; 359 cfiword_t cword; 360 361 addr = flash_map(info, sect, offset); 362 flash_make_cmd(info, cmd, &cword); 363 switch (info->portwidth) { 364 case FLASH_CFI_8BIT: 365 debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, 366 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 367 flash_write8(cword.w8, addr); 368 break; 369 case FLASH_CFI_16BIT: 370 debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, 371 cmd, cword.w16, 372 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 373 flash_write16(cword.w16, addr); 374 break; 375 case FLASH_CFI_32BIT: 376 debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr, 377 cmd, cword.w32, 378 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 379 flash_write32(cword.w32, addr); 380 break; 381 case FLASH_CFI_64BIT: 382 #ifdef DEBUG 383 { 384 char str[20]; 385 386 print_longlong(str, cword.w64); 387 388 debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n", 389 addr, cmd, str, 390 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 391 } 392 #endif 393 flash_write64(cword.w64, addr); 394 break; 395 } 396 397 /* Ensure all the instructions are fully finished */ 398 sync(); 399 400 flash_unmap(info, sect, offset, addr); 401 } 402 403 static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect) 404 { 405 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); 406 flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); 407 } 408 409 /*----------------------------------------------------------------------- 410 */ 411 static int flash_isequal(flash_info_t *info, flash_sect_t sect, uint offset, 412 uchar cmd) 413 { 414 void *addr; 415 cfiword_t cword; 416 int retval; 417 418 addr = flash_map(info, sect, offset); 419 flash_make_cmd(info, cmd, &cword); 420 421 debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr); 422 switch (info->portwidth) { 423 case FLASH_CFI_8BIT: 424 debug("is= %x %x\n", flash_read8(addr), cword.w8); 425 retval = (flash_read8(addr) == cword.w8); 426 break; 427 case FLASH_CFI_16BIT: 428 debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16); 429 retval = (flash_read16(addr) == cword.w16); 430 break; 431 case FLASH_CFI_32BIT: 432 debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32); 433 retval = (flash_read32(addr) == cword.w32); 434 break; 435 case FLASH_CFI_64BIT: 436 #ifdef DEBUG 437 { 438 char str1[20]; 439 char str2[20]; 440 441 print_longlong(str1, flash_read64(addr)); 442 print_longlong(str2, cword.w64); 443 debug("is= %s %s\n", str1, str2); 444 } 445 #endif 446 retval = (flash_read64(addr) == cword.w64); 447 break; 448 default: 449 retval = 0; 450 break; 451 } 452 flash_unmap(info, sect, offset, addr); 453 454 return retval; 455 } 456 457 /*----------------------------------------------------------------------- 458 */ 459 static int flash_isset(flash_info_t *info, flash_sect_t sect, uint offset, 460 uchar cmd) 461 { 462 void *addr; 463 cfiword_t cword; 464 int retval; 465 466 addr = flash_map(info, sect, offset); 467 flash_make_cmd(info, cmd, &cword); 468 switch (info->portwidth) { 469 case FLASH_CFI_8BIT: 470 retval = ((flash_read8(addr) & cword.w8) == cword.w8); 471 break; 472 case FLASH_CFI_16BIT: 473 retval = ((flash_read16(addr) & cword.w16) == cword.w16); 474 break; 475 case FLASH_CFI_32BIT: 476 retval = ((flash_read32(addr) & cword.w32) == cword.w32); 477 break; 478 case FLASH_CFI_64BIT: 479 retval = ((flash_read64(addr) & cword.w64) == cword.w64); 480 break; 481 default: 482 retval = 0; 483 break; 484 } 485 flash_unmap(info, sect, offset, addr); 486 487 return retval; 488 } 489 490 /*----------------------------------------------------------------------- 491 */ 492 static int flash_toggle(flash_info_t *info, flash_sect_t sect, uint offset, 493 uchar cmd) 494 { 495 u8 *addr; 496 cfiword_t cword; 497 int retval; 498 499 addr = flash_map(info, sect, offset); 500 flash_make_cmd(info, cmd, &cword); 501 switch (info->portwidth) { 502 case FLASH_CFI_8BIT: 503 retval = flash_read8(addr) != flash_read8(addr); 504 break; 505 case FLASH_CFI_16BIT: 506 retval = flash_read16(addr) != flash_read16(addr); 507 break; 508 case FLASH_CFI_32BIT: 509 retval = flash_read32(addr) != flash_read32(addr); 510 break; 511 case FLASH_CFI_64BIT: 512 retval = ((flash_read32(addr) != flash_read32(addr)) || 513 (flash_read32(addr + 4) != flash_read32(addr + 4))); 514 break; 515 default: 516 retval = 0; 517 break; 518 } 519 flash_unmap(info, sect, offset, addr); 520 521 return retval; 522 } 523 524 /* 525 * flash_is_busy - check to see if the flash is busy 526 * 527 * This routine checks the status of the chip and returns true if the 528 * chip is busy. 529 */ 530 static int flash_is_busy(flash_info_t *info, flash_sect_t sect) 531 { 532 int retval; 533 534 switch (info->vendor) { 535 case CFI_CMDSET_INTEL_PROG_REGIONS: 536 case CFI_CMDSET_INTEL_STANDARD: 537 case CFI_CMDSET_INTEL_EXTENDED: 538 retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE); 539 break; 540 case CFI_CMDSET_AMD_STANDARD: 541 case CFI_CMDSET_AMD_EXTENDED: 542 #ifdef CONFIG_FLASH_CFI_LEGACY 543 case CFI_CMDSET_AMD_LEGACY: 544 #endif 545 if (info->sr_supported) { 546 flash_write_cmd(info, sect, info->addr_unlock1, 547 FLASH_CMD_READ_STATUS); 548 retval = !flash_isset(info, sect, 0, 549 FLASH_STATUS_DONE); 550 } else { 551 retval = flash_toggle(info, sect, 0, 552 AMD_STATUS_TOGGLE); 553 } 554 555 break; 556 default: 557 retval = 0; 558 } 559 debug("%s: %d\n", __func__, retval); 560 return retval; 561 } 562 563 /*----------------------------------------------------------------------- 564 * wait for XSR.7 to be set. Time out with an error if it does not. 565 * This routine does not set the flash to read-array mode. 566 */ 567 static int flash_status_check(flash_info_t *info, flash_sect_t sector, 568 ulong tout, char *prompt) 569 { 570 ulong start; 571 572 #if CONFIG_SYS_HZ != 1000 573 /* Avoid overflow for large HZ */ 574 if ((ulong)CONFIG_SYS_HZ > 100000) 575 tout *= (ulong)CONFIG_SYS_HZ / 1000; 576 else 577 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 578 #endif 579 580 /* Wait for command completion */ 581 #ifdef CONFIG_SYS_LOW_RES_TIMER 582 reset_timer(); 583 #endif 584 start = get_timer(0); 585 WATCHDOG_RESET(); 586 while (flash_is_busy(info, sector)) { 587 if (get_timer(start) > tout) { 588 printf("Flash %s timeout at address %lx data %lx\n", 589 prompt, info->start[sector], 590 flash_read_long(info, sector, 0)); 591 flash_write_cmd(info, sector, 0, info->cmd_reset); 592 udelay(1); 593 return ERR_TIMEOUT; 594 } 595 udelay(1); /* also triggers watchdog */ 596 } 597 return ERR_OK; 598 } 599 600 /*----------------------------------------------------------------------- 601 * Wait for XSR.7 to be set, if it times out print an error, otherwise 602 * do a full status check. 603 * 604 * This routine sets the flash to read-array mode. 605 */ 606 static int flash_full_status_check(flash_info_t *info, flash_sect_t sector, 607 ulong tout, char *prompt) 608 { 609 int retcode; 610 611 retcode = flash_status_check(info, sector, tout, prompt); 612 switch (info->vendor) { 613 case CFI_CMDSET_INTEL_PROG_REGIONS: 614 case CFI_CMDSET_INTEL_EXTENDED: 615 case CFI_CMDSET_INTEL_STANDARD: 616 if (retcode == ERR_OK && 617 !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { 618 retcode = ERR_INVAL; 619 printf("Flash %s error at address %lx\n", prompt, 620 info->start[sector]); 621 if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | 622 FLASH_STATUS_PSLBS)) { 623 puts("Command Sequence Error.\n"); 624 } else if (flash_isset(info, sector, 0, 625 FLASH_STATUS_ECLBS)) { 626 puts("Block Erase Error.\n"); 627 retcode = ERR_NOT_ERASED; 628 } else if (flash_isset(info, sector, 0, 629 FLASH_STATUS_PSLBS)) { 630 puts("Locking Error\n"); 631 } 632 if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { 633 puts("Block locked.\n"); 634 retcode = ERR_PROTECTED; 635 } 636 if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) 637 puts("Vpp Low Error.\n"); 638 } 639 flash_write_cmd(info, sector, 0, info->cmd_reset); 640 udelay(1); 641 break; 642 default: 643 break; 644 } 645 return retcode; 646 } 647 648 static int use_flash_status_poll(flash_info_t *info) 649 { 650 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 651 if (info->vendor == CFI_CMDSET_AMD_EXTENDED || 652 info->vendor == CFI_CMDSET_AMD_STANDARD) 653 return 1; 654 #endif 655 return 0; 656 } 657 658 static int flash_status_poll(flash_info_t *info, void *src, void *dst, 659 ulong tout, char *prompt) 660 { 661 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 662 ulong start; 663 int ready; 664 665 #if CONFIG_SYS_HZ != 1000 666 /* Avoid overflow for large HZ */ 667 if ((ulong)CONFIG_SYS_HZ > 100000) 668 tout *= (ulong)CONFIG_SYS_HZ / 1000; 669 else 670 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 671 #endif 672 673 /* Wait for command completion */ 674 #ifdef CONFIG_SYS_LOW_RES_TIMER 675 reset_timer(); 676 #endif 677 start = get_timer(0); 678 WATCHDOG_RESET(); 679 while (1) { 680 switch (info->portwidth) { 681 case FLASH_CFI_8BIT: 682 ready = flash_read8(dst) == flash_read8(src); 683 break; 684 case FLASH_CFI_16BIT: 685 ready = flash_read16(dst) == flash_read16(src); 686 break; 687 case FLASH_CFI_32BIT: 688 ready = flash_read32(dst) == flash_read32(src); 689 break; 690 case FLASH_CFI_64BIT: 691 ready = flash_read64(dst) == flash_read64(src); 692 break; 693 default: 694 ready = 0; 695 break; 696 } 697 if (ready) 698 break; 699 if (get_timer(start) > tout) { 700 printf("Flash %s timeout at address %lx data %lx\n", 701 prompt, (ulong)dst, (ulong)flash_read8(dst)); 702 return ERR_TIMEOUT; 703 } 704 udelay(1); /* also triggers watchdog */ 705 } 706 #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ 707 return ERR_OK; 708 } 709 710 /*----------------------------------------------------------------------- 711 */ 712 static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) 713 { 714 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 715 unsigned short w; 716 unsigned int l; 717 unsigned long long ll; 718 #endif 719 720 switch (info->portwidth) { 721 case FLASH_CFI_8BIT: 722 cword->w8 = c; 723 break; 724 case FLASH_CFI_16BIT: 725 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 726 w = c; 727 w <<= 8; 728 cword->w16 = (cword->w16 >> 8) | w; 729 #else 730 cword->w16 = (cword->w16 << 8) | c; 731 #endif 732 break; 733 case FLASH_CFI_32BIT: 734 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 735 l = c; 736 l <<= 24; 737 cword->w32 = (cword->w32 >> 8) | l; 738 #else 739 cword->w32 = (cword->w32 << 8) | c; 740 #endif 741 break; 742 case FLASH_CFI_64BIT: 743 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 744 ll = c; 745 ll <<= 56; 746 cword->w64 = (cword->w64 >> 8) | ll; 747 #else 748 cword->w64 = (cword->w64 << 8) | c; 749 #endif 750 break; 751 } 752 } 753 754 /* 755 * Loop through the sector table starting from the previously found sector. 756 * Searches forwards or backwards, dependent on the passed address. 757 */ 758 static flash_sect_t find_sector(flash_info_t *info, ulong addr) 759 { 760 static flash_sect_t saved_sector; /* previously found sector */ 761 static flash_info_t *saved_info; /* previously used flash bank */ 762 flash_sect_t sector = saved_sector; 763 764 if (info != saved_info || sector >= info->sector_count) 765 sector = 0; 766 767 while ((sector < info->sector_count - 1) && 768 (info->start[sector] < addr)) 769 sector++; 770 while ((info->start[sector] > addr) && (sector > 0)) 771 /* 772 * also decrements the sector in case of an overshot 773 * in the first loop 774 */ 775 sector--; 776 777 saved_sector = sector; 778 saved_info = info; 779 return sector; 780 } 781 782 /*----------------------------------------------------------------------- 783 */ 784 static int flash_write_cfiword(flash_info_t *info, ulong dest, cfiword_t cword) 785 { 786 void *dstaddr = (void *)dest; 787 int flag; 788 flash_sect_t sect = 0; 789 char sect_found = 0; 790 791 /* Check if Flash is (sufficiently) erased */ 792 switch (info->portwidth) { 793 case FLASH_CFI_8BIT: 794 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8); 795 break; 796 case FLASH_CFI_16BIT: 797 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16); 798 break; 799 case FLASH_CFI_32BIT: 800 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32); 801 break; 802 case FLASH_CFI_64BIT: 803 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64); 804 break; 805 default: 806 flag = 0; 807 break; 808 } 809 if (!flag) 810 return ERR_NOT_ERASED; 811 812 /* Disable interrupts which might cause a timeout here */ 813 flag = disable_interrupts(); 814 815 switch (info->vendor) { 816 case CFI_CMDSET_INTEL_PROG_REGIONS: 817 case CFI_CMDSET_INTEL_EXTENDED: 818 case CFI_CMDSET_INTEL_STANDARD: 819 flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); 820 flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); 821 break; 822 case CFI_CMDSET_AMD_EXTENDED: 823 case CFI_CMDSET_AMD_STANDARD: 824 sect = find_sector(info, dest); 825 flash_unlock_seq(info, sect); 826 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE); 827 sect_found = 1; 828 break; 829 #ifdef CONFIG_FLASH_CFI_LEGACY 830 case CFI_CMDSET_AMD_LEGACY: 831 sect = find_sector(info, dest); 832 flash_unlock_seq(info, 0); 833 flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE); 834 sect_found = 1; 835 break; 836 #endif 837 } 838 839 switch (info->portwidth) { 840 case FLASH_CFI_8BIT: 841 flash_write8(cword.w8, dstaddr); 842 break; 843 case FLASH_CFI_16BIT: 844 flash_write16(cword.w16, dstaddr); 845 break; 846 case FLASH_CFI_32BIT: 847 flash_write32(cword.w32, dstaddr); 848 break; 849 case FLASH_CFI_64BIT: 850 flash_write64(cword.w64, dstaddr); 851 break; 852 } 853 854 /* re-enable interrupts if necessary */ 855 if (flag) 856 enable_interrupts(); 857 858 if (!sect_found) 859 sect = find_sector(info, dest); 860 861 if (use_flash_status_poll(info)) 862 return flash_status_poll(info, &cword, dstaddr, 863 info->write_tout, "write"); 864 else 865 return flash_full_status_check(info, sect, 866 info->write_tout, "write"); 867 } 868 869 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 870 871 static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, 872 int len) 873 { 874 flash_sect_t sector; 875 int cnt; 876 int retcode; 877 u8 *src = cp; 878 u8 *dst = (u8 *)dest; 879 u8 *dst2 = dst; 880 int flag = 1; 881 uint offset = 0; 882 unsigned int shift; 883 uchar write_cmd; 884 885 switch (info->portwidth) { 886 case FLASH_CFI_8BIT: 887 shift = 0; 888 break; 889 case FLASH_CFI_16BIT: 890 shift = 1; 891 break; 892 case FLASH_CFI_32BIT: 893 shift = 2; 894 break; 895 case FLASH_CFI_64BIT: 896 shift = 3; 897 break; 898 default: 899 retcode = ERR_INVAL; 900 goto out_unmap; 901 } 902 903 cnt = len >> shift; 904 905 while ((cnt-- > 0) && (flag == 1)) { 906 switch (info->portwidth) { 907 case FLASH_CFI_8BIT: 908 flag = ((flash_read8(dst2) & flash_read8(src)) == 909 flash_read8(src)); 910 src += 1, dst2 += 1; 911 break; 912 case FLASH_CFI_16BIT: 913 flag = ((flash_read16(dst2) & flash_read16(src)) == 914 flash_read16(src)); 915 src += 2, dst2 += 2; 916 break; 917 case FLASH_CFI_32BIT: 918 flag = ((flash_read32(dst2) & flash_read32(src)) == 919 flash_read32(src)); 920 src += 4, dst2 += 4; 921 break; 922 case FLASH_CFI_64BIT: 923 flag = ((flash_read64(dst2) & flash_read64(src)) == 924 flash_read64(src)); 925 src += 8, dst2 += 8; 926 break; 927 } 928 } 929 if (!flag) { 930 retcode = ERR_NOT_ERASED; 931 goto out_unmap; 932 } 933 934 src = cp; 935 sector = find_sector(info, dest); 936 937 switch (info->vendor) { 938 case CFI_CMDSET_INTEL_PROG_REGIONS: 939 case CFI_CMDSET_INTEL_STANDARD: 940 case CFI_CMDSET_INTEL_EXTENDED: 941 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? 942 FLASH_CMD_WRITE_BUFFER_PROG : 943 FLASH_CMD_WRITE_TO_BUFFER; 944 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 945 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 946 flash_write_cmd(info, sector, 0, write_cmd); 947 retcode = flash_status_check(info, sector, 948 info->buffer_write_tout, 949 "write to buffer"); 950 if (retcode == ERR_OK) { 951 /* reduce the number of loops by the width of 952 * the port 953 */ 954 cnt = len >> shift; 955 flash_write_cmd(info, sector, 0, cnt - 1); 956 while (cnt-- > 0) { 957 switch (info->portwidth) { 958 case FLASH_CFI_8BIT: 959 flash_write8(flash_read8(src), dst); 960 src += 1, dst += 1; 961 break; 962 case FLASH_CFI_16BIT: 963 flash_write16(flash_read16(src), dst); 964 src += 2, dst += 2; 965 break; 966 case FLASH_CFI_32BIT: 967 flash_write32(flash_read32(src), dst); 968 src += 4, dst += 4; 969 break; 970 case FLASH_CFI_64BIT: 971 flash_write64(flash_read64(src), dst); 972 src += 8, dst += 8; 973 break; 974 default: 975 retcode = ERR_INVAL; 976 goto out_unmap; 977 } 978 } 979 flash_write_cmd(info, sector, 0, 980 FLASH_CMD_WRITE_BUFFER_CONFIRM); 981 retcode = flash_full_status_check( 982 info, sector, info->buffer_write_tout, 983 "buffer write"); 984 } 985 986 break; 987 988 case CFI_CMDSET_AMD_STANDARD: 989 case CFI_CMDSET_AMD_EXTENDED: 990 flash_unlock_seq(info, sector); 991 992 #ifdef CONFIG_FLASH_SPANSION_S29WS_N 993 offset = ((unsigned long)dst - info->start[sector]) >> shift; 994 #endif 995 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); 996 cnt = len >> shift; 997 flash_write_cmd(info, sector, offset, cnt - 1); 998 999 switch (info->portwidth) { 1000 case FLASH_CFI_8BIT: 1001 while (cnt-- > 0) { 1002 flash_write8(flash_read8(src), dst); 1003 src += 1, dst += 1; 1004 } 1005 break; 1006 case FLASH_CFI_16BIT: 1007 while (cnt-- > 0) { 1008 flash_write16(flash_read16(src), dst); 1009 src += 2, dst += 2; 1010 } 1011 break; 1012 case FLASH_CFI_32BIT: 1013 while (cnt-- > 0) { 1014 flash_write32(flash_read32(src), dst); 1015 src += 4, dst += 4; 1016 } 1017 break; 1018 case FLASH_CFI_64BIT: 1019 while (cnt-- > 0) { 1020 flash_write64(flash_read64(src), dst); 1021 src += 8, dst += 8; 1022 } 1023 break; 1024 default: 1025 retcode = ERR_INVAL; 1026 goto out_unmap; 1027 } 1028 1029 flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); 1030 if (use_flash_status_poll(info)) 1031 retcode = flash_status_poll(info, src - (1 << shift), 1032 dst - (1 << shift), 1033 info->buffer_write_tout, 1034 "buffer write"); 1035 else 1036 retcode = flash_full_status_check(info, sector, 1037 info->buffer_write_tout, 1038 "buffer write"); 1039 break; 1040 1041 default: 1042 debug("Unknown Command Set\n"); 1043 retcode = ERR_INVAL; 1044 break; 1045 } 1046 1047 out_unmap: 1048 return retcode; 1049 } 1050 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1051 1052 /*----------------------------------------------------------------------- 1053 */ 1054 int flash_erase(flash_info_t *info, int s_first, int s_last) 1055 { 1056 int rcode = 0; 1057 int prot; 1058 flash_sect_t sect; 1059 int st; 1060 1061 if (info->flash_id != FLASH_MAN_CFI) { 1062 puts("Can't erase unknown flash type - aborted\n"); 1063 return 1; 1064 } 1065 if (s_first < 0 || s_first > s_last) { 1066 puts("- no sectors to erase\n"); 1067 return 1; 1068 } 1069 1070 prot = 0; 1071 for (sect = s_first; sect <= s_last; ++sect) 1072 if (info->protect[sect]) 1073 prot++; 1074 if (prot) { 1075 printf("- Warning: %d protected sectors will not be erased!\n", 1076 prot); 1077 } else if (flash_verbose) { 1078 putc('\n'); 1079 } 1080 1081 for (sect = s_first; sect <= s_last; sect++) { 1082 if (ctrlc()) { 1083 printf("\n"); 1084 return 1; 1085 } 1086 1087 if (info->protect[sect] == 0) { /* not protected */ 1088 #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE 1089 int k; 1090 int size; 1091 int erased; 1092 u32 *flash; 1093 1094 /* 1095 * Check if whole sector is erased 1096 */ 1097 size = flash_sector_size(info, sect); 1098 erased = 1; 1099 flash = (u32 *)info->start[sect]; 1100 /* divide by 4 for longword access */ 1101 size = size >> 2; 1102 for (k = 0; k < size; k++) { 1103 if (flash_read32(flash++) != 0xffffffff) { 1104 erased = 0; 1105 break; 1106 } 1107 } 1108 if (erased) { 1109 if (flash_verbose) 1110 putc(','); 1111 continue; 1112 } 1113 #endif 1114 switch (info->vendor) { 1115 case CFI_CMDSET_INTEL_PROG_REGIONS: 1116 case CFI_CMDSET_INTEL_STANDARD: 1117 case CFI_CMDSET_INTEL_EXTENDED: 1118 flash_write_cmd(info, sect, 0, 1119 FLASH_CMD_CLEAR_STATUS); 1120 flash_write_cmd(info, sect, 0, 1121 FLASH_CMD_BLOCK_ERASE); 1122 flash_write_cmd(info, sect, 0, 1123 FLASH_CMD_ERASE_CONFIRM); 1124 break; 1125 case CFI_CMDSET_AMD_STANDARD: 1126 case CFI_CMDSET_AMD_EXTENDED: 1127 flash_unlock_seq(info, sect); 1128 flash_write_cmd(info, sect, 1129 info->addr_unlock1, 1130 AMD_CMD_ERASE_START); 1131 flash_unlock_seq(info, sect); 1132 flash_write_cmd(info, sect, 0, 1133 info->cmd_erase_sector); 1134 break; 1135 #ifdef CONFIG_FLASH_CFI_LEGACY 1136 case CFI_CMDSET_AMD_LEGACY: 1137 flash_unlock_seq(info, 0); 1138 flash_write_cmd(info, 0, info->addr_unlock1, 1139 AMD_CMD_ERASE_START); 1140 flash_unlock_seq(info, 0); 1141 flash_write_cmd(info, sect, 0, 1142 AMD_CMD_ERASE_SECTOR); 1143 break; 1144 #endif 1145 default: 1146 debug("Unknown flash vendor %d\n", 1147 info->vendor); 1148 break; 1149 } 1150 1151 if (use_flash_status_poll(info)) { 1152 cfiword_t cword; 1153 void *dest; 1154 1155 cword.w64 = 0xffffffffffffffffULL; 1156 dest = flash_map(info, sect, 0); 1157 st = flash_status_poll(info, &cword, dest, 1158 info->erase_blk_tout, 1159 "erase"); 1160 flash_unmap(info, sect, 0, dest); 1161 } else { 1162 st = flash_full_status_check(info, sect, 1163 info->erase_blk_tout, 1164 "erase"); 1165 } 1166 1167 if (st) 1168 rcode = 1; 1169 else if (flash_verbose) 1170 putc('.'); 1171 } 1172 } 1173 1174 if (flash_verbose) 1175 puts(" done\n"); 1176 1177 return rcode; 1178 } 1179 1180 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1181 static int sector_erased(flash_info_t *info, int i) 1182 { 1183 int k; 1184 int size; 1185 u32 *flash; 1186 1187 /* 1188 * Check if whole sector is erased 1189 */ 1190 size = flash_sector_size(info, i); 1191 flash = (u32 *)info->start[i]; 1192 /* divide by 4 for longword access */ 1193 size = size >> 2; 1194 1195 for (k = 0; k < size; k++) { 1196 if (flash_read32(flash++) != 0xffffffff) 1197 return 0; /* not erased */ 1198 } 1199 1200 return 1; /* erased */ 1201 } 1202 #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ 1203 1204 void flash_print_info(flash_info_t *info) 1205 { 1206 int i; 1207 1208 if (info->flash_id != FLASH_MAN_CFI) { 1209 puts("missing or unknown FLASH type\n"); 1210 return; 1211 } 1212 1213 printf("%s flash (%d x %d)", 1214 info->name, 1215 (info->portwidth << 3), (info->chipwidth << 3)); 1216 if (info->size < 1024 * 1024) 1217 printf(" Size: %ld kB in %d Sectors\n", 1218 info->size >> 10, info->sector_count); 1219 else 1220 printf(" Size: %ld MB in %d Sectors\n", 1221 info->size >> 20, info->sector_count); 1222 printf(" "); 1223 switch (info->vendor) { 1224 case CFI_CMDSET_INTEL_PROG_REGIONS: 1225 printf("Intel Prog Regions"); 1226 break; 1227 case CFI_CMDSET_INTEL_STANDARD: 1228 printf("Intel Standard"); 1229 break; 1230 case CFI_CMDSET_INTEL_EXTENDED: 1231 printf("Intel Extended"); 1232 break; 1233 case CFI_CMDSET_AMD_STANDARD: 1234 printf("AMD Standard"); 1235 break; 1236 case CFI_CMDSET_AMD_EXTENDED: 1237 printf("AMD Extended"); 1238 break; 1239 #ifdef CONFIG_FLASH_CFI_LEGACY 1240 case CFI_CMDSET_AMD_LEGACY: 1241 printf("AMD Legacy"); 1242 break; 1243 #endif 1244 default: 1245 printf("Unknown (%d)", info->vendor); 1246 break; 1247 } 1248 printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x", 1249 info->manufacturer_id); 1250 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1251 info->device_id); 1252 if ((info->device_id & 0xff) == 0x7E) { 1253 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1254 info->device_id2); 1255 } 1256 if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock) 1257 printf("\n Advanced Sector Protection (PPB) enabled"); 1258 printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n", 1259 info->erase_blk_tout, info->write_tout); 1260 if (info->buffer_size > 1) { 1261 printf(" Buffer write timeout: %ld ms, ", 1262 info->buffer_write_tout); 1263 printf("buffer size: %d bytes\n", info->buffer_size); 1264 } 1265 1266 puts("\n Sector Start Addresses:"); 1267 for (i = 0; i < info->sector_count; ++i) { 1268 if (ctrlc()) 1269 break; 1270 if ((i % 5) == 0) 1271 putc('\n'); 1272 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1273 /* print empty and read-only info */ 1274 printf(" %08lX %c %s ", 1275 info->start[i], 1276 sector_erased(info, i) ? 'E' : ' ', 1277 info->protect[i] ? "RO" : " "); 1278 #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ 1279 printf(" %08lX %s ", 1280 info->start[i], 1281 info->protect[i] ? "RO" : " "); 1282 #endif 1283 } 1284 putc('\n'); 1285 } 1286 1287 /*----------------------------------------------------------------------- 1288 * This is used in a few places in write_buf() to show programming 1289 * progress. Making it a function is nasty because it needs to do side 1290 * effect updates to digit and dots. Repeated code is nasty too, so 1291 * we define it once here. 1292 */ 1293 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1294 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ 1295 if (flash_verbose) { \ 1296 dots -= dots_sub; \ 1297 if (scale > 0 && dots <= 0) { \ 1298 if ((digit % 5) == 0) \ 1299 printf("%d", digit / 5); \ 1300 else \ 1301 putc('.'); \ 1302 digit--; \ 1303 dots += scale; \ 1304 } \ 1305 } 1306 #else 1307 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) 1308 #endif 1309 1310 /*----------------------------------------------------------------------- 1311 * Copy memory to flash, returns: 1312 * 0 - OK 1313 * 1 - write timeout 1314 * 2 - Flash not erased 1315 */ 1316 int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) 1317 { 1318 ulong wp; 1319 uchar *p; 1320 int aln; 1321 cfiword_t cword; 1322 int i, rc; 1323 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1324 int buffered_size; 1325 #endif 1326 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1327 int digit = CONFIG_FLASH_SHOW_PROGRESS; 1328 int scale = 0; 1329 int dots = 0; 1330 1331 /* 1332 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. 1333 */ 1334 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { 1335 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / 1336 CONFIG_FLASH_SHOW_PROGRESS); 1337 } 1338 #endif 1339 1340 /* get lower aligned address */ 1341 wp = (addr & ~(info->portwidth - 1)); 1342 1343 /* handle unaligned start */ 1344 aln = addr - wp; 1345 if (aln != 0) { 1346 cword.w32 = 0; 1347 p = (uchar *)wp; 1348 for (i = 0; i < aln; ++i) 1349 flash_add_byte(info, &cword, flash_read8(p + i)); 1350 1351 for (; (i < info->portwidth) && (cnt > 0); i++) { 1352 flash_add_byte(info, &cword, *src++); 1353 cnt--; 1354 } 1355 for (; (cnt == 0) && (i < info->portwidth); ++i) 1356 flash_add_byte(info, &cword, flash_read8(p + i)); 1357 1358 rc = flash_write_cfiword(info, wp, cword); 1359 if (rc != 0) 1360 return rc; 1361 1362 wp += i; 1363 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1364 } 1365 1366 /* handle the aligned part */ 1367 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1368 buffered_size = (info->portwidth / info->chipwidth); 1369 buffered_size *= info->buffer_size; 1370 while (cnt >= info->portwidth) { 1371 /* prohibit buffer write when buffer_size is 1 */ 1372 if (info->buffer_size == 1) { 1373 cword.w32 = 0; 1374 for (i = 0; i < info->portwidth; i++) 1375 flash_add_byte(info, &cword, *src++); 1376 rc = flash_write_cfiword(info, wp, cword); 1377 if (rc != 0) 1378 return rc; 1379 wp += info->portwidth; 1380 cnt -= info->portwidth; 1381 continue; 1382 } 1383 1384 /* write buffer until next buffered_size aligned boundary */ 1385 i = buffered_size - (wp % buffered_size); 1386 if (i > cnt) 1387 i = cnt; 1388 rc = flash_write_cfibuffer(info, wp, src, i); 1389 if (rc != ERR_OK) 1390 return rc; 1391 i -= i & (info->portwidth - 1); 1392 wp += i; 1393 src += i; 1394 cnt -= i; 1395 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1396 /* Only check every once in a while */ 1397 if ((cnt & 0xFFFF) < buffered_size && ctrlc()) 1398 return ERR_ABORTED; 1399 } 1400 #else 1401 while (cnt >= info->portwidth) { 1402 cword.w32 = 0; 1403 for (i = 0; i < info->portwidth; i++) 1404 flash_add_byte(info, &cword, *src++); 1405 rc = flash_write_cfiword(info, wp, cword); 1406 if (rc != 0) 1407 return rc; 1408 wp += info->portwidth; 1409 cnt -= info->portwidth; 1410 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); 1411 /* Only check every once in a while */ 1412 if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) 1413 return ERR_ABORTED; 1414 } 1415 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1416 1417 if (cnt == 0) 1418 return (0); 1419 1420 /* 1421 * handle unaligned tail bytes 1422 */ 1423 cword.w32 = 0; 1424 p = (uchar *)wp; 1425 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { 1426 flash_add_byte(info, &cword, *src++); 1427 --cnt; 1428 } 1429 for (; i < info->portwidth; ++i) 1430 flash_add_byte(info, &cword, flash_read8(p + i)); 1431 1432 return flash_write_cfiword(info, wp, cword); 1433 } 1434 1435 static inline int manufact_match(flash_info_t *info, u32 manu) 1436 { 1437 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); 1438 } 1439 1440 /*----------------------------------------------------------------------- 1441 */ 1442 #ifdef CONFIG_SYS_FLASH_PROTECTION 1443 1444 static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) 1445 { 1446 if (manufact_match(info, INTEL_MANUFACT) && 1447 info->device_id == NUMONYX_256MBIT) { 1448 /* 1449 * see errata called 1450 * "Numonyx Axcell P33/P30 Specification Update" :) 1451 */ 1452 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID); 1453 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT, 1454 prot)) { 1455 /* 1456 * cmd must come before FLASH_CMD_PROTECT + 20us 1457 * Disable interrupts which might cause a timeout here. 1458 */ 1459 int flag = disable_interrupts(); 1460 unsigned short cmd; 1461 1462 if (prot) 1463 cmd = FLASH_CMD_PROTECT_SET; 1464 else 1465 cmd = FLASH_CMD_PROTECT_CLEAR; 1466 1467 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1468 flash_write_cmd(info, sector, 0, cmd); 1469 /* re-enable interrupts if necessary */ 1470 if (flag) 1471 enable_interrupts(); 1472 } 1473 return 1; 1474 } 1475 return 0; 1476 } 1477 1478 int flash_real_protect(flash_info_t *info, long sector, int prot) 1479 { 1480 int retcode = 0; 1481 1482 switch (info->vendor) { 1483 case CFI_CMDSET_INTEL_PROG_REGIONS: 1484 case CFI_CMDSET_INTEL_STANDARD: 1485 case CFI_CMDSET_INTEL_EXTENDED: 1486 if (!cfi_protect_bugfix(info, sector, prot)) { 1487 flash_write_cmd(info, sector, 0, 1488 FLASH_CMD_CLEAR_STATUS); 1489 flash_write_cmd(info, sector, 0, 1490 FLASH_CMD_PROTECT); 1491 if (prot) 1492 flash_write_cmd(info, sector, 0, 1493 FLASH_CMD_PROTECT_SET); 1494 else 1495 flash_write_cmd(info, sector, 0, 1496 FLASH_CMD_PROTECT_CLEAR); 1497 } 1498 break; 1499 case CFI_CMDSET_AMD_EXTENDED: 1500 case CFI_CMDSET_AMD_STANDARD: 1501 /* U-Boot only checks the first byte */ 1502 if (manufact_match(info, ATM_MANUFACT)) { 1503 if (prot) { 1504 flash_unlock_seq(info, 0); 1505 flash_write_cmd(info, 0, 1506 info->addr_unlock1, 1507 ATM_CMD_SOFTLOCK_START); 1508 flash_unlock_seq(info, 0); 1509 flash_write_cmd(info, sector, 0, 1510 ATM_CMD_LOCK_SECT); 1511 } else { 1512 flash_write_cmd(info, 0, 1513 info->addr_unlock1, 1514 AMD_CMD_UNLOCK_START); 1515 if (info->device_id == ATM_ID_BV6416) 1516 flash_write_cmd(info, sector, 1517 0, ATM_CMD_UNLOCK_SECT); 1518 } 1519 } 1520 if (info->legacy_unlock) { 1521 int flag = disable_interrupts(); 1522 int lock_flag; 1523 1524 flash_unlock_seq(info, 0); 1525 flash_write_cmd(info, 0, info->addr_unlock1, 1526 AMD_CMD_SET_PPB_ENTRY); 1527 lock_flag = flash_isset(info, sector, 0, 0x01); 1528 if (prot) { 1529 if (lock_flag) { 1530 flash_write_cmd(info, sector, 0, 1531 AMD_CMD_PPB_LOCK_BC1); 1532 flash_write_cmd(info, sector, 0, 1533 AMD_CMD_PPB_LOCK_BC2); 1534 } 1535 debug("sector %ld %slocked\n", sector, 1536 lock_flag ? "" : "already "); 1537 } else { 1538 if (!lock_flag) { 1539 debug("unlock %ld\n", sector); 1540 flash_write_cmd(info, 0, 0, 1541 AMD_CMD_PPB_UNLOCK_BC1); 1542 flash_write_cmd(info, 0, 0, 1543 AMD_CMD_PPB_UNLOCK_BC2); 1544 } 1545 debug("sector %ld %sunlocked\n", sector, 1546 !lock_flag ? "" : "already "); 1547 } 1548 if (flag) 1549 enable_interrupts(); 1550 1551 if (flash_status_check(info, sector, 1552 info->erase_blk_tout, 1553 prot ? "protect" : "unprotect")) 1554 printf("status check error\n"); 1555 1556 flash_write_cmd(info, 0, 0, 1557 AMD_CMD_SET_PPB_EXIT_BC1); 1558 flash_write_cmd(info, 0, 0, 1559 AMD_CMD_SET_PPB_EXIT_BC2); 1560 } 1561 break; 1562 #ifdef CONFIG_FLASH_CFI_LEGACY 1563 case CFI_CMDSET_AMD_LEGACY: 1564 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 1565 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1566 if (prot) 1567 flash_write_cmd(info, sector, 0, 1568 FLASH_CMD_PROTECT_SET); 1569 else 1570 flash_write_cmd(info, sector, 0, 1571 FLASH_CMD_PROTECT_CLEAR); 1572 #endif 1573 }; 1574 1575 /* 1576 * Flash needs to be in status register read mode for 1577 * flash_full_status_check() to work correctly 1578 */ 1579 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 1580 retcode = flash_full_status_check(info, sector, info->erase_blk_tout, 1581 prot ? "protect" : "unprotect"); 1582 if (retcode == 0) { 1583 info->protect[sector] = prot; 1584 1585 /* 1586 * On some of Intel's flash chips (marked via legacy_unlock) 1587 * unprotect unprotects all locking. 1588 */ 1589 if (prot == 0 && info->legacy_unlock) { 1590 flash_sect_t i; 1591 1592 for (i = 0; i < info->sector_count; i++) { 1593 if (info->protect[i]) 1594 flash_real_protect(info, i, 1); 1595 } 1596 } 1597 } 1598 return retcode; 1599 } 1600 1601 /*----------------------------------------------------------------------- 1602 * flash_read_user_serial - read the OneTimeProgramming cells 1603 */ 1604 void flash_read_user_serial(flash_info_t *info, void *buffer, int offset, 1605 int len) 1606 { 1607 uchar *src; 1608 uchar *dst; 1609 1610 dst = buffer; 1611 src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION); 1612 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1613 memcpy(dst, src + offset, len); 1614 flash_write_cmd(info, 0, 0, info->cmd_reset); 1615 udelay(1); 1616 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); 1617 } 1618 1619 /* 1620 * flash_read_factory_serial - read the device Id from the protection area 1621 */ 1622 void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset, 1623 int len) 1624 { 1625 uchar *src; 1626 1627 src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION); 1628 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1629 memcpy(buffer, src + offset, len); 1630 flash_write_cmd(info, 0, 0, info->cmd_reset); 1631 udelay(1); 1632 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); 1633 } 1634 1635 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 1636 1637 /*----------------------------------------------------------------------- 1638 * Reverse the order of the erase regions in the CFI QRY structure. 1639 * This is needed for chips that are either a) correctly detected as 1640 * top-boot, or b) buggy. 1641 */ 1642 static void cfi_reverse_geometry(struct cfi_qry *qry) 1643 { 1644 unsigned int i, j; 1645 u32 tmp; 1646 1647 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { 1648 tmp = get_unaligned(&qry->erase_region_info[i]); 1649 put_unaligned(get_unaligned(&qry->erase_region_info[j]), 1650 &qry->erase_region_info[i]); 1651 put_unaligned(tmp, &qry->erase_region_info[j]); 1652 } 1653 } 1654 1655 /*----------------------------------------------------------------------- 1656 * read jedec ids from device and set corresponding fields in info struct 1657 * 1658 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct 1659 * 1660 */ 1661 static void cmdset_intel_read_jedec_ids(flash_info_t *info) 1662 { 1663 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1664 udelay(1); 1665 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1666 udelay(1000); /* some flash are slow to respond */ 1667 info->manufacturer_id = flash_read_uchar(info, 1668 FLASH_OFFSET_MANUFACTURER_ID); 1669 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? 1670 flash_read_word(info, FLASH_OFFSET_DEVICE_ID) : 1671 flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID); 1672 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1673 } 1674 1675 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) 1676 { 1677 info->cmd_reset = FLASH_CMD_RESET; 1678 1679 cmdset_intel_read_jedec_ids(info); 1680 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1681 1682 #ifdef CONFIG_SYS_FLASH_PROTECTION 1683 /* read legacy lock/unlock bit from intel flash */ 1684 if (info->ext_addr) { 1685 info->legacy_unlock = 1686 flash_read_uchar(info, info->ext_addr + 5) & 0x08; 1687 } 1688 #endif 1689 1690 return 0; 1691 } 1692 1693 static void cmdset_amd_read_jedec_ids(flash_info_t *info) 1694 { 1695 ushort bank_id = 0; 1696 uchar manu_id; 1697 uchar feature; 1698 1699 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1700 flash_unlock_seq(info, 0); 1701 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); 1702 udelay(1000); /* some flash are slow to respond */ 1703 1704 manu_id = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID); 1705 /* JEDEC JEP106Z specifies ID codes up to bank 7 */ 1706 while (manu_id == FLASH_CONTINUATION_CODE && bank_id < 0x800) { 1707 bank_id += 0x100; 1708 manu_id = flash_read_uchar(info, 1709 bank_id | FLASH_OFFSET_MANUFACTURER_ID); 1710 } 1711 info->manufacturer_id = manu_id; 1712 1713 debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n", 1714 info->ext_addr, info->cfi_version); 1715 if (info->ext_addr && info->cfi_version >= 0x3134) { 1716 /* read software feature (at 0x53) */ 1717 feature = flash_read_uchar(info, info->ext_addr + 0x13); 1718 debug("feature = 0x%x\n", feature); 1719 info->sr_supported = feature & 0x1; 1720 } 1721 1722 switch (info->chipwidth) { 1723 case FLASH_CFI_8BIT: 1724 info->device_id = flash_read_uchar(info, 1725 FLASH_OFFSET_DEVICE_ID); 1726 if (info->device_id == 0x7E) { 1727 /* AMD 3-byte (expanded) device ids */ 1728 info->device_id2 = flash_read_uchar(info, 1729 FLASH_OFFSET_DEVICE_ID2); 1730 info->device_id2 <<= 8; 1731 info->device_id2 |= flash_read_uchar(info, 1732 FLASH_OFFSET_DEVICE_ID3); 1733 } 1734 break; 1735 case FLASH_CFI_16BIT: 1736 info->device_id = flash_read_word(info, 1737 FLASH_OFFSET_DEVICE_ID); 1738 if ((info->device_id & 0xff) == 0x7E) { 1739 /* AMD 3-byte (expanded) device ids */ 1740 info->device_id2 = flash_read_uchar(info, 1741 FLASH_OFFSET_DEVICE_ID2); 1742 info->device_id2 <<= 8; 1743 info->device_id2 |= flash_read_uchar(info, 1744 FLASH_OFFSET_DEVICE_ID3); 1745 } 1746 break; 1747 default: 1748 break; 1749 } 1750 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1751 udelay(1); 1752 } 1753 1754 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) 1755 { 1756 info->cmd_reset = AMD_CMD_RESET; 1757 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; 1758 1759 cmdset_amd_read_jedec_ids(info); 1760 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1761 1762 #ifdef CONFIG_SYS_FLASH_PROTECTION 1763 if (info->ext_addr) { 1764 /* read sector protect/unprotect scheme (at 0x49) */ 1765 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) 1766 info->legacy_unlock = 1; 1767 } 1768 #endif 1769 1770 return 0; 1771 } 1772 1773 #ifdef CONFIG_FLASH_CFI_LEGACY 1774 static void flash_read_jedec_ids(flash_info_t *info) 1775 { 1776 info->manufacturer_id = 0; 1777 info->device_id = 0; 1778 info->device_id2 = 0; 1779 1780 switch (info->vendor) { 1781 case CFI_CMDSET_INTEL_PROG_REGIONS: 1782 case CFI_CMDSET_INTEL_STANDARD: 1783 case CFI_CMDSET_INTEL_EXTENDED: 1784 cmdset_intel_read_jedec_ids(info); 1785 break; 1786 case CFI_CMDSET_AMD_STANDARD: 1787 case CFI_CMDSET_AMD_EXTENDED: 1788 cmdset_amd_read_jedec_ids(info); 1789 break; 1790 default: 1791 break; 1792 } 1793 } 1794 1795 /*----------------------------------------------------------------------- 1796 * Call board code to request info about non-CFI flash. 1797 * board_flash_get_legacy needs to fill in at least: 1798 * info->portwidth, info->chipwidth and info->interface for Jedec probing. 1799 */ 1800 static int flash_detect_legacy(phys_addr_t base, int banknum) 1801 { 1802 flash_info_t *info = &flash_info[banknum]; 1803 1804 if (board_flash_get_legacy(base, banknum, info)) { 1805 /* board code may have filled info completely. If not, we 1806 * use JEDEC ID probing. 1807 */ 1808 if (!info->vendor) { 1809 int modes[] = { 1810 CFI_CMDSET_AMD_STANDARD, 1811 CFI_CMDSET_INTEL_STANDARD 1812 }; 1813 int i; 1814 1815 for (i = 0; i < ARRAY_SIZE(modes); i++) { 1816 info->vendor = modes[i]; 1817 info->start[0] = 1818 (ulong)map_physmem(base, 1819 info->portwidth, 1820 MAP_NOCACHE); 1821 if (info->portwidth == FLASH_CFI_8BIT && 1822 info->interface == FLASH_CFI_X8X16) { 1823 info->addr_unlock1 = 0x2AAA; 1824 info->addr_unlock2 = 0x5555; 1825 } else { 1826 info->addr_unlock1 = 0x5555; 1827 info->addr_unlock2 = 0x2AAA; 1828 } 1829 flash_read_jedec_ids(info); 1830 debug("JEDEC PROBE: ID %x %x %x\n", 1831 info->manufacturer_id, 1832 info->device_id, 1833 info->device_id2); 1834 if (jedec_flash_match(info, info->start[0])) 1835 break; 1836 1837 unmap_physmem((void *)info->start[0], 1838 info->portwidth); 1839 } 1840 } 1841 1842 switch (info->vendor) { 1843 case CFI_CMDSET_INTEL_PROG_REGIONS: 1844 case CFI_CMDSET_INTEL_STANDARD: 1845 case CFI_CMDSET_INTEL_EXTENDED: 1846 info->cmd_reset = FLASH_CMD_RESET; 1847 break; 1848 case CFI_CMDSET_AMD_STANDARD: 1849 case CFI_CMDSET_AMD_EXTENDED: 1850 case CFI_CMDSET_AMD_LEGACY: 1851 info->cmd_reset = AMD_CMD_RESET; 1852 break; 1853 } 1854 info->flash_id = FLASH_MAN_CFI; 1855 return 1; 1856 } 1857 return 0; /* use CFI */ 1858 } 1859 #else 1860 static inline int flash_detect_legacy(phys_addr_t base, int banknum) 1861 { 1862 return 0; /* use CFI */ 1863 } 1864 #endif 1865 1866 /*----------------------------------------------------------------------- 1867 * detect if flash is compatible with the Common Flash Interface (CFI) 1868 * http://www.jedec.org/download/search/jesd68.pdf 1869 */ 1870 static void flash_read_cfi(flash_info_t *info, void *buf, unsigned int start, 1871 size_t len) 1872 { 1873 u8 *p = buf; 1874 unsigned int i; 1875 1876 for (i = 0; i < len; i++) 1877 p[i] = flash_read_uchar(info, start + i); 1878 } 1879 1880 static void __flash_cmd_reset(flash_info_t *info) 1881 { 1882 /* 1883 * We do not yet know what kind of commandset to use, so we issue 1884 * the reset command in both Intel and AMD variants, in the hope 1885 * that AMD flash roms ignore the Intel command. 1886 */ 1887 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1888 udelay(1); 1889 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1890 } 1891 1892 void flash_cmd_reset(flash_info_t *info) 1893 __attribute__((weak, alias("__flash_cmd_reset"))); 1894 1895 static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) 1896 { 1897 int cfi_offset; 1898 1899 /* Issue FLASH reset command */ 1900 flash_cmd_reset(info); 1901 1902 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi); 1903 cfi_offset++) { 1904 flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset], 1905 FLASH_CMD_CFI); 1906 if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && 1907 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && 1908 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { 1909 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, 1910 sizeof(struct cfi_qry)); 1911 info->interface = le16_to_cpu(qry->interface_desc); 1912 1913 info->cfi_offset = flash_offset_cfi[cfi_offset]; 1914 debug("device interface is %d\n", 1915 info->interface); 1916 debug("found port %d chip %d ", 1917 info->portwidth, info->chipwidth); 1918 debug("port %d bits chip %d bits\n", 1919 info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1920 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1921 1922 /* calculate command offsets as in the Linux driver */ 1923 info->addr_unlock1 = 0x555; 1924 info->addr_unlock2 = 0x2aa; 1925 1926 /* 1927 * modify the unlock address if we are 1928 * in compatibility mode 1929 */ 1930 if (/* x8/x16 in x8 mode */ 1931 (info->chipwidth == FLASH_CFI_BY8 && 1932 info->interface == FLASH_CFI_X8X16) || 1933 /* x16/x32 in x16 mode */ 1934 (info->chipwidth == FLASH_CFI_BY16 && 1935 info->interface == FLASH_CFI_X16X32)) { 1936 info->addr_unlock1 = 0xaaa; 1937 info->addr_unlock2 = 0x555; 1938 } 1939 1940 info->name = "CFI conformant"; 1941 return 1; 1942 } 1943 } 1944 1945 return 0; 1946 } 1947 1948 static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) 1949 { 1950 debug("flash detect cfi\n"); 1951 1952 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; 1953 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { 1954 for (info->chipwidth = FLASH_CFI_BY8; 1955 info->chipwidth <= info->portwidth; 1956 info->chipwidth <<= 1) 1957 if (__flash_detect_cfi(info, qry)) 1958 return 1; 1959 } 1960 debug("not found\n"); 1961 return 0; 1962 } 1963 1964 /* 1965 * Manufacturer-specific quirks. Add workarounds for geometry 1966 * reversal, etc. here. 1967 */ 1968 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) 1969 { 1970 /* check if flash geometry needs reversal */ 1971 if (qry->num_erase_regions > 1) { 1972 /* reverse geometry if top boot part */ 1973 if (info->cfi_version < 0x3131) { 1974 /* CFI < 1.1, try to guess from device id */ 1975 if ((info->device_id & 0x80) != 0) 1976 cfi_reverse_geometry(qry); 1977 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1978 /* CFI >= 1.1, deduct from top/bottom flag */ 1979 /* note: ext_addr is valid since cfi_version > 0 */ 1980 cfi_reverse_geometry(qry); 1981 } 1982 } 1983 } 1984 1985 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) 1986 { 1987 int reverse_geometry = 0; 1988 1989 /* Check the "top boot" bit in the PRI */ 1990 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) 1991 reverse_geometry = 1; 1992 1993 /* AT49BV6416(T) list the erase regions in the wrong order. 1994 * However, the device ID is identical with the non-broken 1995 * AT49BV642D they differ in the high byte. 1996 */ 1997 if (info->device_id == 0xd6 || info->device_id == 0xd2) 1998 reverse_geometry = !reverse_geometry; 1999 2000 if (reverse_geometry) 2001 cfi_reverse_geometry(qry); 2002 } 2003 2004 static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) 2005 { 2006 /* check if flash geometry needs reversal */ 2007 if (qry->num_erase_regions > 1) { 2008 /* reverse geometry if top boot part */ 2009 if (info->cfi_version < 0x3131) { 2010 /* CFI < 1.1, guess by device id */ 2011 if (info->device_id == 0x22CA || /* M29W320DT */ 2012 info->device_id == 0x2256 || /* M29W320ET */ 2013 info->device_id == 0x22D7) { /* M29W800DT */ 2014 cfi_reverse_geometry(qry); 2015 } 2016 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 2017 /* CFI >= 1.1, deduct from top/bottom flag */ 2018 /* note: ext_addr is valid since cfi_version > 0 */ 2019 cfi_reverse_geometry(qry); 2020 } 2021 } 2022 } 2023 2024 static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) 2025 { 2026 /* 2027 * SST, for many recent nor parallel flashes, says they are 2028 * CFI-conformant. This is not true, since qry struct. 2029 * reports a std. AMD command set (0x0002), while SST allows to 2030 * erase two different sector sizes for the same memory. 2031 * 64KB sector (SST call it block) needs 0x30 to be erased. 2032 * 4KB sector (SST call it sector) needs 0x50 to be erased. 2033 * Since CFI query detect the 4KB number of sectors, users expects 2034 * a sector granularity of 4KB, and it is here set. 2035 */ 2036 if (info->device_id == 0x5D23 || /* SST39VF3201B */ 2037 info->device_id == 0x5C23) { /* SST39VF3202B */ 2038 /* set sector granularity to 4KB */ 2039 info->cmd_erase_sector = 0x50; 2040 } 2041 } 2042 2043 static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) 2044 { 2045 /* 2046 * The M29EW devices seem to report the CFI information wrong 2047 * when it's in 8 bit mode. 2048 * There's an app note from Numonyx on this issue. 2049 * So adjust the buffer size for M29EW while operating in 8-bit mode 2050 */ 2051 if (qry->max_buf_write_size > 0x8 && 2052 info->device_id == 0x7E && 2053 (info->device_id2 == 0x2201 || 2054 info->device_id2 == 0x2301 || 2055 info->device_id2 == 0x2801 || 2056 info->device_id2 == 0x4801)) { 2057 debug("Adjusted buffer size on Numonyx flash"); 2058 debug(" M29EW family in 8 bit mode\n"); 2059 qry->max_buf_write_size = 0x8; 2060 } 2061 } 2062 2063 /* 2064 * The following code cannot be run from FLASH! 2065 * 2066 */ 2067 ulong flash_get_size(phys_addr_t base, int banknum) 2068 { 2069 flash_info_t *info = &flash_info[banknum]; 2070 int i, j; 2071 flash_sect_t sect_cnt; 2072 phys_addr_t sector; 2073 unsigned long tmp; 2074 int size_ratio; 2075 uchar num_erase_regions; 2076 int erase_region_size; 2077 int erase_region_count; 2078 struct cfi_qry qry; 2079 unsigned long max_size; 2080 2081 memset(&qry, 0, sizeof(qry)); 2082 2083 info->ext_addr = 0; 2084 info->cfi_version = 0; 2085 #ifdef CONFIG_SYS_FLASH_PROTECTION 2086 info->legacy_unlock = 0; 2087 #endif 2088 2089 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); 2090 2091 if (flash_detect_cfi(info, &qry)) { 2092 info->vendor = le16_to_cpu(get_unaligned(&qry.p_id)); 2093 info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr)); 2094 num_erase_regions = qry.num_erase_regions; 2095 2096 if (info->ext_addr) { 2097 info->cfi_version = (ushort)flash_read_uchar(info, 2098 info->ext_addr + 3) << 8; 2099 info->cfi_version |= (ushort)flash_read_uchar(info, 2100 info->ext_addr + 4); 2101 } 2102 2103 #ifdef DEBUG 2104 flash_printqry(&qry); 2105 #endif 2106 2107 switch (info->vendor) { 2108 case CFI_CMDSET_INTEL_PROG_REGIONS: 2109 case CFI_CMDSET_INTEL_STANDARD: 2110 case CFI_CMDSET_INTEL_EXTENDED: 2111 cmdset_intel_init(info, &qry); 2112 break; 2113 case CFI_CMDSET_AMD_STANDARD: 2114 case CFI_CMDSET_AMD_EXTENDED: 2115 cmdset_amd_init(info, &qry); 2116 break; 2117 default: 2118 printf("CFI: Unknown command set 0x%x\n", 2119 info->vendor); 2120 /* 2121 * Unfortunately, this means we don't know how 2122 * to get the chip back to Read mode. Might 2123 * as well try an Intel-style reset... 2124 */ 2125 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 2126 return 0; 2127 } 2128 2129 /* Do manufacturer-specific fixups */ 2130 switch (info->manufacturer_id) { 2131 case 0x0001: /* AMD */ 2132 case 0x0037: /* AMIC */ 2133 flash_fixup_amd(info, &qry); 2134 break; 2135 case 0x001f: 2136 flash_fixup_atmel(info, &qry); 2137 break; 2138 case 0x0020: 2139 flash_fixup_stm(info, &qry); 2140 break; 2141 case 0x00bf: /* SST */ 2142 flash_fixup_sst(info, &qry); 2143 break; 2144 case 0x0089: /* Numonyx */ 2145 flash_fixup_num(info, &qry); 2146 break; 2147 } 2148 2149 debug("manufacturer is %d\n", info->vendor); 2150 debug("manufacturer id is 0x%x\n", info->manufacturer_id); 2151 debug("device id is 0x%x\n", info->device_id); 2152 debug("device id2 is 0x%x\n", info->device_id2); 2153 debug("cfi version is 0x%04x\n", info->cfi_version); 2154 2155 size_ratio = info->portwidth / info->chipwidth; 2156 /* if the chip is x8/x16 reduce the ratio by half */ 2157 if (info->interface == FLASH_CFI_X8X16 && 2158 info->chipwidth == FLASH_CFI_BY8) { 2159 size_ratio >>= 1; 2160 } 2161 debug("size_ratio %d port %d bits chip %d bits\n", 2162 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 2163 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 2164 info->size = 1 << qry.dev_size; 2165 /* multiply the size by the number of chips */ 2166 info->size *= size_ratio; 2167 max_size = cfi_flash_bank_size(banknum); 2168 if (max_size && info->size > max_size) { 2169 debug("[truncated from %ldMiB]", info->size >> 20); 2170 info->size = max_size; 2171 } 2172 debug("found %d erase regions\n", num_erase_regions); 2173 sect_cnt = 0; 2174 sector = base; 2175 for (i = 0; i < num_erase_regions; i++) { 2176 if (i > NUM_ERASE_REGIONS) { 2177 printf("%d erase regions found, only %d used\n", 2178 num_erase_regions, NUM_ERASE_REGIONS); 2179 break; 2180 } 2181 2182 tmp = le32_to_cpu(get_unaligned( 2183 &qry.erase_region_info[i])); 2184 debug("erase region %u: 0x%08lx\n", i, tmp); 2185 2186 erase_region_count = (tmp & 0xffff) + 1; 2187 tmp >>= 16; 2188 erase_region_size = 2189 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; 2190 debug("erase_region_count = %d ", erase_region_count); 2191 debug("erase_region_size = %d\n", erase_region_size); 2192 for (j = 0; j < erase_region_count; j++) { 2193 if (sector - base >= info->size) 2194 break; 2195 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { 2196 printf("ERROR: too many flash sectors\n"); 2197 break; 2198 } 2199 info->start[sect_cnt] = 2200 (ulong)map_physmem(sector, 2201 info->portwidth, 2202 MAP_NOCACHE); 2203 sector += (erase_region_size * size_ratio); 2204 2205 /* 2206 * Only read protection status from 2207 * supported devices (intel...) 2208 */ 2209 switch (info->vendor) { 2210 case CFI_CMDSET_INTEL_PROG_REGIONS: 2211 case CFI_CMDSET_INTEL_EXTENDED: 2212 case CFI_CMDSET_INTEL_STANDARD: 2213 /* 2214 * Set flash to read-id mode. Otherwise 2215 * reading protected status is not 2216 * guaranteed. 2217 */ 2218 flash_write_cmd(info, sect_cnt, 0, 2219 FLASH_CMD_READ_ID); 2220 info->protect[sect_cnt] = 2221 flash_isset(info, sect_cnt, 2222 FLASH_OFFSET_PROTECT, 2223 FLASH_STATUS_PROTECT); 2224 flash_write_cmd(info, sect_cnt, 0, 2225 FLASH_CMD_RESET); 2226 break; 2227 case CFI_CMDSET_AMD_EXTENDED: 2228 case CFI_CMDSET_AMD_STANDARD: 2229 if (!info->legacy_unlock) { 2230 /* default: not protected */ 2231 info->protect[sect_cnt] = 0; 2232 break; 2233 } 2234 2235 /* Read protection (PPB) from sector */ 2236 flash_write_cmd(info, 0, 0, 2237 info->cmd_reset); 2238 flash_unlock_seq(info, 0); 2239 flash_write_cmd(info, 0, 2240 info->addr_unlock1, 2241 FLASH_CMD_READ_ID); 2242 info->protect[sect_cnt] = 2243 flash_isset( 2244 info, sect_cnt, 2245 FLASH_OFFSET_PROTECT, 2246 FLASH_STATUS_PROTECT); 2247 break; 2248 default: 2249 /* default: not protected */ 2250 info->protect[sect_cnt] = 0; 2251 } 2252 2253 sect_cnt++; 2254 } 2255 } 2256 2257 info->sector_count = sect_cnt; 2258 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); 2259 tmp = 1 << qry.block_erase_timeout_typ; 2260 info->erase_blk_tout = tmp * 2261 (1 << qry.block_erase_timeout_max); 2262 tmp = (1 << qry.buf_write_timeout_typ) * 2263 (1 << qry.buf_write_timeout_max); 2264 2265 /* round up when converting to ms */ 2266 info->buffer_write_tout = (tmp + 999) / 1000; 2267 tmp = (1 << qry.word_write_timeout_typ) * 2268 (1 << qry.word_write_timeout_max); 2269 /* round up when converting to ms */ 2270 info->write_tout = (tmp + 999) / 1000; 2271 info->flash_id = FLASH_MAN_CFI; 2272 if (info->interface == FLASH_CFI_X8X16 && 2273 info->chipwidth == FLASH_CFI_BY8) { 2274 /* XXX - Need to test on x8/x16 in parallel. */ 2275 info->portwidth >>= 1; 2276 } 2277 2278 flash_write_cmd(info, 0, 0, info->cmd_reset); 2279 } 2280 2281 return (info->size); 2282 } 2283 2284 #ifdef CONFIG_FLASH_CFI_MTD 2285 void flash_set_verbose(uint v) 2286 { 2287 flash_verbose = v; 2288 } 2289 #endif 2290 2291 static void cfi_flash_set_config_reg(u32 base, u16 val) 2292 { 2293 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 2294 /* 2295 * Only set this config register if really defined 2296 * to a valid value (0xffff is invalid) 2297 */ 2298 if (val == 0xffff) 2299 return; 2300 2301 /* 2302 * Set configuration register. Data is "encrypted" in the 16 lower 2303 * address bits. 2304 */ 2305 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); 2306 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); 2307 2308 /* 2309 * Finally issue reset-command to bring device back to 2310 * read-array mode 2311 */ 2312 flash_write16(FLASH_CMD_RESET, (void *)base); 2313 #endif 2314 } 2315 2316 /*----------------------------------------------------------------------- 2317 */ 2318 2319 static void flash_protect_default(void) 2320 { 2321 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2322 int i; 2323 struct apl_s { 2324 ulong start; 2325 ulong size; 2326 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; 2327 #endif 2328 2329 /* Monitor protection ON by default */ 2330 #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ 2331 (!defined(CONFIG_MONITOR_IS_IN_RAM)) 2332 flash_protect(FLAG_PROTECT_SET, 2333 CONFIG_SYS_MONITOR_BASE, 2334 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 2335 flash_get_info(CONFIG_SYS_MONITOR_BASE)); 2336 #endif 2337 2338 /* Environment protection ON by default */ 2339 #ifdef CONFIG_ENV_IS_IN_FLASH 2340 flash_protect(FLAG_PROTECT_SET, 2341 CONFIG_ENV_ADDR, 2342 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 2343 flash_get_info(CONFIG_ENV_ADDR)); 2344 #endif 2345 2346 /* Redundant environment protection ON by default */ 2347 #ifdef CONFIG_ENV_ADDR_REDUND 2348 flash_protect(FLAG_PROTECT_SET, 2349 CONFIG_ENV_ADDR_REDUND, 2350 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 2351 flash_get_info(CONFIG_ENV_ADDR_REDUND)); 2352 #endif 2353 2354 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2355 for (i = 0; i < ARRAY_SIZE(apl); i++) { 2356 debug("autoprotecting from %08lx to %08lx\n", 2357 apl[i].start, apl[i].start + apl[i].size - 1); 2358 flash_protect(FLAG_PROTECT_SET, 2359 apl[i].start, 2360 apl[i].start + apl[i].size - 1, 2361 flash_get_info(apl[i].start)); 2362 } 2363 #endif 2364 } 2365 2366 unsigned long flash_init(void) 2367 { 2368 unsigned long size = 0; 2369 int i; 2370 2371 #ifdef CONFIG_SYS_FLASH_PROTECTION 2372 /* read environment from EEPROM */ 2373 char s[64]; 2374 2375 env_get_f("unlock", s, sizeof(s)); 2376 #endif 2377 2378 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2379 cfi_flash_init_dm(); 2380 #endif 2381 2382 /* Init: no FLASHes known */ 2383 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { 2384 flash_info[i].flash_id = FLASH_UNKNOWN; 2385 2386 /* Optionally write flash configuration register */ 2387 cfi_flash_set_config_reg(cfi_flash_bank_addr(i), 2388 cfi_flash_config_reg(i)); 2389 2390 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) 2391 flash_get_size(cfi_flash_bank_addr(i), i); 2392 size += flash_info[i].size; 2393 if (flash_info[i].flash_id == FLASH_UNKNOWN) { 2394 #ifndef CONFIG_SYS_FLASH_QUIET_TEST 2395 printf("## Unknown flash on Bank %d ", i + 1); 2396 printf("- Size = 0x%08lx = %ld MB\n", 2397 flash_info[i].size, 2398 flash_info[i].size >> 20); 2399 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ 2400 } 2401 #ifdef CONFIG_SYS_FLASH_PROTECTION 2402 else if (strcmp(s, "yes") == 0) { 2403 /* 2404 * Only the U-Boot image and it's environment 2405 * is protected, all other sectors are 2406 * unprotected (unlocked) if flash hardware 2407 * protection is used (CONFIG_SYS_FLASH_PROTECTION) 2408 * and the environment variable "unlock" is 2409 * set to "yes". 2410 */ 2411 if (flash_info[i].legacy_unlock) { 2412 int k; 2413 2414 /* 2415 * Disable legacy_unlock temporarily, 2416 * since flash_real_protect would 2417 * relock all other sectors again 2418 * otherwise. 2419 */ 2420 flash_info[i].legacy_unlock = 0; 2421 2422 /* 2423 * Legacy unlocking (e.g. Intel J3) -> 2424 * unlock only one sector. This will 2425 * unlock all sectors. 2426 */ 2427 flash_real_protect(&flash_info[i], 0, 0); 2428 2429 flash_info[i].legacy_unlock = 1; 2430 2431 /* 2432 * Manually mark other sectors as 2433 * unlocked (unprotected) 2434 */ 2435 for (k = 1; k < flash_info[i].sector_count; k++) 2436 flash_info[i].protect[k] = 0; 2437 } else { 2438 /* 2439 * No legancy unlocking -> unlock all sectors 2440 */ 2441 flash_protect(FLAG_PROTECT_CLEAR, 2442 flash_info[i].start[0], 2443 flash_info[i].start[0] 2444 + flash_info[i].size - 1, 2445 &flash_info[i]); 2446 } 2447 } 2448 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 2449 } 2450 2451 flash_protect_default(); 2452 #ifdef CONFIG_FLASH_CFI_MTD 2453 cfi_mtd_init(); 2454 #endif 2455 2456 return (size); 2457 } 2458 2459 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2460 static int cfi_flash_probe(struct udevice *dev) 2461 { 2462 void *blob = (void *)gd->fdt_blob; 2463 int node = dev_of_offset(dev); 2464 const fdt32_t *cell; 2465 phys_addr_t addr; 2466 int parent, addrc, sizec; 2467 int len, idx; 2468 2469 parent = fdt_parent_offset(blob, node); 2470 fdt_support_default_count_cells(blob, parent, &addrc, &sizec); 2471 /* decode regs, there may be multiple reg tuples. */ 2472 cell = fdt_getprop(blob, node, "reg", &len); 2473 if (!cell) 2474 return -ENOENT; 2475 idx = 0; 2476 len /= sizeof(fdt32_t); 2477 while (idx < len) { 2478 addr = fdt_translate_address((void *)blob, 2479 node, cell + idx); 2480 flash_info[cfi_flash_num_flash_banks].dev = dev; 2481 flash_info[cfi_flash_num_flash_banks].base = addr; 2482 cfi_flash_num_flash_banks++; 2483 idx += addrc + sizec; 2484 } 2485 gd->bd->bi_flashstart = flash_info[0].base; 2486 2487 return 0; 2488 } 2489 2490 static const struct udevice_id cfi_flash_ids[] = { 2491 { .compatible = "cfi-flash" }, 2492 { .compatible = "jedec-flash" }, 2493 {} 2494 }; 2495 2496 U_BOOT_DRIVER(cfi_flash) = { 2497 .name = "cfi_flash", 2498 .id = UCLASS_MTD, 2499 .of_match = cfi_flash_ids, 2500 .probe = cfi_flash_probe, 2501 }; 2502 #endif /* CONFIG_CFI_FLASH */ 2503