1 /* 2 * (C) Copyright 2002-2004 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com 4 * 5 * Copyright (C) 2003 Arabella Software Ltd. 6 * Yuli Barcohen <yuli@arabellasw.com> 7 * 8 * Copyright (C) 2004 9 * Ed Okerson 10 * 11 * Copyright (C) 2006 12 * Tolunay Orkun <listmember@orkun.us> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 /* The DEBUG define must be before common to enable debugging */ 18 /* #define DEBUG */ 19 20 #include <common.h> 21 #include <console.h> 22 #include <dm.h> 23 #include <errno.h> 24 #include <fdt_support.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include <asm/byteorder.h> 28 #include <asm/unaligned.h> 29 #include <environment.h> 30 #include <mtd/cfi_flash.h> 31 #include <watchdog.h> 32 33 /* 34 * This file implements a Common Flash Interface (CFI) driver for 35 * U-Boot. 36 * 37 * The width of the port and the width of the chips are determined at 38 * initialization. These widths are used to calculate the address for 39 * access CFI data structures. 40 * 41 * References 42 * JEDEC Standard JESD68 - Common Flash Interface (CFI) 43 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes 44 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets 45 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet 46 * AMD CFI Specification, Release 2.0 December 1, 2001 47 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte 48 * Device IDs, Publication Number 25538 Revision A, November 8, 2001 49 * 50 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between 51 * reading and writing ... (yes there is such a Hardware). 52 */ 53 54 DECLARE_GLOBAL_DATA_PTR; 55 56 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; 57 #ifdef CONFIG_FLASH_CFI_MTD 58 static uint flash_verbose = 1; 59 #else 60 #define flash_verbose 1 61 #endif 62 63 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ 64 65 /* 66 * Check if chip width is defined. If not, start detecting with 8bit. 67 */ 68 #ifndef CONFIG_SYS_FLASH_CFI_WIDTH 69 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 70 #endif 71 72 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 73 #define __maybe_weak __weak 74 #else 75 #define __maybe_weak static 76 #endif 77 78 /* 79 * 0xffff is an undefined value for the configuration register. When 80 * this value is returned, the configuration register shall not be 81 * written at all (default mode). 82 */ 83 static u16 cfi_flash_config_reg(int i) 84 { 85 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 86 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; 87 #else 88 return 0xffff; 89 #endif 90 } 91 92 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 93 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; 94 #endif 95 96 #ifdef CONFIG_CFI_FLASH /* for driver model */ 97 static void cfi_flash_init_dm(void) 98 { 99 struct udevice *dev; 100 101 cfi_flash_num_flash_banks = 0; 102 /* 103 * The uclass_first_device() will probe the first device and 104 * uclass_next_device() will probe the rest if they exist. So 105 * that cfi_flash_probe() will get called assigning the base 106 * addresses that are available. 107 */ 108 for (uclass_first_device(UCLASS_MTD, &dev); 109 dev; 110 uclass_next_device(&dev)) { 111 } 112 } 113 114 phys_addr_t cfi_flash_bank_addr(int i) 115 { 116 return flash_info[i].base; 117 } 118 #else 119 __weak phys_addr_t cfi_flash_bank_addr(int i) 120 { 121 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; 122 } 123 #endif 124 125 __weak unsigned long cfi_flash_bank_size(int i) 126 { 127 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES 128 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; 129 #else 130 return 0; 131 #endif 132 } 133 134 __maybe_weak void flash_write8(u8 value, void *addr) 135 { 136 __raw_writeb(value, addr); 137 } 138 139 __maybe_weak void flash_write16(u16 value, void *addr) 140 { 141 __raw_writew(value, addr); 142 } 143 144 __maybe_weak void flash_write32(u32 value, void *addr) 145 { 146 __raw_writel(value, addr); 147 } 148 149 __maybe_weak void flash_write64(u64 value, void *addr) 150 { 151 /* No architectures currently implement __raw_writeq() */ 152 *(volatile u64 *)addr = value; 153 } 154 155 __maybe_weak u8 flash_read8(void *addr) 156 { 157 return __raw_readb(addr); 158 } 159 160 __maybe_weak u16 flash_read16(void *addr) 161 { 162 return __raw_readw(addr); 163 } 164 165 __maybe_weak u32 flash_read32(void *addr) 166 { 167 return __raw_readl(addr); 168 } 169 170 __maybe_weak u64 flash_read64(void *addr) 171 { 172 /* No architectures currently implement __raw_readq() */ 173 return *(volatile u64 *)addr; 174 } 175 176 /*----------------------------------------------------------------------- 177 */ 178 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) 179 static flash_info_t *flash_get_info(ulong base) 180 { 181 int i; 182 flash_info_t *info; 183 184 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { 185 info = &flash_info[i]; 186 if (info->size && info->start[0] <= base && 187 base <= info->start[0] + info->size - 1) 188 return info; 189 } 190 191 return NULL; 192 } 193 #endif 194 195 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) 196 { 197 if (sect != (info->sector_count - 1)) 198 return info->start[sect + 1] - info->start[sect]; 199 else 200 return info->start[0] + info->size - info->start[sect]; 201 } 202 203 /*----------------------------------------------------------------------- 204 * create an address based on the offset and the port width 205 */ 206 static inline void * 207 flash_map(flash_info_t *info, flash_sect_t sect, uint offset) 208 { 209 unsigned int byte_offset = offset * info->portwidth; 210 211 return (void *)(info->start[sect] + byte_offset); 212 } 213 214 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, 215 unsigned int offset, void *addr) 216 { 217 } 218 219 /*----------------------------------------------------------------------- 220 * make a proper sized command based on the port and chip widths 221 */ 222 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) 223 { 224 int i; 225 int cword_offset; 226 int cp_offset; 227 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 228 u32 cmd_le = cpu_to_le32(cmd); 229 #endif 230 uchar val; 231 uchar *cp = (uchar *) cmdbuf; 232 233 for (i = info->portwidth; i > 0; i--) { 234 cword_offset = (info->portwidth - i) % info->chipwidth; 235 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 236 cp_offset = info->portwidth - i; 237 val = *((uchar *)&cmd_le + cword_offset); 238 #else 239 cp_offset = i - 1; 240 val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1); 241 #endif 242 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; 243 } 244 } 245 246 #ifdef DEBUG 247 /*----------------------------------------------------------------------- 248 * Debug support 249 */ 250 static void print_longlong(char *str, unsigned long long data) 251 { 252 int i; 253 char *cp; 254 255 cp = (char *)&data; 256 for (i = 0; i < 8; i++) 257 sprintf(&str[i * 2], "%2.2x", *cp++); 258 } 259 260 static void flash_printqry(struct cfi_qry *qry) 261 { 262 u8 *p = (u8 *)qry; 263 int x, y; 264 265 for (x = 0; x < sizeof(struct cfi_qry); x += 16) { 266 debug("%02x : ", x); 267 for (y = 0; y < 16; y++) 268 debug("%2.2x ", p[x + y]); 269 debug(" "); 270 for (y = 0; y < 16; y++) { 271 unsigned char c = p[x + y]; 272 273 if (c >= 0x20 && c <= 0x7e) 274 debug("%c", c); 275 else 276 debug("."); 277 } 278 debug("\n"); 279 } 280 } 281 #endif 282 283 /*----------------------------------------------------------------------- 284 * read a character at a port width address 285 */ 286 static inline uchar flash_read_uchar(flash_info_t *info, uint offset) 287 { 288 uchar *cp; 289 uchar retval; 290 291 cp = flash_map(info, 0, offset); 292 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 293 retval = flash_read8(cp); 294 #else 295 retval = flash_read8(cp + info->portwidth - 1); 296 #endif 297 flash_unmap(info, 0, offset, cp); 298 return retval; 299 } 300 301 /*----------------------------------------------------------------------- 302 * read a word at a port width address, assume 16bit bus 303 */ 304 static inline ushort flash_read_word(flash_info_t *info, uint offset) 305 { 306 ushort *addr, retval; 307 308 addr = flash_map(info, 0, offset); 309 retval = flash_read16(addr); 310 flash_unmap(info, 0, offset, addr); 311 return retval; 312 } 313 314 /*----------------------------------------------------------------------- 315 * read a long word by picking the least significant byte of each maximum 316 * port size word. Swap for ppc format. 317 */ 318 static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, 319 uint offset) 320 { 321 uchar *addr; 322 ulong retval; 323 324 #ifdef DEBUG 325 int x; 326 #endif 327 addr = flash_map(info, sect, offset); 328 329 #ifdef DEBUG 330 debug("long addr is at %p info->portwidth = %d\n", addr, 331 info->portwidth); 332 for (x = 0; x < 4 * info->portwidth; x++) 333 debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); 334 #endif 335 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 336 retval = ((flash_read8(addr) << 16) | 337 (flash_read8(addr + info->portwidth) << 24) | 338 (flash_read8(addr + 2 * info->portwidth)) | 339 (flash_read8(addr + 3 * info->portwidth) << 8)); 340 #else 341 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | 342 (flash_read8(addr + info->portwidth - 1) << 16) | 343 (flash_read8(addr + 4 * info->portwidth - 1) << 8) | 344 (flash_read8(addr + 3 * info->portwidth - 1))); 345 #endif 346 flash_unmap(info, sect, offset, addr); 347 348 return retval; 349 } 350 351 /* 352 * Write a proper sized command to the correct address 353 */ 354 static void flash_write_cmd(flash_info_t *info, flash_sect_t sect, 355 uint offset, u32 cmd) 356 { 357 void *addr; 358 cfiword_t cword; 359 360 addr = flash_map(info, sect, offset); 361 flash_make_cmd(info, cmd, &cword); 362 switch (info->portwidth) { 363 case FLASH_CFI_8BIT: 364 debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, 365 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 366 flash_write8(cword.w8, addr); 367 break; 368 case FLASH_CFI_16BIT: 369 debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, 370 cmd, cword.w16, 371 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 372 flash_write16(cword.w16, addr); 373 break; 374 case FLASH_CFI_32BIT: 375 debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr, 376 cmd, cword.w32, 377 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 378 flash_write32(cword.w32, addr); 379 break; 380 case FLASH_CFI_64BIT: 381 #ifdef DEBUG 382 { 383 char str[20]; 384 385 print_longlong(str, cword.w64); 386 387 debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n", 388 addr, cmd, str, 389 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 390 } 391 #endif 392 flash_write64(cword.w64, addr); 393 break; 394 } 395 396 /* Ensure all the instructions are fully finished */ 397 sync(); 398 399 flash_unmap(info, sect, offset, addr); 400 } 401 402 static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect) 403 { 404 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); 405 flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); 406 } 407 408 /*----------------------------------------------------------------------- 409 */ 410 static int flash_isequal(flash_info_t *info, flash_sect_t sect, 411 uint offset, uchar cmd) 412 { 413 void *addr; 414 cfiword_t cword; 415 int retval; 416 417 addr = flash_map(info, sect, offset); 418 flash_make_cmd(info, cmd, &cword); 419 420 debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr); 421 switch (info->portwidth) { 422 case FLASH_CFI_8BIT: 423 debug("is= %x %x\n", flash_read8(addr), cword.w8); 424 retval = (flash_read8(addr) == cword.w8); 425 break; 426 case FLASH_CFI_16BIT: 427 debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16); 428 retval = (flash_read16(addr) == cword.w16); 429 break; 430 case FLASH_CFI_32BIT: 431 debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32); 432 retval = (flash_read32(addr) == cword.w32); 433 break; 434 case FLASH_CFI_64BIT: 435 #ifdef DEBUG 436 { 437 char str1[20]; 438 char str2[20]; 439 440 print_longlong(str1, flash_read64(addr)); 441 print_longlong(str2, cword.w64); 442 debug("is= %s %s\n", str1, str2); 443 } 444 #endif 445 retval = (flash_read64(addr) == cword.w64); 446 break; 447 default: 448 retval = 0; 449 break; 450 } 451 flash_unmap(info, sect, offset, addr); 452 453 return retval; 454 } 455 456 /*----------------------------------------------------------------------- 457 */ 458 static int flash_isset(flash_info_t *info, flash_sect_t sect, 459 uint offset, uchar cmd) 460 { 461 void *addr; 462 cfiword_t cword; 463 int retval; 464 465 addr = flash_map(info, sect, offset); 466 flash_make_cmd(info, cmd, &cword); 467 switch (info->portwidth) { 468 case FLASH_CFI_8BIT: 469 retval = ((flash_read8(addr) & cword.w8) == cword.w8); 470 break; 471 case FLASH_CFI_16BIT: 472 retval = ((flash_read16(addr) & cword.w16) == cword.w16); 473 break; 474 case FLASH_CFI_32BIT: 475 retval = ((flash_read32(addr) & cword.w32) == cword.w32); 476 break; 477 case FLASH_CFI_64BIT: 478 retval = ((flash_read64(addr) & cword.w64) == cword.w64); 479 break; 480 default: 481 retval = 0; 482 break; 483 } 484 flash_unmap(info, sect, offset, addr); 485 486 return retval; 487 } 488 489 /*----------------------------------------------------------------------- 490 */ 491 static int flash_toggle(flash_info_t *info, flash_sect_t sect, 492 uint offset, uchar cmd) 493 { 494 void *addr; 495 cfiword_t cword; 496 int retval; 497 498 addr = flash_map(info, sect, offset); 499 flash_make_cmd(info, cmd, &cword); 500 switch (info->portwidth) { 501 case FLASH_CFI_8BIT: 502 retval = flash_read8(addr) != flash_read8(addr); 503 break; 504 case FLASH_CFI_16BIT: 505 retval = flash_read16(addr) != flash_read16(addr); 506 break; 507 case FLASH_CFI_32BIT: 508 retval = flash_read32(addr) != flash_read32(addr); 509 break; 510 case FLASH_CFI_64BIT: 511 retval = ((flash_read32(addr) != flash_read32(addr)) || 512 (flash_read32(addr + 4) != flash_read32(addr + 4))); 513 break; 514 default: 515 retval = 0; 516 break; 517 } 518 flash_unmap(info, sect, offset, addr); 519 520 return retval; 521 } 522 523 /* 524 * flash_is_busy - check to see if the flash is busy 525 * 526 * This routine checks the status of the chip and returns true if the 527 * chip is busy. 528 */ 529 static int flash_is_busy(flash_info_t *info, flash_sect_t sect) 530 { 531 int retval; 532 533 switch (info->vendor) { 534 case CFI_CMDSET_INTEL_PROG_REGIONS: 535 case CFI_CMDSET_INTEL_STANDARD: 536 case CFI_CMDSET_INTEL_EXTENDED: 537 retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE); 538 break; 539 case CFI_CMDSET_AMD_STANDARD: 540 case CFI_CMDSET_AMD_EXTENDED: 541 #ifdef CONFIG_FLASH_CFI_LEGACY 542 case CFI_CMDSET_AMD_LEGACY: 543 #endif 544 if (info->sr_supported) { 545 flash_write_cmd(info, sect, info->addr_unlock1, 546 FLASH_CMD_READ_STATUS); 547 retval = !flash_isset(info, sect, 0, 548 FLASH_STATUS_DONE); 549 } else { 550 retval = flash_toggle(info, sect, 0, 551 AMD_STATUS_TOGGLE); 552 } 553 554 break; 555 default: 556 retval = 0; 557 } 558 debug("flash_is_busy: %d\n", retval); 559 return retval; 560 } 561 562 /*----------------------------------------------------------------------- 563 * wait for XSR.7 to be set. Time out with an error if it does not. 564 * This routine does not set the flash to read-array mode. 565 */ 566 static int flash_status_check(flash_info_t *info, flash_sect_t sector, 567 ulong tout, char *prompt) 568 { 569 ulong start; 570 571 #if CONFIG_SYS_HZ != 1000 572 if ((ulong)CONFIG_SYS_HZ > 100000) 573 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ 574 else 575 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 576 #endif 577 578 /* Wait for command completion */ 579 #ifdef CONFIG_SYS_LOW_RES_TIMER 580 reset_timer(); 581 #endif 582 start = get_timer(0); 583 WATCHDOG_RESET(); 584 while (flash_is_busy(info, sector)) { 585 if (get_timer(start) > tout) { 586 printf("Flash %s timeout at address %lx data %lx\n", 587 prompt, info->start[sector], 588 flash_read_long(info, sector, 0)); 589 flash_write_cmd(info, sector, 0, info->cmd_reset); 590 udelay(1); 591 return ERR_TIMOUT; 592 } 593 udelay(1); /* also triggers watchdog */ 594 } 595 return ERR_OK; 596 } 597 598 /*----------------------------------------------------------------------- 599 * Wait for XSR.7 to be set, if it times out print an error, otherwise 600 * do a full status check. 601 * 602 * This routine sets the flash to read-array mode. 603 */ 604 static int flash_full_status_check(flash_info_t *info, flash_sect_t sector, 605 ulong tout, char *prompt) 606 { 607 int retcode; 608 609 retcode = flash_status_check(info, sector, tout, prompt); 610 switch (info->vendor) { 611 case CFI_CMDSET_INTEL_PROG_REGIONS: 612 case CFI_CMDSET_INTEL_EXTENDED: 613 case CFI_CMDSET_INTEL_STANDARD: 614 if ((retcode == ERR_OK) && 615 !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { 616 retcode = ERR_INVAL; 617 printf("Flash %s error at address %lx\n", prompt, 618 info->start[sector]); 619 if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | 620 FLASH_STATUS_PSLBS)) { 621 puts("Command Sequence Error.\n"); 622 } else if (flash_isset(info, sector, 0, 623 FLASH_STATUS_ECLBS)) { 624 puts("Block Erase Error.\n"); 625 retcode = ERR_NOT_ERASED; 626 } else if (flash_isset(info, sector, 0, 627 FLASH_STATUS_PSLBS)) { 628 puts("Locking Error\n"); 629 } 630 if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { 631 puts("Block locked.\n"); 632 retcode = ERR_PROTECTED; 633 } 634 if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) 635 puts("Vpp Low Error.\n"); 636 } 637 flash_write_cmd(info, sector, 0, info->cmd_reset); 638 udelay(1); 639 break; 640 default: 641 break; 642 } 643 return retcode; 644 } 645 646 static int use_flash_status_poll(flash_info_t *info) 647 { 648 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 649 if (info->vendor == CFI_CMDSET_AMD_EXTENDED || 650 info->vendor == CFI_CMDSET_AMD_STANDARD) 651 return 1; 652 #endif 653 return 0; 654 } 655 656 static int flash_status_poll(flash_info_t *info, void *src, void *dst, 657 ulong tout, char *prompt) 658 { 659 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 660 ulong start; 661 int ready; 662 663 #if CONFIG_SYS_HZ != 1000 664 if ((ulong)CONFIG_SYS_HZ > 100000) 665 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ 666 else 667 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 668 #endif 669 670 /* Wait for command completion */ 671 #ifdef CONFIG_SYS_LOW_RES_TIMER 672 reset_timer(); 673 #endif 674 start = get_timer(0); 675 WATCHDOG_RESET(); 676 while (1) { 677 switch (info->portwidth) { 678 case FLASH_CFI_8BIT: 679 ready = flash_read8(dst) == flash_read8(src); 680 break; 681 case FLASH_CFI_16BIT: 682 ready = flash_read16(dst) == flash_read16(src); 683 break; 684 case FLASH_CFI_32BIT: 685 ready = flash_read32(dst) == flash_read32(src); 686 break; 687 case FLASH_CFI_64BIT: 688 ready = flash_read64(dst) == flash_read64(src); 689 break; 690 default: 691 ready = 0; 692 break; 693 } 694 if (ready) 695 break; 696 if (get_timer(start) > tout) { 697 printf("Flash %s timeout at address %lx data %lx\n", 698 prompt, (ulong)dst, (ulong)flash_read8(dst)); 699 return ERR_TIMOUT; 700 } 701 udelay(1); /* also triggers watchdog */ 702 } 703 #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ 704 return ERR_OK; 705 } 706 707 /*----------------------------------------------------------------------- 708 */ 709 static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) 710 { 711 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 712 unsigned short w; 713 unsigned int l; 714 unsigned long long ll; 715 #endif 716 717 switch (info->portwidth) { 718 case FLASH_CFI_8BIT: 719 cword->w8 = c; 720 break; 721 case FLASH_CFI_16BIT: 722 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 723 w = c; 724 w <<= 8; 725 cword->w16 = (cword->w16 >> 8) | w; 726 #else 727 cword->w16 = (cword->w16 << 8) | c; 728 #endif 729 break; 730 case FLASH_CFI_32BIT: 731 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 732 l = c; 733 l <<= 24; 734 cword->w32 = (cword->w32 >> 8) | l; 735 #else 736 cword->w32 = (cword->w32 << 8) | c; 737 #endif 738 break; 739 case FLASH_CFI_64BIT: 740 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 741 ll = c; 742 ll <<= 56; 743 cword->w64 = (cword->w64 >> 8) | ll; 744 #else 745 cword->w64 = (cword->w64 << 8) | c; 746 #endif 747 break; 748 } 749 } 750 751 /* 752 * Loop through the sector table starting from the previously found sector. 753 * Searches forwards or backwards, dependent on the passed address. 754 */ 755 static flash_sect_t find_sector(flash_info_t *info, ulong addr) 756 { 757 static flash_sect_t saved_sector; /* previously found sector */ 758 static flash_info_t *saved_info; /* previously used flash bank */ 759 flash_sect_t sector = saved_sector; 760 761 if ((info != saved_info) || (sector >= info->sector_count)) 762 sector = 0; 763 764 while ((info->start[sector] < addr) && 765 (sector < info->sector_count - 1)) 766 sector++; 767 while ((info->start[sector] > addr) && (sector > 0)) 768 /* 769 * also decrements the sector in case of an overshot 770 * in the first loop 771 */ 772 sector--; 773 774 saved_sector = sector; 775 saved_info = info; 776 return sector; 777 } 778 779 /*----------------------------------------------------------------------- 780 */ 781 static int flash_write_cfiword(flash_info_t *info, ulong dest, 782 cfiword_t cword) 783 { 784 void *dstaddr = (void *)dest; 785 int flag; 786 flash_sect_t sect = 0; 787 char sect_found = 0; 788 789 /* Check if Flash is (sufficiently) erased */ 790 switch (info->portwidth) { 791 case FLASH_CFI_8BIT: 792 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8); 793 break; 794 case FLASH_CFI_16BIT: 795 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16); 796 break; 797 case FLASH_CFI_32BIT: 798 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32); 799 break; 800 case FLASH_CFI_64BIT: 801 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64); 802 break; 803 default: 804 flag = 0; 805 break; 806 } 807 if (!flag) 808 return ERR_NOT_ERASED; 809 810 /* Disable interrupts which might cause a timeout here */ 811 flag = disable_interrupts(); 812 813 switch (info->vendor) { 814 case CFI_CMDSET_INTEL_PROG_REGIONS: 815 case CFI_CMDSET_INTEL_EXTENDED: 816 case CFI_CMDSET_INTEL_STANDARD: 817 flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); 818 flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); 819 break; 820 case CFI_CMDSET_AMD_EXTENDED: 821 case CFI_CMDSET_AMD_STANDARD: 822 sect = find_sector(info, dest); 823 flash_unlock_seq(info, sect); 824 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE); 825 sect_found = 1; 826 break; 827 #ifdef CONFIG_FLASH_CFI_LEGACY 828 case CFI_CMDSET_AMD_LEGACY: 829 sect = find_sector(info, dest); 830 flash_unlock_seq(info, 0); 831 flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE); 832 sect_found = 1; 833 break; 834 #endif 835 } 836 837 switch (info->portwidth) { 838 case FLASH_CFI_8BIT: 839 flash_write8(cword.w8, dstaddr); 840 break; 841 case FLASH_CFI_16BIT: 842 flash_write16(cword.w16, dstaddr); 843 break; 844 case FLASH_CFI_32BIT: 845 flash_write32(cword.w32, dstaddr); 846 break; 847 case FLASH_CFI_64BIT: 848 flash_write64(cword.w64, dstaddr); 849 break; 850 } 851 852 /* re-enable interrupts if necessary */ 853 if (flag) 854 enable_interrupts(); 855 856 if (!sect_found) 857 sect = find_sector(info, dest); 858 859 if (use_flash_status_poll(info)) 860 return flash_status_poll(info, &cword, dstaddr, 861 info->write_tout, "write"); 862 else 863 return flash_full_status_check(info, sect, 864 info->write_tout, "write"); 865 } 866 867 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 868 869 static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, 870 int len) 871 { 872 flash_sect_t sector; 873 int cnt; 874 int retcode; 875 void *src = cp; 876 void *dst = (void *)dest; 877 void *dst2 = dst; 878 int flag = 1; 879 uint offset = 0; 880 unsigned int shift; 881 uchar write_cmd; 882 883 switch (info->portwidth) { 884 case FLASH_CFI_8BIT: 885 shift = 0; 886 break; 887 case FLASH_CFI_16BIT: 888 shift = 1; 889 break; 890 case FLASH_CFI_32BIT: 891 shift = 2; 892 break; 893 case FLASH_CFI_64BIT: 894 shift = 3; 895 break; 896 default: 897 retcode = ERR_INVAL; 898 goto out_unmap; 899 } 900 901 cnt = len >> shift; 902 903 while ((cnt-- > 0) && (flag == 1)) { 904 switch (info->portwidth) { 905 case FLASH_CFI_8BIT: 906 flag = ((flash_read8(dst2) & flash_read8(src)) == 907 flash_read8(src)); 908 src += 1, dst2 += 1; 909 break; 910 case FLASH_CFI_16BIT: 911 flag = ((flash_read16(dst2) & flash_read16(src)) == 912 flash_read16(src)); 913 src += 2, dst2 += 2; 914 break; 915 case FLASH_CFI_32BIT: 916 flag = ((flash_read32(dst2) & flash_read32(src)) == 917 flash_read32(src)); 918 src += 4, dst2 += 4; 919 break; 920 case FLASH_CFI_64BIT: 921 flag = ((flash_read64(dst2) & flash_read64(src)) == 922 flash_read64(src)); 923 src += 8, dst2 += 8; 924 break; 925 } 926 } 927 if (!flag) { 928 retcode = ERR_NOT_ERASED; 929 goto out_unmap; 930 } 931 932 src = cp; 933 sector = find_sector(info, dest); 934 935 switch (info->vendor) { 936 case CFI_CMDSET_INTEL_PROG_REGIONS: 937 case CFI_CMDSET_INTEL_STANDARD: 938 case CFI_CMDSET_INTEL_EXTENDED: 939 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? 940 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; 941 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 942 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 943 flash_write_cmd(info, sector, 0, write_cmd); 944 retcode = flash_status_check(info, sector, 945 info->buffer_write_tout, 946 "write to buffer"); 947 if (retcode == ERR_OK) { 948 /* reduce the number of loops by the width of 949 * the port */ 950 cnt = len >> shift; 951 flash_write_cmd(info, sector, 0, cnt - 1); 952 while (cnt-- > 0) { 953 switch (info->portwidth) { 954 case FLASH_CFI_8BIT: 955 flash_write8(flash_read8(src), dst); 956 src += 1, dst += 1; 957 break; 958 case FLASH_CFI_16BIT: 959 flash_write16(flash_read16(src), dst); 960 src += 2, dst += 2; 961 break; 962 case FLASH_CFI_32BIT: 963 flash_write32(flash_read32(src), dst); 964 src += 4, dst += 4; 965 break; 966 case FLASH_CFI_64BIT: 967 flash_write64(flash_read64(src), dst); 968 src += 8, dst += 8; 969 break; 970 default: 971 retcode = ERR_INVAL; 972 goto out_unmap; 973 } 974 } 975 flash_write_cmd(info, sector, 0, 976 FLASH_CMD_WRITE_BUFFER_CONFIRM); 977 retcode = flash_full_status_check( 978 info, sector, info->buffer_write_tout, 979 "buffer write"); 980 } 981 982 break; 983 984 case CFI_CMDSET_AMD_STANDARD: 985 case CFI_CMDSET_AMD_EXTENDED: 986 flash_unlock_seq(info, sector); 987 988 #ifdef CONFIG_FLASH_SPANSION_S29WS_N 989 offset = ((unsigned long)dst - info->start[sector]) >> shift; 990 #endif 991 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); 992 cnt = len >> shift; 993 flash_write_cmd(info, sector, offset, cnt - 1); 994 995 switch (info->portwidth) { 996 case FLASH_CFI_8BIT: 997 while (cnt-- > 0) { 998 flash_write8(flash_read8(src), dst); 999 src += 1, dst += 1; 1000 } 1001 break; 1002 case FLASH_CFI_16BIT: 1003 while (cnt-- > 0) { 1004 flash_write16(flash_read16(src), dst); 1005 src += 2, dst += 2; 1006 } 1007 break; 1008 case FLASH_CFI_32BIT: 1009 while (cnt-- > 0) { 1010 flash_write32(flash_read32(src), dst); 1011 src += 4, dst += 4; 1012 } 1013 break; 1014 case FLASH_CFI_64BIT: 1015 while (cnt-- > 0) { 1016 flash_write64(flash_read64(src), dst); 1017 src += 8, dst += 8; 1018 } 1019 break; 1020 default: 1021 retcode = ERR_INVAL; 1022 goto out_unmap; 1023 } 1024 1025 flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); 1026 if (use_flash_status_poll(info)) 1027 retcode = flash_status_poll(info, src - (1 << shift), 1028 dst - (1 << shift), 1029 info->buffer_write_tout, 1030 "buffer write"); 1031 else 1032 retcode = flash_full_status_check(info, sector, 1033 info->buffer_write_tout, 1034 "buffer write"); 1035 break; 1036 1037 default: 1038 debug("Unknown Command Set\n"); 1039 retcode = ERR_INVAL; 1040 break; 1041 } 1042 1043 out_unmap: 1044 return retcode; 1045 } 1046 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1047 1048 /*----------------------------------------------------------------------- 1049 */ 1050 int flash_erase(flash_info_t *info, int s_first, int s_last) 1051 { 1052 int rcode = 0; 1053 int prot; 1054 flash_sect_t sect; 1055 int st; 1056 1057 if (info->flash_id != FLASH_MAN_CFI) { 1058 puts("Can't erase unknown flash type - aborted\n"); 1059 return 1; 1060 } 1061 if ((s_first < 0) || (s_first > s_last)) { 1062 puts("- no sectors to erase\n"); 1063 return 1; 1064 } 1065 1066 prot = 0; 1067 for (sect = s_first; sect <= s_last; ++sect) 1068 if (info->protect[sect]) 1069 prot++; 1070 if (prot) { 1071 printf("- Warning: %d protected sectors will not be erased!\n", 1072 prot); 1073 } else if (flash_verbose) { 1074 putc('\n'); 1075 } 1076 1077 for (sect = s_first; sect <= s_last; sect++) { 1078 if (ctrlc()) { 1079 printf("\n"); 1080 return 1; 1081 } 1082 1083 if (info->protect[sect] == 0) { /* not protected */ 1084 #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE 1085 int k; 1086 int size; 1087 int erased; 1088 u32 *flash; 1089 1090 /* 1091 * Check if whole sector is erased 1092 */ 1093 size = flash_sector_size(info, sect); 1094 erased = 1; 1095 flash = (u32 *)info->start[sect]; 1096 /* divide by 4 for longword access */ 1097 size = size >> 2; 1098 for (k = 0; k < size; k++) { 1099 if (flash_read32(flash++) != 0xffffffff) { 1100 erased = 0; 1101 break; 1102 } 1103 } 1104 if (erased) { 1105 if (flash_verbose) 1106 putc(','); 1107 continue; 1108 } 1109 #endif 1110 switch (info->vendor) { 1111 case CFI_CMDSET_INTEL_PROG_REGIONS: 1112 case CFI_CMDSET_INTEL_STANDARD: 1113 case CFI_CMDSET_INTEL_EXTENDED: 1114 flash_write_cmd(info, sect, 0, 1115 FLASH_CMD_CLEAR_STATUS); 1116 flash_write_cmd(info, sect, 0, 1117 FLASH_CMD_BLOCK_ERASE); 1118 flash_write_cmd(info, sect, 0, 1119 FLASH_CMD_ERASE_CONFIRM); 1120 break; 1121 case CFI_CMDSET_AMD_STANDARD: 1122 case CFI_CMDSET_AMD_EXTENDED: 1123 flash_unlock_seq(info, sect); 1124 flash_write_cmd(info, sect, 1125 info->addr_unlock1, 1126 AMD_CMD_ERASE_START); 1127 flash_unlock_seq(info, sect); 1128 flash_write_cmd(info, sect, 0, 1129 info->cmd_erase_sector); 1130 break; 1131 #ifdef CONFIG_FLASH_CFI_LEGACY 1132 case CFI_CMDSET_AMD_LEGACY: 1133 flash_unlock_seq(info, 0); 1134 flash_write_cmd(info, 0, info->addr_unlock1, 1135 AMD_CMD_ERASE_START); 1136 flash_unlock_seq(info, 0); 1137 flash_write_cmd(info, sect, 0, 1138 AMD_CMD_ERASE_SECTOR); 1139 break; 1140 #endif 1141 default: 1142 debug("Unkown flash vendor %d\n", 1143 info->vendor); 1144 break; 1145 } 1146 1147 if (use_flash_status_poll(info)) { 1148 cfiword_t cword; 1149 void *dest; 1150 1151 cword.w64 = 0xffffffffffffffffULL; 1152 dest = flash_map(info, sect, 0); 1153 st = flash_status_poll(info, &cword, dest, 1154 info->erase_blk_tout, "erase"); 1155 flash_unmap(info, sect, 0, dest); 1156 } else 1157 st = flash_full_status_check(info, sect, 1158 info->erase_blk_tout, 1159 "erase"); 1160 if (st) 1161 rcode = 1; 1162 else if (flash_verbose) 1163 putc('.'); 1164 } 1165 } 1166 1167 if (flash_verbose) 1168 puts(" done\n"); 1169 1170 return rcode; 1171 } 1172 1173 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1174 static int sector_erased(flash_info_t *info, int i) 1175 { 1176 int k; 1177 int size; 1178 u32 *flash; 1179 1180 /* 1181 * Check if whole sector is erased 1182 */ 1183 size = flash_sector_size(info, i); 1184 flash = (u32 *)info->start[i]; 1185 /* divide by 4 for longword access */ 1186 size = size >> 2; 1187 1188 for (k = 0; k < size; k++) { 1189 if (flash_read32(flash++) != 0xffffffff) 1190 return 0; /* not erased */ 1191 } 1192 1193 return 1; /* erased */ 1194 } 1195 #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ 1196 1197 void flash_print_info(flash_info_t *info) 1198 { 1199 int i; 1200 1201 if (info->flash_id != FLASH_MAN_CFI) { 1202 puts("missing or unknown FLASH type\n"); 1203 return; 1204 } 1205 1206 printf("%s flash (%d x %d)", 1207 info->name, 1208 (info->portwidth << 3), (info->chipwidth << 3)); 1209 if (info->size < 1024 * 1024) 1210 printf(" Size: %ld kB in %d Sectors\n", 1211 info->size >> 10, info->sector_count); 1212 else 1213 printf(" Size: %ld MB in %d Sectors\n", 1214 info->size >> 20, info->sector_count); 1215 printf(" "); 1216 switch (info->vendor) { 1217 case CFI_CMDSET_INTEL_PROG_REGIONS: 1218 printf("Intel Prog Regions"); 1219 break; 1220 case CFI_CMDSET_INTEL_STANDARD: 1221 printf("Intel Standard"); 1222 break; 1223 case CFI_CMDSET_INTEL_EXTENDED: 1224 printf("Intel Extended"); 1225 break; 1226 case CFI_CMDSET_AMD_STANDARD: 1227 printf("AMD Standard"); 1228 break; 1229 case CFI_CMDSET_AMD_EXTENDED: 1230 printf("AMD Extended"); 1231 break; 1232 #ifdef CONFIG_FLASH_CFI_LEGACY 1233 case CFI_CMDSET_AMD_LEGACY: 1234 printf("AMD Legacy"); 1235 break; 1236 #endif 1237 default: 1238 printf("Unknown (%d)", info->vendor); 1239 break; 1240 } 1241 printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x", 1242 info->manufacturer_id); 1243 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1244 info->device_id); 1245 if ((info->device_id & 0xff) == 0x7E) { 1246 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1247 info->device_id2); 1248 } 1249 if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock)) 1250 printf("\n Advanced Sector Protection (PPB) enabled"); 1251 printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n", 1252 info->erase_blk_tout, 1253 info->write_tout); 1254 if (info->buffer_size > 1) { 1255 printf(" Buffer write timeout: %ld ms, " 1256 "buffer size: %d bytes\n", 1257 info->buffer_write_tout, 1258 info->buffer_size); 1259 } 1260 1261 puts("\n Sector Start Addresses:"); 1262 for (i = 0; i < info->sector_count; ++i) { 1263 if (ctrlc()) 1264 break; 1265 if ((i % 5) == 0) 1266 putc('\n'); 1267 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1268 /* print empty and read-only info */ 1269 printf(" %08lX %c %s ", 1270 info->start[i], 1271 sector_erased(info, i) ? 'E' : ' ', 1272 info->protect[i] ? "RO" : " "); 1273 #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ 1274 printf(" %08lX %s ", 1275 info->start[i], 1276 info->protect[i] ? "RO" : " "); 1277 #endif 1278 } 1279 putc('\n'); 1280 return; 1281 } 1282 1283 /*----------------------------------------------------------------------- 1284 * This is used in a few places in write_buf() to show programming 1285 * progress. Making it a function is nasty because it needs to do side 1286 * effect updates to digit and dots. Repeated code is nasty too, so 1287 * we define it once here. 1288 */ 1289 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1290 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ 1291 if (flash_verbose) { \ 1292 dots -= dots_sub; \ 1293 if ((scale > 0) && (dots <= 0)) { \ 1294 if ((digit % 5) == 0) \ 1295 printf("%d", digit / 5); \ 1296 else \ 1297 putc('.'); \ 1298 digit--; \ 1299 dots += scale; \ 1300 } \ 1301 } 1302 #else 1303 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) 1304 #endif 1305 1306 /*----------------------------------------------------------------------- 1307 * Copy memory to flash, returns: 1308 * 0 - OK 1309 * 1 - write timeout 1310 * 2 - Flash not erased 1311 */ 1312 int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) 1313 { 1314 ulong wp; 1315 uchar *p; 1316 int aln; 1317 cfiword_t cword; 1318 int i, rc; 1319 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1320 int buffered_size; 1321 #endif 1322 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1323 int digit = CONFIG_FLASH_SHOW_PROGRESS; 1324 int scale = 0; 1325 int dots = 0; 1326 1327 /* 1328 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. 1329 */ 1330 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { 1331 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / 1332 CONFIG_FLASH_SHOW_PROGRESS); 1333 } 1334 #endif 1335 1336 /* get lower aligned address */ 1337 wp = (addr & ~(info->portwidth - 1)); 1338 1339 /* handle unaligned start */ 1340 if ((aln = addr - wp) != 0) { 1341 cword.w32 = 0; 1342 p = (uchar *)wp; 1343 for (i = 0; i < aln; ++i) 1344 flash_add_byte(info, &cword, flash_read8(p + i)); 1345 1346 for (; (i < info->portwidth) && (cnt > 0); i++) { 1347 flash_add_byte(info, &cword, *src++); 1348 cnt--; 1349 } 1350 for (; (cnt == 0) && (i < info->portwidth); ++i) 1351 flash_add_byte(info, &cword, flash_read8(p + i)); 1352 1353 rc = flash_write_cfiword(info, wp, cword); 1354 if (rc != 0) 1355 return rc; 1356 1357 wp += i; 1358 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1359 } 1360 1361 /* handle the aligned part */ 1362 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1363 buffered_size = (info->portwidth / info->chipwidth); 1364 buffered_size *= info->buffer_size; 1365 while (cnt >= info->portwidth) { 1366 /* prohibit buffer write when buffer_size is 1 */ 1367 if (info->buffer_size == 1) { 1368 cword.w32 = 0; 1369 for (i = 0; i < info->portwidth; i++) 1370 flash_add_byte(info, &cword, *src++); 1371 if ((rc = flash_write_cfiword(info, wp, cword)) != 0) 1372 return rc; 1373 wp += info->portwidth; 1374 cnt -= info->portwidth; 1375 continue; 1376 } 1377 1378 /* write buffer until next buffered_size aligned boundary */ 1379 i = buffered_size - (wp % buffered_size); 1380 if (i > cnt) 1381 i = cnt; 1382 if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) 1383 return rc; 1384 i -= i & (info->portwidth - 1); 1385 wp += i; 1386 src += i; 1387 cnt -= i; 1388 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1389 /* Only check every once in a while */ 1390 if ((cnt & 0xFFFF) < buffered_size && ctrlc()) 1391 return ERR_ABORTED; 1392 } 1393 #else 1394 while (cnt >= info->portwidth) { 1395 cword.w32 = 0; 1396 for (i = 0; i < info->portwidth; i++) 1397 flash_add_byte(info, &cword, *src++); 1398 if ((rc = flash_write_cfiword(info, wp, cword)) != 0) 1399 return rc; 1400 wp += info->portwidth; 1401 cnt -= info->portwidth; 1402 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); 1403 /* Only check every once in a while */ 1404 if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) 1405 return ERR_ABORTED; 1406 } 1407 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1408 1409 if (cnt == 0) 1410 return (0); 1411 1412 /* 1413 * handle unaligned tail bytes 1414 */ 1415 cword.w32 = 0; 1416 p = (uchar *)wp; 1417 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { 1418 flash_add_byte(info, &cword, *src++); 1419 --cnt; 1420 } 1421 for (; i < info->portwidth; ++i) 1422 flash_add_byte(info, &cword, flash_read8(p + i)); 1423 1424 return flash_write_cfiword(info, wp, cword); 1425 } 1426 1427 static inline int manufact_match(flash_info_t *info, u32 manu) 1428 { 1429 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); 1430 } 1431 1432 /*----------------------------------------------------------------------- 1433 */ 1434 #ifdef CONFIG_SYS_FLASH_PROTECTION 1435 1436 static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) 1437 { 1438 if (manufact_match(info, INTEL_MANUFACT) && 1439 info->device_id == NUMONYX_256MBIT) { 1440 /* 1441 * see errata called 1442 * "Numonyx Axcell P33/P30 Specification Update" :) 1443 */ 1444 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID); 1445 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT, 1446 prot)) { 1447 /* 1448 * cmd must come before FLASH_CMD_PROTECT + 20us 1449 * Disable interrupts which might cause a timeout here. 1450 */ 1451 int flag = disable_interrupts(); 1452 unsigned short cmd; 1453 1454 if (prot) 1455 cmd = FLASH_CMD_PROTECT_SET; 1456 else 1457 cmd = FLASH_CMD_PROTECT_CLEAR; 1458 1459 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1460 flash_write_cmd(info, sector, 0, cmd); 1461 /* re-enable interrupts if necessary */ 1462 if (flag) 1463 enable_interrupts(); 1464 } 1465 return 1; 1466 } 1467 return 0; 1468 } 1469 1470 int flash_real_protect(flash_info_t *info, long sector, int prot) 1471 { 1472 int retcode = 0; 1473 1474 switch (info->vendor) { 1475 case CFI_CMDSET_INTEL_PROG_REGIONS: 1476 case CFI_CMDSET_INTEL_STANDARD: 1477 case CFI_CMDSET_INTEL_EXTENDED: 1478 if (!cfi_protect_bugfix(info, sector, prot)) { 1479 flash_write_cmd(info, sector, 0, 1480 FLASH_CMD_CLEAR_STATUS); 1481 flash_write_cmd(info, sector, 0, 1482 FLASH_CMD_PROTECT); 1483 if (prot) 1484 flash_write_cmd(info, sector, 0, 1485 FLASH_CMD_PROTECT_SET); 1486 else 1487 flash_write_cmd(info, sector, 0, 1488 FLASH_CMD_PROTECT_CLEAR); 1489 } 1490 break; 1491 case CFI_CMDSET_AMD_EXTENDED: 1492 case CFI_CMDSET_AMD_STANDARD: 1493 /* U-Boot only checks the first byte */ 1494 if (manufact_match(info, ATM_MANUFACT)) { 1495 if (prot) { 1496 flash_unlock_seq(info, 0); 1497 flash_write_cmd(info, 0, 1498 info->addr_unlock1, 1499 ATM_CMD_SOFTLOCK_START); 1500 flash_unlock_seq(info, 0); 1501 flash_write_cmd(info, sector, 0, 1502 ATM_CMD_LOCK_SECT); 1503 } else { 1504 flash_write_cmd(info, 0, 1505 info->addr_unlock1, 1506 AMD_CMD_UNLOCK_START); 1507 if (info->device_id == ATM_ID_BV6416) 1508 flash_write_cmd(info, sector, 1509 0, ATM_CMD_UNLOCK_SECT); 1510 } 1511 } 1512 if (info->legacy_unlock) { 1513 int flag = disable_interrupts(); 1514 int lock_flag; 1515 1516 flash_unlock_seq(info, 0); 1517 flash_write_cmd(info, 0, info->addr_unlock1, 1518 AMD_CMD_SET_PPB_ENTRY); 1519 lock_flag = flash_isset(info, sector, 0, 0x01); 1520 if (prot) { 1521 if (lock_flag) { 1522 flash_write_cmd(info, sector, 0, 1523 AMD_CMD_PPB_LOCK_BC1); 1524 flash_write_cmd(info, sector, 0, 1525 AMD_CMD_PPB_LOCK_BC2); 1526 } 1527 debug("sector %ld %slocked\n", sector, 1528 lock_flag ? "" : "already "); 1529 } else { 1530 if (!lock_flag) { 1531 debug("unlock %ld\n", sector); 1532 flash_write_cmd(info, 0, 0, 1533 AMD_CMD_PPB_UNLOCK_BC1); 1534 flash_write_cmd(info, 0, 0, 1535 AMD_CMD_PPB_UNLOCK_BC2); 1536 } 1537 debug("sector %ld %sunlocked\n", sector, 1538 !lock_flag ? "" : "already "); 1539 } 1540 if (flag) 1541 enable_interrupts(); 1542 1543 if (flash_status_check(info, sector, 1544 info->erase_blk_tout, 1545 prot ? "protect" : "unprotect")) 1546 printf("status check error\n"); 1547 1548 flash_write_cmd(info, 0, 0, 1549 AMD_CMD_SET_PPB_EXIT_BC1); 1550 flash_write_cmd(info, 0, 0, 1551 AMD_CMD_SET_PPB_EXIT_BC2); 1552 } 1553 break; 1554 #ifdef CONFIG_FLASH_CFI_LEGACY 1555 case CFI_CMDSET_AMD_LEGACY: 1556 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 1557 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1558 if (prot) 1559 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); 1560 else 1561 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); 1562 #endif 1563 }; 1564 1565 /* 1566 * Flash needs to be in status register read mode for 1567 * flash_full_status_check() to work correctly 1568 */ 1569 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 1570 if ((retcode = 1571 flash_full_status_check(info, sector, info->erase_blk_tout, 1572 prot ? "protect" : "unprotect")) == 0) { 1573 info->protect[sector] = prot; 1574 1575 /* 1576 * On some of Intel's flash chips (marked via legacy_unlock) 1577 * unprotect unprotects all locking. 1578 */ 1579 if ((prot == 0) && (info->legacy_unlock)) { 1580 flash_sect_t i; 1581 1582 for (i = 0; i < info->sector_count; i++) { 1583 if (info->protect[i]) 1584 flash_real_protect(info, i, 1); 1585 } 1586 } 1587 } 1588 return retcode; 1589 } 1590 1591 /*----------------------------------------------------------------------- 1592 * flash_read_user_serial - read the OneTimeProgramming cells 1593 */ 1594 void flash_read_user_serial(flash_info_t *info, void *buffer, int offset, 1595 int len) 1596 { 1597 uchar *src; 1598 uchar *dst; 1599 1600 dst = buffer; 1601 src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION); 1602 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1603 memcpy(dst, src + offset, len); 1604 flash_write_cmd(info, 0, 0, info->cmd_reset); 1605 udelay(1); 1606 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); 1607 } 1608 1609 /* 1610 * flash_read_factory_serial - read the device Id from the protection area 1611 */ 1612 void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset, 1613 int len) 1614 { 1615 uchar *src; 1616 1617 src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION); 1618 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1619 memcpy(buffer, src + offset, len); 1620 flash_write_cmd(info, 0, 0, info->cmd_reset); 1621 udelay(1); 1622 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); 1623 } 1624 1625 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 1626 1627 /*----------------------------------------------------------------------- 1628 * Reverse the order of the erase regions in the CFI QRY structure. 1629 * This is needed for chips that are either a) correctly detected as 1630 * top-boot, or b) buggy. 1631 */ 1632 static void cfi_reverse_geometry(struct cfi_qry *qry) 1633 { 1634 unsigned int i, j; 1635 u32 tmp; 1636 1637 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { 1638 tmp = get_unaligned(&(qry->erase_region_info[i])); 1639 put_unaligned(get_unaligned(&(qry->erase_region_info[j])), 1640 &(qry->erase_region_info[i])); 1641 put_unaligned(tmp, &(qry->erase_region_info[j])); 1642 } 1643 } 1644 1645 /*----------------------------------------------------------------------- 1646 * read jedec ids from device and set corresponding fields in info struct 1647 * 1648 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct 1649 * 1650 */ 1651 static void cmdset_intel_read_jedec_ids(flash_info_t *info) 1652 { 1653 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1654 udelay(1); 1655 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1656 udelay(1000); /* some flash are slow to respond */ 1657 info->manufacturer_id = flash_read_uchar(info, 1658 FLASH_OFFSET_MANUFACTURER_ID); 1659 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? 1660 flash_read_word(info, FLASH_OFFSET_DEVICE_ID) : 1661 flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID); 1662 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1663 } 1664 1665 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) 1666 { 1667 info->cmd_reset = FLASH_CMD_RESET; 1668 1669 cmdset_intel_read_jedec_ids(info); 1670 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1671 1672 #ifdef CONFIG_SYS_FLASH_PROTECTION 1673 /* read legacy lock/unlock bit from intel flash */ 1674 if (info->ext_addr) { 1675 info->legacy_unlock = flash_read_uchar(info, 1676 info->ext_addr + 5) & 0x08; 1677 } 1678 #endif 1679 1680 return 0; 1681 } 1682 1683 static void cmdset_amd_read_jedec_ids(flash_info_t *info) 1684 { 1685 ushort bankId = 0; 1686 uchar manuId; 1687 uchar feature; 1688 1689 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1690 flash_unlock_seq(info, 0); 1691 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); 1692 udelay(1000); /* some flash are slow to respond */ 1693 1694 manuId = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID); 1695 /* JEDEC JEP106Z specifies ID codes up to bank 7 */ 1696 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { 1697 bankId += 0x100; 1698 manuId = flash_read_uchar(info, 1699 bankId | FLASH_OFFSET_MANUFACTURER_ID); 1700 } 1701 info->manufacturer_id = manuId; 1702 1703 debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n", 1704 info->ext_addr, info->cfi_version); 1705 if (info->ext_addr && info->cfi_version >= 0x3134) { 1706 /* read software feature (at 0x53) */ 1707 feature = flash_read_uchar(info, info->ext_addr + 0x13); 1708 debug("feature = 0x%x\n", feature); 1709 info->sr_supported = feature & 0x1; 1710 } 1711 1712 switch (info->chipwidth) { 1713 case FLASH_CFI_8BIT: 1714 info->device_id = flash_read_uchar(info, 1715 FLASH_OFFSET_DEVICE_ID); 1716 if (info->device_id == 0x7E) { 1717 /* AMD 3-byte (expanded) device ids */ 1718 info->device_id2 = flash_read_uchar(info, 1719 FLASH_OFFSET_DEVICE_ID2); 1720 info->device_id2 <<= 8; 1721 info->device_id2 |= flash_read_uchar(info, 1722 FLASH_OFFSET_DEVICE_ID3); 1723 } 1724 break; 1725 case FLASH_CFI_16BIT: 1726 info->device_id = flash_read_word(info, 1727 FLASH_OFFSET_DEVICE_ID); 1728 if ((info->device_id & 0xff) == 0x7E) { 1729 /* AMD 3-byte (expanded) device ids */ 1730 info->device_id2 = flash_read_uchar(info, 1731 FLASH_OFFSET_DEVICE_ID2); 1732 info->device_id2 <<= 8; 1733 info->device_id2 |= flash_read_uchar(info, 1734 FLASH_OFFSET_DEVICE_ID3); 1735 } 1736 break; 1737 default: 1738 break; 1739 } 1740 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1741 udelay(1); 1742 } 1743 1744 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) 1745 { 1746 info->cmd_reset = AMD_CMD_RESET; 1747 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; 1748 1749 cmdset_amd_read_jedec_ids(info); 1750 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1751 1752 #ifdef CONFIG_SYS_FLASH_PROTECTION 1753 if (info->ext_addr) { 1754 /* read sector protect/unprotect scheme (at 0x49) */ 1755 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) 1756 info->legacy_unlock = 1; 1757 } 1758 #endif 1759 1760 return 0; 1761 } 1762 1763 #ifdef CONFIG_FLASH_CFI_LEGACY 1764 static void flash_read_jedec_ids(flash_info_t *info) 1765 { 1766 info->manufacturer_id = 0; 1767 info->device_id = 0; 1768 info->device_id2 = 0; 1769 1770 switch (info->vendor) { 1771 case CFI_CMDSET_INTEL_PROG_REGIONS: 1772 case CFI_CMDSET_INTEL_STANDARD: 1773 case CFI_CMDSET_INTEL_EXTENDED: 1774 cmdset_intel_read_jedec_ids(info); 1775 break; 1776 case CFI_CMDSET_AMD_STANDARD: 1777 case CFI_CMDSET_AMD_EXTENDED: 1778 cmdset_amd_read_jedec_ids(info); 1779 break; 1780 default: 1781 break; 1782 } 1783 } 1784 1785 /*----------------------------------------------------------------------- 1786 * Call board code to request info about non-CFI flash. 1787 * board_flash_get_legacy needs to fill in at least: 1788 * info->portwidth, info->chipwidth and info->interface for Jedec probing. 1789 */ 1790 static int flash_detect_legacy(phys_addr_t base, int banknum) 1791 { 1792 flash_info_t *info = &flash_info[banknum]; 1793 1794 if (board_flash_get_legacy(base, banknum, info)) { 1795 /* board code may have filled info completely. If not, we 1796 use JEDEC ID probing. */ 1797 if (!info->vendor) { 1798 int modes[] = { 1799 CFI_CMDSET_AMD_STANDARD, 1800 CFI_CMDSET_INTEL_STANDARD 1801 }; 1802 int i; 1803 1804 for (i = 0; i < ARRAY_SIZE(modes); i++) { 1805 info->vendor = modes[i]; 1806 info->start[0] = 1807 (ulong)map_physmem(base, 1808 info->portwidth, 1809 MAP_NOCACHE); 1810 if (info->portwidth == FLASH_CFI_8BIT && 1811 info->interface == FLASH_CFI_X8X16) { 1812 info->addr_unlock1 = 0x2AAA; 1813 info->addr_unlock2 = 0x5555; 1814 } else { 1815 info->addr_unlock1 = 0x5555; 1816 info->addr_unlock2 = 0x2AAA; 1817 } 1818 flash_read_jedec_ids(info); 1819 debug("JEDEC PROBE: ID %x %x %x\n", 1820 info->manufacturer_id, 1821 info->device_id, 1822 info->device_id2); 1823 if (jedec_flash_match(info, info->start[0])) 1824 break; 1825 else 1826 unmap_physmem((void *)info->start[0], 1827 info->portwidth); 1828 } 1829 } 1830 1831 switch (info->vendor) { 1832 case CFI_CMDSET_INTEL_PROG_REGIONS: 1833 case CFI_CMDSET_INTEL_STANDARD: 1834 case CFI_CMDSET_INTEL_EXTENDED: 1835 info->cmd_reset = FLASH_CMD_RESET; 1836 break; 1837 case CFI_CMDSET_AMD_STANDARD: 1838 case CFI_CMDSET_AMD_EXTENDED: 1839 case CFI_CMDSET_AMD_LEGACY: 1840 info->cmd_reset = AMD_CMD_RESET; 1841 break; 1842 } 1843 info->flash_id = FLASH_MAN_CFI; 1844 return 1; 1845 } 1846 return 0; /* use CFI */ 1847 } 1848 #else 1849 static inline int flash_detect_legacy(phys_addr_t base, int banknum) 1850 { 1851 return 0; /* use CFI */ 1852 } 1853 #endif 1854 1855 /*----------------------------------------------------------------------- 1856 * detect if flash is compatible with the Common Flash Interface (CFI) 1857 * http://www.jedec.org/download/search/jesd68.pdf 1858 */ 1859 static void flash_read_cfi(flash_info_t *info, void *buf, 1860 unsigned int start, size_t len) 1861 { 1862 u8 *p = buf; 1863 unsigned int i; 1864 1865 for (i = 0; i < len; i++) 1866 p[i] = flash_read_uchar(info, start + i); 1867 } 1868 1869 static void __flash_cmd_reset(flash_info_t *info) 1870 { 1871 /* 1872 * We do not yet know what kind of commandset to use, so we issue 1873 * the reset command in both Intel and AMD variants, in the hope 1874 * that AMD flash roms ignore the Intel command. 1875 */ 1876 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1877 udelay(1); 1878 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1879 } 1880 1881 void flash_cmd_reset(flash_info_t *info) 1882 __attribute__((weak, alias("__flash_cmd_reset"))); 1883 1884 static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) 1885 { 1886 int cfi_offset; 1887 1888 /* Issue FLASH reset command */ 1889 flash_cmd_reset(info); 1890 1891 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi); 1892 cfi_offset++) { 1893 flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset], 1894 FLASH_CMD_CFI); 1895 if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && 1896 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && 1897 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { 1898 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, 1899 sizeof(struct cfi_qry)); 1900 info->interface = le16_to_cpu(qry->interface_desc); 1901 1902 info->cfi_offset = flash_offset_cfi[cfi_offset]; 1903 debug("device interface is %d\n", 1904 info->interface); 1905 debug("found port %d chip %d ", 1906 info->portwidth, info->chipwidth); 1907 debug("port %d bits chip %d bits\n", 1908 info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1909 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1910 1911 /* calculate command offsets as in the Linux driver */ 1912 info->addr_unlock1 = 0x555; 1913 info->addr_unlock2 = 0x2aa; 1914 1915 /* 1916 * modify the unlock address if we are 1917 * in compatibility mode 1918 */ 1919 if (/* x8/x16 in x8 mode */ 1920 ((info->chipwidth == FLASH_CFI_BY8) && 1921 (info->interface == FLASH_CFI_X8X16)) || 1922 /* x16/x32 in x16 mode */ 1923 ((info->chipwidth == FLASH_CFI_BY16) && 1924 (info->interface == FLASH_CFI_X16X32))) 1925 { 1926 info->addr_unlock1 = 0xaaa; 1927 info->addr_unlock2 = 0x555; 1928 } 1929 1930 info->name = "CFI conformant"; 1931 return 1; 1932 } 1933 } 1934 1935 return 0; 1936 } 1937 1938 static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) 1939 { 1940 debug("flash detect cfi\n"); 1941 1942 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; 1943 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { 1944 for (info->chipwidth = FLASH_CFI_BY8; 1945 info->chipwidth <= info->portwidth; 1946 info->chipwidth <<= 1) 1947 if (__flash_detect_cfi(info, qry)) 1948 return 1; 1949 } 1950 debug("not found\n"); 1951 return 0; 1952 } 1953 1954 /* 1955 * Manufacturer-specific quirks. Add workarounds for geometry 1956 * reversal, etc. here. 1957 */ 1958 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) 1959 { 1960 /* check if flash geometry needs reversal */ 1961 if (qry->num_erase_regions > 1) { 1962 /* reverse geometry if top boot part */ 1963 if (info->cfi_version < 0x3131) { 1964 /* CFI < 1.1, try to guess from device id */ 1965 if ((info->device_id & 0x80) != 0) 1966 cfi_reverse_geometry(qry); 1967 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1968 /* CFI >= 1.1, deduct from top/bottom flag */ 1969 /* note: ext_addr is valid since cfi_version > 0 */ 1970 cfi_reverse_geometry(qry); 1971 } 1972 } 1973 } 1974 1975 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) 1976 { 1977 int reverse_geometry = 0; 1978 1979 /* Check the "top boot" bit in the PRI */ 1980 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) 1981 reverse_geometry = 1; 1982 1983 /* AT49BV6416(T) list the erase regions in the wrong order. 1984 * However, the device ID is identical with the non-broken 1985 * AT49BV642D they differ in the high byte. 1986 */ 1987 if (info->device_id == 0xd6 || info->device_id == 0xd2) 1988 reverse_geometry = !reverse_geometry; 1989 1990 if (reverse_geometry) 1991 cfi_reverse_geometry(qry); 1992 } 1993 1994 static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) 1995 { 1996 /* check if flash geometry needs reversal */ 1997 if (qry->num_erase_regions > 1) { 1998 /* reverse geometry if top boot part */ 1999 if (info->cfi_version < 0x3131) { 2000 /* CFI < 1.1, guess by device id */ 2001 if (info->device_id == 0x22CA || /* M29W320DT */ 2002 info->device_id == 0x2256 || /* M29W320ET */ 2003 info->device_id == 0x22D7) { /* M29W800DT */ 2004 cfi_reverse_geometry(qry); 2005 } 2006 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 2007 /* CFI >= 1.1, deduct from top/bottom flag */ 2008 /* note: ext_addr is valid since cfi_version > 0 */ 2009 cfi_reverse_geometry(qry); 2010 } 2011 } 2012 } 2013 2014 static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) 2015 { 2016 /* 2017 * SST, for many recent nor parallel flashes, says they are 2018 * CFI-conformant. This is not true, since qry struct. 2019 * reports a std. AMD command set (0x0002), while SST allows to 2020 * erase two different sector sizes for the same memory. 2021 * 64KB sector (SST call it block) needs 0x30 to be erased. 2022 * 4KB sector (SST call it sector) needs 0x50 to be erased. 2023 * Since CFI query detect the 4KB number of sectors, users expects 2024 * a sector granularity of 4KB, and it is here set. 2025 */ 2026 if (info->device_id == 0x5D23 || /* SST39VF3201B */ 2027 info->device_id == 0x5C23) { /* SST39VF3202B */ 2028 /* set sector granularity to 4KB */ 2029 info->cmd_erase_sector = 0x50; 2030 } 2031 } 2032 2033 static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) 2034 { 2035 /* 2036 * The M29EW devices seem to report the CFI information wrong 2037 * when it's in 8 bit mode. 2038 * There's an app note from Numonyx on this issue. 2039 * So adjust the buffer size for M29EW while operating in 8-bit mode 2040 */ 2041 if (((qry->max_buf_write_size) > 0x8) && 2042 (info->device_id == 0x7E) && 2043 (info->device_id2 == 0x2201 || 2044 info->device_id2 == 0x2301 || 2045 info->device_id2 == 0x2801 || 2046 info->device_id2 == 0x4801)) { 2047 debug("Adjusted buffer size on Numonyx flash" 2048 " M29EW family in 8 bit mode\n"); 2049 qry->max_buf_write_size = 0x8; 2050 } 2051 } 2052 2053 /* 2054 * The following code cannot be run from FLASH! 2055 * 2056 */ 2057 ulong flash_get_size(phys_addr_t base, int banknum) 2058 { 2059 flash_info_t *info = &flash_info[banknum]; 2060 int i, j; 2061 flash_sect_t sect_cnt; 2062 phys_addr_t sector; 2063 unsigned long tmp; 2064 int size_ratio; 2065 uchar num_erase_regions; 2066 int erase_region_size; 2067 int erase_region_count; 2068 struct cfi_qry qry; 2069 unsigned long max_size; 2070 2071 memset(&qry, 0, sizeof(qry)); 2072 2073 info->ext_addr = 0; 2074 info->cfi_version = 0; 2075 #ifdef CONFIG_SYS_FLASH_PROTECTION 2076 info->legacy_unlock = 0; 2077 #endif 2078 2079 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); 2080 2081 if (flash_detect_cfi(info, &qry)) { 2082 info->vendor = le16_to_cpu(get_unaligned(&(qry.p_id))); 2083 info->ext_addr = le16_to_cpu(get_unaligned(&(qry.p_adr))); 2084 num_erase_regions = qry.num_erase_regions; 2085 2086 if (info->ext_addr) { 2087 info->cfi_version = (ushort)flash_read_uchar(info, 2088 info->ext_addr + 3) << 8; 2089 info->cfi_version |= (ushort)flash_read_uchar(info, 2090 info->ext_addr + 4); 2091 } 2092 2093 #ifdef DEBUG 2094 flash_printqry(&qry); 2095 #endif 2096 2097 switch (info->vendor) { 2098 case CFI_CMDSET_INTEL_PROG_REGIONS: 2099 case CFI_CMDSET_INTEL_STANDARD: 2100 case CFI_CMDSET_INTEL_EXTENDED: 2101 cmdset_intel_init(info, &qry); 2102 break; 2103 case CFI_CMDSET_AMD_STANDARD: 2104 case CFI_CMDSET_AMD_EXTENDED: 2105 cmdset_amd_init(info, &qry); 2106 break; 2107 default: 2108 printf("CFI: Unknown command set 0x%x\n", 2109 info->vendor); 2110 /* 2111 * Unfortunately, this means we don't know how 2112 * to get the chip back to Read mode. Might 2113 * as well try an Intel-style reset... 2114 */ 2115 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 2116 return 0; 2117 } 2118 2119 /* Do manufacturer-specific fixups */ 2120 switch (info->manufacturer_id) { 2121 case 0x0001: /* AMD */ 2122 case 0x0037: /* AMIC */ 2123 flash_fixup_amd(info, &qry); 2124 break; 2125 case 0x001f: 2126 flash_fixup_atmel(info, &qry); 2127 break; 2128 case 0x0020: 2129 flash_fixup_stm(info, &qry); 2130 break; 2131 case 0x00bf: /* SST */ 2132 flash_fixup_sst(info, &qry); 2133 break; 2134 case 0x0089: /* Numonyx */ 2135 flash_fixup_num(info, &qry); 2136 break; 2137 } 2138 2139 debug("manufacturer is %d\n", info->vendor); 2140 debug("manufacturer id is 0x%x\n", info->manufacturer_id); 2141 debug("device id is 0x%x\n", info->device_id); 2142 debug("device id2 is 0x%x\n", info->device_id2); 2143 debug("cfi version is 0x%04x\n", info->cfi_version); 2144 2145 size_ratio = info->portwidth / info->chipwidth; 2146 /* if the chip is x8/x16 reduce the ratio by half */ 2147 if ((info->interface == FLASH_CFI_X8X16) && 2148 (info->chipwidth == FLASH_CFI_BY8)) { 2149 size_ratio >>= 1; 2150 } 2151 debug("size_ratio %d port %d bits chip %d bits\n", 2152 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 2153 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 2154 info->size = 1 << qry.dev_size; 2155 /* multiply the size by the number of chips */ 2156 info->size *= size_ratio; 2157 max_size = cfi_flash_bank_size(banknum); 2158 if (max_size && (info->size > max_size)) { 2159 debug("[truncated from %ldMiB]", info->size >> 20); 2160 info->size = max_size; 2161 } 2162 debug("found %d erase regions\n", num_erase_regions); 2163 sect_cnt = 0; 2164 sector = base; 2165 for (i = 0; i < num_erase_regions; i++) { 2166 if (i > NUM_ERASE_REGIONS) { 2167 printf("%d erase regions found, only %d used\n", 2168 num_erase_regions, NUM_ERASE_REGIONS); 2169 break; 2170 } 2171 2172 tmp = le32_to_cpu(get_unaligned( 2173 &(qry.erase_region_info[i]))); 2174 debug("erase region %u: 0x%08lx\n", i, tmp); 2175 2176 erase_region_count = (tmp & 0xffff) + 1; 2177 tmp >>= 16; 2178 erase_region_size = 2179 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; 2180 debug("erase_region_count = %d erase_region_size = %d\n", 2181 erase_region_count, erase_region_size); 2182 for (j = 0; j < erase_region_count; j++) { 2183 if (sector - base >= info->size) 2184 break; 2185 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { 2186 printf("ERROR: too many flash sectors\n"); 2187 break; 2188 } 2189 info->start[sect_cnt] = 2190 (ulong)map_physmem(sector, 2191 info->portwidth, 2192 MAP_NOCACHE); 2193 sector += (erase_region_size * size_ratio); 2194 2195 /* 2196 * Only read protection status from 2197 * supported devices (intel...) 2198 */ 2199 switch (info->vendor) { 2200 case CFI_CMDSET_INTEL_PROG_REGIONS: 2201 case CFI_CMDSET_INTEL_EXTENDED: 2202 case CFI_CMDSET_INTEL_STANDARD: 2203 /* 2204 * Set flash to read-id mode. Otherwise 2205 * reading protected status is not 2206 * guaranteed. 2207 */ 2208 flash_write_cmd(info, sect_cnt, 0, 2209 FLASH_CMD_READ_ID); 2210 info->protect[sect_cnt] = 2211 flash_isset(info, sect_cnt, 2212 FLASH_OFFSET_PROTECT, 2213 FLASH_STATUS_PROTECT); 2214 flash_write_cmd(info, sect_cnt, 0, 2215 FLASH_CMD_RESET); 2216 break; 2217 case CFI_CMDSET_AMD_EXTENDED: 2218 case CFI_CMDSET_AMD_STANDARD: 2219 if (!info->legacy_unlock) { 2220 /* default: not protected */ 2221 info->protect[sect_cnt] = 0; 2222 break; 2223 } 2224 2225 /* Read protection (PPB) from sector */ 2226 flash_write_cmd(info, 0, 0, 2227 info->cmd_reset); 2228 flash_unlock_seq(info, 0); 2229 flash_write_cmd(info, 0, 2230 info->addr_unlock1, 2231 FLASH_CMD_READ_ID); 2232 info->protect[sect_cnt] = 2233 flash_isset( 2234 info, sect_cnt, 2235 FLASH_OFFSET_PROTECT, 2236 FLASH_STATUS_PROTECT); 2237 break; 2238 default: 2239 /* default: not protected */ 2240 info->protect[sect_cnt] = 0; 2241 } 2242 2243 sect_cnt++; 2244 } 2245 } 2246 2247 info->sector_count = sect_cnt; 2248 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); 2249 tmp = 1 << qry.block_erase_timeout_typ; 2250 info->erase_blk_tout = tmp * 2251 (1 << qry.block_erase_timeout_max); 2252 tmp = (1 << qry.buf_write_timeout_typ) * 2253 (1 << qry.buf_write_timeout_max); 2254 2255 /* round up when converting to ms */ 2256 info->buffer_write_tout = (tmp + 999) / 1000; 2257 tmp = (1 << qry.word_write_timeout_typ) * 2258 (1 << qry.word_write_timeout_max); 2259 /* round up when converting to ms */ 2260 info->write_tout = (tmp + 999) / 1000; 2261 info->flash_id = FLASH_MAN_CFI; 2262 if ((info->interface == FLASH_CFI_X8X16) && 2263 (info->chipwidth == FLASH_CFI_BY8)) { 2264 /* XXX - Need to test on x8/x16 in parallel. */ 2265 info->portwidth >>= 1; 2266 } 2267 2268 flash_write_cmd(info, 0, 0, info->cmd_reset); 2269 } 2270 2271 return (info->size); 2272 } 2273 2274 #ifdef CONFIG_FLASH_CFI_MTD 2275 void flash_set_verbose(uint v) 2276 { 2277 flash_verbose = v; 2278 } 2279 #endif 2280 2281 static void cfi_flash_set_config_reg(u32 base, u16 val) 2282 { 2283 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 2284 /* 2285 * Only set this config register if really defined 2286 * to a valid value (0xffff is invalid) 2287 */ 2288 if (val == 0xffff) 2289 return; 2290 2291 /* 2292 * Set configuration register. Data is "encrypted" in the 16 lower 2293 * address bits. 2294 */ 2295 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); 2296 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); 2297 2298 /* 2299 * Finally issue reset-command to bring device back to 2300 * read-array mode 2301 */ 2302 flash_write16(FLASH_CMD_RESET, (void *)base); 2303 #endif 2304 } 2305 2306 /*----------------------------------------------------------------------- 2307 */ 2308 2309 static void flash_protect_default(void) 2310 { 2311 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2312 int i; 2313 struct apl_s { 2314 ulong start; 2315 ulong size; 2316 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; 2317 #endif 2318 2319 /* Monitor protection ON by default */ 2320 #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ 2321 (!defined(CONFIG_MONITOR_IS_IN_RAM)) 2322 flash_protect(FLAG_PROTECT_SET, 2323 CONFIG_SYS_MONITOR_BASE, 2324 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 2325 flash_get_info(CONFIG_SYS_MONITOR_BASE)); 2326 #endif 2327 2328 /* Environment protection ON by default */ 2329 #ifdef CONFIG_ENV_IS_IN_FLASH 2330 flash_protect(FLAG_PROTECT_SET, 2331 CONFIG_ENV_ADDR, 2332 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 2333 flash_get_info(CONFIG_ENV_ADDR)); 2334 #endif 2335 2336 /* Redundant environment protection ON by default */ 2337 #ifdef CONFIG_ENV_ADDR_REDUND 2338 flash_protect(FLAG_PROTECT_SET, 2339 CONFIG_ENV_ADDR_REDUND, 2340 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 2341 flash_get_info(CONFIG_ENV_ADDR_REDUND)); 2342 #endif 2343 2344 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2345 for (i = 0; i < ARRAY_SIZE(apl); i++) { 2346 debug("autoprotecting from %08lx to %08lx\n", 2347 apl[i].start, apl[i].start + apl[i].size - 1); 2348 flash_protect(FLAG_PROTECT_SET, 2349 apl[i].start, 2350 apl[i].start + apl[i].size - 1, 2351 flash_get_info(apl[i].start)); 2352 } 2353 #endif 2354 } 2355 2356 unsigned long flash_init(void) 2357 { 2358 unsigned long size = 0; 2359 int i; 2360 2361 #ifdef CONFIG_SYS_FLASH_PROTECTION 2362 /* read environment from EEPROM */ 2363 char s[64]; 2364 2365 env_get_f("unlock", s, sizeof(s)); 2366 #endif 2367 2368 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2369 cfi_flash_init_dm(); 2370 #endif 2371 2372 /* Init: no FLASHes known */ 2373 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { 2374 flash_info[i].flash_id = FLASH_UNKNOWN; 2375 2376 /* Optionally write flash configuration register */ 2377 cfi_flash_set_config_reg(cfi_flash_bank_addr(i), 2378 cfi_flash_config_reg(i)); 2379 2380 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) 2381 flash_get_size(cfi_flash_bank_addr(i), i); 2382 size += flash_info[i].size; 2383 if (flash_info[i].flash_id == FLASH_UNKNOWN) { 2384 #ifndef CONFIG_SYS_FLASH_QUIET_TEST 2385 printf("## Unknown flash on Bank %d " 2386 "- Size = 0x%08lx = %ld MB\n", 2387 i + 1, flash_info[i].size, 2388 flash_info[i].size >> 20); 2389 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ 2390 } 2391 #ifdef CONFIG_SYS_FLASH_PROTECTION 2392 else if (strcmp(s, "yes") == 0) { 2393 /* 2394 * Only the U-Boot image and it's environment 2395 * is protected, all other sectors are 2396 * unprotected (unlocked) if flash hardware 2397 * protection is used (CONFIG_SYS_FLASH_PROTECTION) 2398 * and the environment variable "unlock" is 2399 * set to "yes". 2400 */ 2401 if (flash_info[i].legacy_unlock) { 2402 int k; 2403 2404 /* 2405 * Disable legacy_unlock temporarily, 2406 * since flash_real_protect would 2407 * relock all other sectors again 2408 * otherwise. 2409 */ 2410 flash_info[i].legacy_unlock = 0; 2411 2412 /* 2413 * Legacy unlocking (e.g. Intel J3) -> 2414 * unlock only one sector. This will 2415 * unlock all sectors. 2416 */ 2417 flash_real_protect(&flash_info[i], 0, 0); 2418 2419 flash_info[i].legacy_unlock = 1; 2420 2421 /* 2422 * Manually mark other sectors as 2423 * unlocked (unprotected) 2424 */ 2425 for (k = 1; k < flash_info[i].sector_count; k++) 2426 flash_info[i].protect[k] = 0; 2427 } else { 2428 /* 2429 * No legancy unlocking -> unlock all sectors 2430 */ 2431 flash_protect(FLAG_PROTECT_CLEAR, 2432 flash_info[i].start[0], 2433 flash_info[i].start[0] 2434 + flash_info[i].size - 1, 2435 &flash_info[i]); 2436 } 2437 } 2438 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 2439 } 2440 2441 flash_protect_default(); 2442 #ifdef CONFIG_FLASH_CFI_MTD 2443 cfi_mtd_init(); 2444 #endif 2445 2446 return (size); 2447 } 2448 2449 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2450 static int cfi_flash_probe(struct udevice *dev) 2451 { 2452 void *blob = (void *)gd->fdt_blob; 2453 int node = dev_of_offset(dev); 2454 const fdt32_t *cell; 2455 phys_addr_t addr; 2456 int parent, addrc, sizec; 2457 int len, idx; 2458 2459 parent = fdt_parent_offset(blob, node); 2460 fdt_support_default_count_cells(blob, parent, &addrc, &sizec); 2461 /* decode regs, there may be multiple reg tuples. */ 2462 cell = fdt_getprop(blob, node, "reg", &len); 2463 if (!cell) 2464 return -ENOENT; 2465 idx = 0; 2466 len /= sizeof(fdt32_t); 2467 while (idx < len) { 2468 addr = fdt_translate_address((void *)blob, 2469 node, cell + idx); 2470 flash_info[cfi_flash_num_flash_banks].dev = dev; 2471 flash_info[cfi_flash_num_flash_banks].base = addr; 2472 cfi_flash_num_flash_banks++; 2473 idx += addrc + sizec; 2474 } 2475 gd->bd->bi_flashstart = flash_info[0].base; 2476 2477 return 0; 2478 } 2479 2480 static const struct udevice_id cfi_flash_ids[] = { 2481 { .compatible = "cfi-flash" }, 2482 { .compatible = "jedec-flash" }, 2483 {} 2484 }; 2485 2486 U_BOOT_DRIVER(cfi_flash) = { 2487 .name = "cfi_flash", 2488 .id = UCLASS_MTD, 2489 .of_match = cfi_flash_ids, 2490 .probe = cfi_flash_probe, 2491 }; 2492 #endif /* CONFIG_CFI_FLASH */ 2493