1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2015 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <dm/device.h> 13 #include <errno.h> 14 #include <asm/gpio.h> 15 #include <asm/io.h> 16 #ifndef CONFIG_TEGRA186 17 #include <asm/arch/clock.h> 18 #include <asm/arch-tegra/clk_rst.h> 19 #endif 20 #include <asm/arch-tegra/mmc.h> 21 #include <asm/arch-tegra/tegra_mmc.h> 22 #include <mmc.h> 23 24 /* 25 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that 26 * should not be present. These are needed because newer Tegra SoCs support 27 * only the standard clock/reset APIs, whereas older Tegra SoCs support only 28 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be 29 * fixed to implement the standard APIs, and all drivers converted to solely 30 * use the new standard APIs, with no ifdefs. 31 */ 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 struct tegra_mmc_priv { 36 struct tegra_mmc *reg; 37 int id; /* device id/number, 0-3 */ 38 int enabled; /* 1 to enable, 0 to disable */ 39 int width; /* Bus Width, 1, 4 or 8 */ 40 #ifdef CONFIG_TEGRA186 41 struct reset_ctl reset_ctl; 42 struct clk clk; 43 #else 44 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ 45 #endif 46 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 47 struct gpio_desc pwr_gpio; /* Power GPIO */ 48 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 49 unsigned int version; /* SDHCI spec. version */ 50 unsigned int clock; /* Current clock (MHz) */ 51 struct mmc_config cfg; /* mmc configuration */ 52 }; 53 54 struct tegra_mmc_priv mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; 55 56 #if !CONFIG_IS_ENABLED(OF_CONTROL) 57 #error "Please enable device tree support to use this driver" 58 #endif 59 60 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, 61 unsigned short power) 62 { 63 u8 pwr = 0; 64 debug("%s: power = %x\n", __func__, power); 65 66 if (power != (unsigned short)-1) { 67 switch (1 << power) { 68 case MMC_VDD_165_195: 69 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 70 break; 71 case MMC_VDD_29_30: 72 case MMC_VDD_30_31: 73 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 74 break; 75 case MMC_VDD_32_33: 76 case MMC_VDD_33_34: 77 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 78 break; 79 } 80 } 81 debug("%s: pwr = %X\n", __func__, pwr); 82 83 /* Set the bus voltage first (if any) */ 84 writeb(pwr, &priv->reg->pwrcon); 85 if (pwr == 0) 86 return; 87 88 /* Now enable bus power */ 89 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 90 writeb(pwr, &priv->reg->pwrcon); 91 } 92 93 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv, 94 struct mmc_data *data, 95 struct bounce_buffer *bbstate) 96 { 97 unsigned char ctrl; 98 99 100 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 101 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 102 data->blocksize); 103 104 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad); 105 /* 106 * DMASEL[4:3] 107 * 00 = Selects SDMA 108 * 01 = Reserved 109 * 10 = Selects 32-bit Address ADMA2 110 * 11 = Selects 64-bit Address ADMA2 111 */ 112 ctrl = readb(&priv->reg->hostctl); 113 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 114 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 115 writeb(ctrl, &priv->reg->hostctl); 116 117 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 118 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); 119 writew(data->blocks, &priv->reg->blkcnt); 120 } 121 122 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv, 123 struct mmc_data *data) 124 { 125 unsigned short mode; 126 debug(" mmc_set_transfer_mode called\n"); 127 /* 128 * TRNMOD 129 * MUL1SIN0[5] : Multi/Single Block Select 130 * RD1WT0[4] : Data Transfer Direction Select 131 * 1 = read 132 * 0 = write 133 * ENACMD12[2] : Auto CMD12 Enable 134 * ENBLKCNT[1] : Block Count Enable 135 * ENDMA[0] : DMA Enable 136 */ 137 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 138 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 139 140 if (data->blocks > 1) 141 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 142 143 if (data->flags & MMC_DATA_READ) 144 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 145 146 writew(mode, &priv->reg->trnmod); 147 } 148 149 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv, 150 struct mmc_cmd *cmd, 151 struct mmc_data *data, 152 unsigned int timeout) 153 { 154 /* 155 * PRNSTS 156 * CMDINHDAT[1] : Command Inhibit (DAT) 157 * CMDINHCMD[0] : Command Inhibit (CMD) 158 */ 159 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 160 161 /* 162 * We shouldn't wait for data inhibit for stop commands, even 163 * though they might use busy signaling 164 */ 165 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 166 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 167 168 while (readl(&priv->reg->prnsts) & mask) { 169 if (timeout == 0) { 170 printf("%s: timeout error\n", __func__); 171 return -1; 172 } 173 timeout--; 174 udelay(1000); 175 } 176 177 return 0; 178 } 179 180 static int tegra_mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 181 struct mmc_data *data, 182 struct bounce_buffer *bbstate) 183 { 184 struct tegra_mmc_priv *priv = mmc->priv; 185 int flags, i; 186 int result; 187 unsigned int mask = 0; 188 unsigned int retry = 0x100000; 189 debug(" mmc_send_cmd called\n"); 190 191 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */); 192 193 if (result < 0) 194 return result; 195 196 if (data) 197 tegra_mmc_prepare_data(priv, data, bbstate); 198 199 debug("cmd->arg: %08x\n", cmd->cmdarg); 200 writel(cmd->cmdarg, &priv->reg->argument); 201 202 if (data) 203 tegra_mmc_set_transfer_mode(priv, data); 204 205 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 206 return -1; 207 208 /* 209 * CMDREG 210 * CMDIDX[13:8] : Command index 211 * DATAPRNT[5] : Data Present Select 212 * ENCMDIDX[4] : Command Index Check Enable 213 * ENCMDCRC[3] : Command CRC Check Enable 214 * RSPTYP[1:0] 215 * 00 = No Response 216 * 01 = Length 136 217 * 10 = Length 48 218 * 11 = Length 48 Check busy after response 219 */ 220 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 221 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 222 else if (cmd->resp_type & MMC_RSP_136) 223 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 224 else if (cmd->resp_type & MMC_RSP_BUSY) 225 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 226 else 227 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 228 229 if (cmd->resp_type & MMC_RSP_CRC) 230 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 231 if (cmd->resp_type & MMC_RSP_OPCODE) 232 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 233 if (data) 234 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 235 236 debug("cmd: %d\n", cmd->cmdidx); 237 238 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); 239 240 for (i = 0; i < retry; i++) { 241 mask = readl(&priv->reg->norintsts); 242 /* Command Complete */ 243 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 244 if (!data) 245 writel(mask, &priv->reg->norintsts); 246 break; 247 } 248 } 249 250 if (i == retry) { 251 printf("%s: waiting for status update\n", __func__); 252 writel(mask, &priv->reg->norintsts); 253 return -ETIMEDOUT; 254 } 255 256 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 257 /* Timeout Error */ 258 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 259 writel(mask, &priv->reg->norintsts); 260 return -ETIMEDOUT; 261 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 262 /* Error Interrupt */ 263 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 264 writel(mask, &priv->reg->norintsts); 265 return -1; 266 } 267 268 if (cmd->resp_type & MMC_RSP_PRESENT) { 269 if (cmd->resp_type & MMC_RSP_136) { 270 /* CRC is stripped so we need to do some shifting. */ 271 for (i = 0; i < 4; i++) { 272 unsigned long offset = (unsigned long) 273 (&priv->reg->rspreg3 - i); 274 cmd->response[i] = readl(offset) << 8; 275 276 if (i != 3) { 277 cmd->response[i] |= 278 readb(offset - 1); 279 } 280 debug("cmd->resp[%d]: %08x\n", 281 i, cmd->response[i]); 282 } 283 } else if (cmd->resp_type & MMC_RSP_BUSY) { 284 for (i = 0; i < retry; i++) { 285 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 286 if (readl(&priv->reg->prnsts) 287 & (1 << 20)) /* DAT[0] */ 288 break; 289 } 290 291 if (i == retry) { 292 printf("%s: card is still busy\n", __func__); 293 writel(mask, &priv->reg->norintsts); 294 return -ETIMEDOUT; 295 } 296 297 cmd->response[0] = readl(&priv->reg->rspreg0); 298 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 299 } else { 300 cmd->response[0] = readl(&priv->reg->rspreg0); 301 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 302 } 303 } 304 305 if (data) { 306 unsigned long start = get_timer(0); 307 308 while (1) { 309 mask = readl(&priv->reg->norintsts); 310 311 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 312 /* Error Interrupt */ 313 writel(mask, &priv->reg->norintsts); 314 printf("%s: error during transfer: 0x%08x\n", 315 __func__, mask); 316 return -1; 317 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 318 /* 319 * DMA Interrupt, restart the transfer where 320 * it was interrupted. 321 */ 322 unsigned int address = readl(&priv->reg->sysad); 323 324 debug("DMA end\n"); 325 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 326 &priv->reg->norintsts); 327 writel(address, &priv->reg->sysad); 328 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 329 /* Transfer Complete */ 330 debug("r/w is done\n"); 331 break; 332 } else if (get_timer(start) > 8000UL) { 333 writel(mask, &priv->reg->norintsts); 334 printf("%s: MMC Timeout\n" 335 " Interrupt status 0x%08x\n" 336 " Interrupt status enable 0x%08x\n" 337 " Interrupt signal enable 0x%08x\n" 338 " Present status 0x%08x\n", 339 __func__, mask, 340 readl(&priv->reg->norintstsen), 341 readl(&priv->reg->norintsigen), 342 readl(&priv->reg->prnsts)); 343 return -1; 344 } 345 } 346 writel(mask, &priv->reg->norintsts); 347 } 348 349 udelay(1000); 350 return 0; 351 } 352 353 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 354 struct mmc_data *data) 355 { 356 void *buf; 357 unsigned int bbflags; 358 size_t len; 359 struct bounce_buffer bbstate; 360 int ret; 361 362 if (data) { 363 if (data->flags & MMC_DATA_READ) { 364 buf = data->dest; 365 bbflags = GEN_BB_WRITE; 366 } else { 367 buf = (void *)data->src; 368 bbflags = GEN_BB_READ; 369 } 370 len = data->blocks * data->blocksize; 371 372 bounce_buffer_start(&bbstate, buf, len, bbflags); 373 } 374 375 ret = tegra_mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 376 377 if (data) 378 bounce_buffer_stop(&bbstate); 379 380 return ret; 381 } 382 383 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) 384 { 385 int div; 386 unsigned short clk; 387 unsigned long timeout; 388 389 debug(" mmc_change_clock called\n"); 390 391 /* 392 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 393 */ 394 if (clock == 0) 395 goto out; 396 #ifdef CONFIG_TEGRA186 397 { 398 ulong rate = clk_set_rate(&priv->clk, clock); 399 div = (rate + clock - 1) / clock; 400 } 401 #else 402 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock, 403 &div); 404 #endif 405 debug("div = %d\n", div); 406 407 writew(0, &priv->reg->clkcon); 408 409 /* 410 * CLKCON 411 * SELFREQ[15:8] : base clock divided by value 412 * ENSDCLK[2] : SD Clock Enable 413 * STBLINTCLK[1] : Internal Clock Stable 414 * ENINTCLK[0] : Internal Clock Enable 415 */ 416 div >>= 1; 417 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 418 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 419 writew(clk, &priv->reg->clkcon); 420 421 /* Wait max 10 ms */ 422 timeout = 10; 423 while (!(readw(&priv->reg->clkcon) & 424 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 425 if (timeout == 0) { 426 printf("%s: timeout error\n", __func__); 427 return; 428 } 429 timeout--; 430 udelay(1000); 431 } 432 433 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 434 writew(clk, &priv->reg->clkcon); 435 436 debug("mmc_change_clock: clkcon = %08X\n", clk); 437 438 out: 439 priv->clock = clock; 440 } 441 442 static void tegra_mmc_set_ios(struct mmc *mmc) 443 { 444 struct tegra_mmc_priv *priv = mmc->priv; 445 unsigned char ctrl; 446 debug(" mmc_set_ios called\n"); 447 448 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 449 450 /* Change clock first */ 451 tegra_mmc_change_clock(priv, mmc->clock); 452 453 ctrl = readb(&priv->reg->hostctl); 454 455 /* 456 * WIDE8[5] 457 * 0 = Depend on WIDE4 458 * 1 = 8-bit mode 459 * WIDE4[1] 460 * 1 = 4-bit mode 461 * 0 = 1-bit mode 462 */ 463 if (mmc->bus_width == 8) 464 ctrl |= (1 << 5); 465 else if (mmc->bus_width == 4) 466 ctrl |= (1 << 1); 467 else 468 ctrl &= ~(1 << 1); 469 470 writeb(ctrl, &priv->reg->hostctl); 471 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 472 } 473 474 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) 475 { 476 #if defined(CONFIG_TEGRA30) 477 u32 val; 478 479 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); 480 481 /* Set the pad drive strength for SDMMC1 or 3 only */ 482 if (priv->reg != (void *)0x78000000 && 483 priv->reg != (void *)0x78000400) { 484 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 485 __func__); 486 return; 487 } 488 489 val = readl(&priv->reg->sdmemcmppadctl); 490 val &= 0xFFFFFFF0; 491 val |= MEMCOMP_PADCTRL_VREF; 492 writel(val, &priv->reg->sdmemcmppadctl); 493 494 val = readl(&priv->reg->autocalcfg); 495 val &= 0xFFFF0000; 496 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 497 writel(val, &priv->reg->autocalcfg); 498 #endif 499 } 500 501 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) 502 { 503 unsigned int timeout; 504 debug(" mmc_reset called\n"); 505 506 /* 507 * RSTALL[0] : Software reset for all 508 * 1 = reset 509 * 0 = work 510 */ 511 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst); 512 513 priv->clock = 0; 514 515 /* Wait max 100 ms */ 516 timeout = 100; 517 518 /* hw clears the bit when it's done */ 519 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 520 if (timeout == 0) { 521 printf("%s: timeout error\n", __func__); 522 return; 523 } 524 timeout--; 525 udelay(1000); 526 } 527 528 /* Set SD bus voltage & enable bus power */ 529 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1); 530 debug("%s: power control = %02X, host control = %02X\n", __func__, 531 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); 532 533 /* Make sure SDIO pads are set up */ 534 tegra_mmc_pad_init(priv); 535 } 536 537 static int tegra_mmc_core_init(struct mmc *mmc) 538 { 539 struct tegra_mmc_priv *priv = mmc->priv; 540 unsigned int mask; 541 debug(" mmc_core_init called\n"); 542 543 tegra_mmc_reset(priv, mmc); 544 545 priv->version = readw(&priv->reg->hcver); 546 debug("host version = %x\n", priv->version); 547 548 /* mask all */ 549 writel(0xffffffff, &priv->reg->norintstsen); 550 writel(0xffffffff, &priv->reg->norintsigen); 551 552 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */ 553 /* 554 * NORMAL Interrupt Status Enable Register init 555 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 556 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 557 * [3] ENSTADMAINT : DMA boundary interrupt 558 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 559 * [0] ENSTACMDCMPLT : Command Complete Status Enable 560 */ 561 mask = readl(&priv->reg->norintstsen); 562 mask &= ~(0xffff); 563 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 564 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 565 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 566 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 567 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 568 writel(mask, &priv->reg->norintstsen); 569 570 /* 571 * NORMAL Interrupt Signal Enable Register init 572 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 573 */ 574 mask = readl(&priv->reg->norintsigen); 575 mask &= ~(0xffff); 576 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 577 writel(mask, &priv->reg->norintsigen); 578 579 return 0; 580 } 581 582 static int tegra_mmc_getcd(struct mmc *mmc) 583 { 584 struct tegra_mmc_priv *priv = mmc->priv; 585 586 debug("tegra_mmc_getcd called\n"); 587 588 if (dm_gpio_is_valid(&priv->cd_gpio)) 589 return dm_gpio_get_value(&priv->cd_gpio); 590 591 return 1; 592 } 593 594 static const struct mmc_ops tegra_mmc_ops = { 595 .send_cmd = tegra_mmc_send_cmd, 596 .set_ios = tegra_mmc_set_ios, 597 .init = tegra_mmc_core_init, 598 .getcd = tegra_mmc_getcd, 599 }; 600 601 static int do_mmc_init(int dev_index, bool removable) 602 { 603 struct tegra_mmc_priv *priv; 604 struct mmc *mmc; 605 #ifdef CONFIG_TEGRA186 606 int ret; 607 #endif 608 609 /* DT should have been read & host config filled in */ 610 priv = &mmc_host[dev_index]; 611 if (!priv->enabled) 612 return -1; 613 614 debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n", 615 dev_index, priv->width, gpio_get_number(&priv->pwr_gpio), 616 gpio_get_number(&priv->cd_gpio)); 617 618 priv->clock = 0; 619 620 #ifdef CONFIG_TEGRA186 621 ret = reset_assert(&priv->reset_ctl); 622 if (ret) 623 return ret; 624 ret = clk_enable(&priv->clk); 625 if (ret) 626 return ret; 627 ret = clk_set_rate(&priv->clk, 20000000); 628 if (IS_ERR_VALUE(ret)) 629 return ret; 630 ret = reset_deassert(&priv->reset_ctl); 631 if (ret) 632 return ret; 633 #else 634 clock_start_periph_pll(priv->mmc_id, CLOCK_ID_PERIPH, 20000000); 635 #endif 636 637 if (dm_gpio_is_valid(&priv->pwr_gpio)) 638 dm_gpio_set_value(&priv->pwr_gpio, 1); 639 640 memset(&priv->cfg, 0, sizeof(priv->cfg)); 641 642 priv->cfg.name = "Tegra SD/MMC"; 643 priv->cfg.ops = &tegra_mmc_ops; 644 645 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 646 priv->cfg.host_caps = 0; 647 if (priv->width == 8) 648 priv->cfg.host_caps |= MMC_MODE_8BIT; 649 if (priv->width >= 4) 650 priv->cfg.host_caps |= MMC_MODE_4BIT; 651 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 652 653 /* 654 * min freq is for card identification, and is the highest 655 * low-speed SDIO card frequency (actually 400KHz) 656 * max freq is highest HS eMMC clock as per the SD/MMC spec 657 * (actually 52MHz) 658 */ 659 priv->cfg.f_min = 375000; 660 priv->cfg.f_max = 48000000; 661 662 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 663 664 mmc = mmc_create(&priv->cfg, priv); 665 mmc->block_dev.removable = removable; 666 if (mmc == NULL) 667 return -1; 668 669 return 0; 670 } 671 672 /** 673 * Get the host address and peripheral ID for a node. 674 * 675 * @param blob fdt blob 676 * @param node Device index (0-3) 677 * @param priv Structure to fill in (reg, width, mmc_id) 678 */ 679 static int mmc_get_config(const void *blob, int node, 680 struct tegra_mmc_priv *priv, bool *removablep) 681 { 682 debug("%s: node = %d\n", __func__, node); 683 684 priv->enabled = fdtdec_get_is_enabled(blob, node); 685 686 priv->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg"); 687 if ((fdt_addr_t)priv->reg == FDT_ADDR_T_NONE) { 688 debug("%s: no sdmmc base reg info found\n", __func__); 689 return -FDT_ERR_NOTFOUND; 690 } 691 692 #ifdef CONFIG_TEGRA186 693 { 694 /* 695 * FIXME: This variable should go away when the MMC device 696 * actually is a udevice. 697 */ 698 struct udevice dev; 699 int ret; 700 dev.of_offset = node; 701 ret = reset_get_by_name(&dev, "sdhci", &priv->reset_ctl); 702 if (ret) { 703 debug("reset_get_by_name() failed: %d\n", ret); 704 return ret; 705 } 706 ret = clk_get_by_index(&dev, 0, &priv->clk); 707 if (ret) { 708 debug("clk_get_by_index() failed: %d\n", ret); 709 return ret; 710 } 711 } 712 #else 713 priv->mmc_id = clock_decode_periph_id(blob, node); 714 if (priv->mmc_id == PERIPH_ID_NONE) { 715 debug("%s: could not decode periph id\n", __func__); 716 return -FDT_ERR_NOTFOUND; 717 } 718 #endif 719 720 /* 721 * NOTE: mmc->bus_width is determined by mmc.c dynamically. 722 * TBD: Override it with this value? 723 */ 724 priv->width = fdtdec_get_int(blob, node, "bus-width", 0); 725 if (!priv->width) 726 debug("%s: no sdmmc width found\n", __func__); 727 728 /* These GPIOs are optional */ 729 gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &priv->cd_gpio, 730 GPIOD_IS_IN); 731 gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &priv->wp_gpio, 732 GPIOD_IS_IN); 733 gpio_request_by_name_nodev(blob, node, "power-gpios", 0, 734 &priv->pwr_gpio, GPIOD_IS_OUT); 735 *removablep = !fdtdec_get_bool(blob, node, "non-removable"); 736 737 debug("%s: found controller at %p, width = %d, periph_id = %d\n", 738 __func__, priv->reg, priv->width, 739 #ifndef CONFIG_TEGRA186 740 priv->mmc_id 741 #else 742 -1 743 #endif 744 ); 745 return 0; 746 } 747 748 /* 749 * Process a list of nodes, adding them to our list of SDMMC ports. 750 * 751 * @param blob fdt blob 752 * @param node_list list of nodes to process (any <=0 are ignored) 753 * @param count number of nodes to process 754 * @return 0 if ok, -1 on error 755 */ 756 static int process_nodes(const void *blob, int node_list[], int count) 757 { 758 struct tegra_mmc_priv *priv; 759 bool removable; 760 int i, node; 761 762 debug("%s: count = %d\n", __func__, count); 763 764 /* build mmc_host[] for each controller */ 765 for (i = 0; i < count; i++) { 766 node = node_list[i]; 767 if (node <= 0) 768 continue; 769 770 priv = &mmc_host[i]; 771 priv->id = i; 772 773 if (mmc_get_config(blob, node, priv, &removable)) { 774 printf("%s: failed to decode dev %d\n", __func__, i); 775 return -1; 776 } 777 do_mmc_init(i, removable); 778 } 779 return 0; 780 } 781 782 void tegra_mmc_init(void) 783 { 784 int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count; 785 const void *blob = gd->fdt_blob; 786 debug("%s entry\n", __func__); 787 788 /* See if any Tegra186 MMC controllers are present */ 789 count = fdtdec_find_aliases_for_id(blob, "mmc", 790 COMPAT_NVIDIA_TEGRA186_SDMMC, node_list, 791 CONFIG_SYS_MMC_MAX_DEVICE); 792 debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count); 793 if (process_nodes(blob, node_list, count)) { 794 printf("%s: Error processing T186 mmc node(s)!\n", __func__); 795 return; 796 } 797 798 /* See if any Tegra210 MMC controllers are present */ 799 count = fdtdec_find_aliases_for_id(blob, "mmc", 800 COMPAT_NVIDIA_TEGRA210_SDMMC, node_list, 801 CONFIG_SYS_MMC_MAX_DEVICE); 802 debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count); 803 if (process_nodes(blob, node_list, count)) { 804 printf("%s: Error processing T210 mmc node(s)!\n", __func__); 805 return; 806 } 807 808 /* See if any Tegra124 MMC controllers are present */ 809 count = fdtdec_find_aliases_for_id(blob, "mmc", 810 COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, 811 CONFIG_SYS_MMC_MAX_DEVICE); 812 debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); 813 if (process_nodes(blob, node_list, count)) { 814 printf("%s: Error processing T124 mmc node(s)!\n", __func__); 815 return; 816 } 817 818 /* See if any Tegra30 MMC controllers are present */ 819 count = fdtdec_find_aliases_for_id(blob, "mmc", 820 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, 821 CONFIG_SYS_MMC_MAX_DEVICE); 822 debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); 823 if (process_nodes(blob, node_list, count)) { 824 printf("%s: Error processing T30 mmc node(s)!\n", __func__); 825 return; 826 } 827 828 /* Now look for any Tegra20 MMC controllers */ 829 count = fdtdec_find_aliases_for_id(blob, "mmc", 830 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, 831 CONFIG_SYS_MMC_MAX_DEVICE); 832 debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); 833 if (process_nodes(blob, node_list, count)) { 834 printf("%s: Error processing T20 mmc node(s)!\n", __func__); 835 return; 836 } 837 } 838