1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Aaron <leafy.myeh@allwinnertech.com> 5 * 6 * MMC driver for allwinner sunxi platform. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/mmc.h> 19 #include <asm-generic/gpio.h> 20 21 struct sunxi_mmc_host { 22 unsigned mmc_no; 23 uint32_t *mclkreg; 24 unsigned fatal_err; 25 struct sunxi_mmc *reg; 26 struct mmc_config cfg; 27 }; 28 29 /* support 4 mmc hosts */ 30 struct sunxi_mmc_host mmc_host[4]; 31 32 static int sunxi_mmc_getcd_gpio(int sdc_no) 33 { 34 switch (sdc_no) { 35 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); 36 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); 37 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); 38 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); 39 } 40 return -1; 41 } 42 43 static int mmc_resource_init(int sdc_no) 44 { 45 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 46 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 47 int cd_pin, ret = 0; 48 49 debug("init mmc %d resource\n", sdc_no); 50 51 switch (sdc_no) { 52 case 0: 53 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; 54 mmchost->mclkreg = &ccm->sd0_clk_cfg; 55 break; 56 case 1: 57 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; 58 mmchost->mclkreg = &ccm->sd1_clk_cfg; 59 break; 60 case 2: 61 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; 62 mmchost->mclkreg = &ccm->sd2_clk_cfg; 63 break; 64 case 3: 65 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; 66 mmchost->mclkreg = &ccm->sd3_clk_cfg; 67 break; 68 default: 69 printf("Wrong mmc number %d\n", sdc_no); 70 return -1; 71 } 72 mmchost->mmc_no = sdc_no; 73 74 cd_pin = sunxi_mmc_getcd_gpio(sdc_no); 75 if (cd_pin != -1) 76 ret = gpio_request(cd_pin, "mmc_cd"); 77 78 return ret; 79 } 80 81 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) 82 { 83 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 84 85 if (hz <= 24000000) { 86 pll = CCM_MMC_CTRL_OSCM24; 87 pll_hz = 24000000; 88 } else { 89 pll = CCM_MMC_CTRL_PLL6; 90 pll_hz = clock_get_pll6(); 91 } 92 93 div = pll_hz / hz; 94 if (pll_hz % hz) 95 div++; 96 97 n = 0; 98 while (div > 16) { 99 n++; 100 div = (div + 1) / 2; 101 } 102 103 if (n > 3) { 104 printf("mmc %u error cannot set clock to %u\n", 105 mmchost->mmc_no, hz); 106 return -1; 107 } 108 109 /* determine delays */ 110 if (hz <= 400000) { 111 oclk_dly = 0; 112 sclk_dly = 7; 113 } else if (hz <= 25000000) { 114 oclk_dly = 0; 115 sclk_dly = 5; 116 } else if (hz <= 50000000) { 117 oclk_dly = 3; 118 sclk_dly = 5; 119 } else { 120 /* hz > 50000000 */ 121 oclk_dly = 2; 122 sclk_dly = 4; 123 } 124 125 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | 126 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 127 CCM_MMC_CTRL_M(div), mmchost->mclkreg); 128 129 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", 130 mmchost->mmc_no, hz, pll_hz, 1u << n, div, 131 pll_hz / (1u << n) / div); 132 133 return 0; 134 } 135 136 static int mmc_clk_io_on(int sdc_no) 137 { 138 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 139 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 140 141 debug("init mmc %d clock and io\n", sdc_no); 142 143 /* config ahb clock */ 144 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); 145 146 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) 147 /* unassert reset */ 148 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); 149 #endif 150 151 return mmc_set_mod_clk(mmchost, 24000000); 152 } 153 154 static int mmc_update_clk(struct mmc *mmc) 155 { 156 struct sunxi_mmc_host *mmchost = mmc->priv; 157 unsigned int cmd; 158 unsigned timeout_msecs = 2000; 159 160 cmd = SUNXI_MMC_CMD_START | 161 SUNXI_MMC_CMD_UPCLK_ONLY | 162 SUNXI_MMC_CMD_WAIT_PRE_OVER; 163 writel(cmd, &mmchost->reg->cmd); 164 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { 165 if (!timeout_msecs--) 166 return -1; 167 udelay(1000); 168 } 169 170 /* clock update sets various irq status bits, clear these */ 171 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); 172 173 return 0; 174 } 175 176 static int mmc_config_clock(struct mmc *mmc) 177 { 178 struct sunxi_mmc_host *mmchost = mmc->priv; 179 unsigned rval = readl(&mmchost->reg->clkcr); 180 181 /* Disable Clock */ 182 rval &= ~SUNXI_MMC_CLK_ENABLE; 183 writel(rval, &mmchost->reg->clkcr); 184 if (mmc_update_clk(mmc)) 185 return -1; 186 187 /* Set mod_clk to new rate */ 188 if (mmc_set_mod_clk(mmchost, mmc->clock)) 189 return -1; 190 191 /* Clear internal divider */ 192 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 193 writel(rval, &mmchost->reg->clkcr); 194 195 /* Re-enable Clock */ 196 rval |= SUNXI_MMC_CLK_ENABLE; 197 writel(rval, &mmchost->reg->clkcr); 198 if (mmc_update_clk(mmc)) 199 return -1; 200 201 return 0; 202 } 203 204 static void mmc_set_ios(struct mmc *mmc) 205 { 206 struct sunxi_mmc_host *mmchost = mmc->priv; 207 208 debug("set ios: bus_width: %x, clock: %d\n", 209 mmc->bus_width, mmc->clock); 210 211 /* Change clock first */ 212 if (mmc->clock && mmc_config_clock(mmc) != 0) { 213 mmchost->fatal_err = 1; 214 return; 215 } 216 217 /* Change bus width */ 218 if (mmc->bus_width == 8) 219 writel(0x2, &mmchost->reg->width); 220 else if (mmc->bus_width == 4) 221 writel(0x1, &mmchost->reg->width); 222 else 223 writel(0x0, &mmchost->reg->width); 224 } 225 226 static int mmc_core_init(struct mmc *mmc) 227 { 228 struct sunxi_mmc_host *mmchost = mmc->priv; 229 230 /* Reset controller */ 231 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 232 udelay(1000); 233 234 return 0; 235 } 236 237 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) 238 { 239 struct sunxi_mmc_host *mmchost = mmc->priv; 240 const int reading = !!(data->flags & MMC_DATA_READ); 241 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : 242 SUNXI_MMC_STATUS_FIFO_FULL; 243 unsigned i; 244 unsigned byte_cnt = data->blocksize * data->blocks; 245 unsigned timeout_msecs = 2000; 246 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); 247 248 /* Always read / write data through the CPU */ 249 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); 250 251 for (i = 0; i < (byte_cnt >> 2); i++) { 252 while (readl(&mmchost->reg->status) & status_bit) { 253 if (!timeout_msecs--) 254 return -1; 255 udelay(1000); 256 } 257 258 if (reading) 259 buff[i] = readl(&mmchost->reg->fifo); 260 else 261 writel(buff[i], &mmchost->reg->fifo); 262 } 263 264 return 0; 265 } 266 267 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, 268 unsigned int done_bit, const char *what) 269 { 270 struct sunxi_mmc_host *mmchost = mmc->priv; 271 unsigned int status; 272 273 do { 274 status = readl(&mmchost->reg->rint); 275 if (!timeout_msecs-- || 276 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { 277 debug("%s timeout %x\n", what, 278 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); 279 return TIMEOUT; 280 } 281 udelay(1000); 282 } while (!(status & done_bit)); 283 284 return 0; 285 } 286 287 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 288 struct mmc_data *data) 289 { 290 struct sunxi_mmc_host *mmchost = mmc->priv; 291 unsigned int cmdval = SUNXI_MMC_CMD_START; 292 unsigned int timeout_msecs; 293 int error = 0; 294 unsigned int status = 0; 295 unsigned int bytecnt = 0; 296 297 if (mmchost->fatal_err) 298 return -1; 299 if (cmd->resp_type & MMC_RSP_BUSY) 300 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); 301 if (cmd->cmdidx == 12) 302 return 0; 303 304 if (!cmd->cmdidx) 305 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 306 if (cmd->resp_type & MMC_RSP_PRESENT) 307 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; 308 if (cmd->resp_type & MMC_RSP_136) 309 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; 310 if (cmd->resp_type & MMC_RSP_CRC) 311 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; 312 313 if (data) { 314 if ((u32) data->dest & 0x3) { 315 error = -1; 316 goto out; 317 } 318 319 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; 320 if (data->flags & MMC_DATA_WRITE) 321 cmdval |= SUNXI_MMC_CMD_WRITE; 322 if (data->blocks > 1) 323 cmdval |= SUNXI_MMC_CMD_AUTO_STOP; 324 writel(data->blocksize, &mmchost->reg->blksz); 325 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); 326 } 327 328 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, 329 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); 330 writel(cmd->cmdarg, &mmchost->reg->arg); 331 332 if (!data) 333 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 334 335 /* 336 * transfer data and check status 337 * STATREG[2] : FIFO empty 338 * STATREG[3] : FIFO full 339 */ 340 if (data) { 341 int ret = 0; 342 343 bytecnt = data->blocksize * data->blocks; 344 debug("trans data %d bytes\n", bytecnt); 345 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 346 ret = mmc_trans_data_by_cpu(mmc, data); 347 if (ret) { 348 error = readl(&mmchost->reg->rint) & \ 349 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; 350 error = TIMEOUT; 351 goto out; 352 } 353 } 354 355 error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); 356 if (error) 357 goto out; 358 359 if (data) { 360 timeout_msecs = 120; 361 debug("cacl timeout %x msec\n", timeout_msecs); 362 error = mmc_rint_wait(mmc, timeout_msecs, 363 data->blocks > 1 ? 364 SUNXI_MMC_RINT_AUTO_COMMAND_DONE : 365 SUNXI_MMC_RINT_DATA_OVER, 366 "data"); 367 if (error) 368 goto out; 369 } 370 371 if (cmd->resp_type & MMC_RSP_BUSY) { 372 timeout_msecs = 2000; 373 do { 374 status = readl(&mmchost->reg->status); 375 if (!timeout_msecs--) { 376 debug("busy timeout\n"); 377 error = TIMEOUT; 378 goto out; 379 } 380 udelay(1000); 381 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); 382 } 383 384 if (cmd->resp_type & MMC_RSP_136) { 385 cmd->response[0] = readl(&mmchost->reg->resp3); 386 cmd->response[1] = readl(&mmchost->reg->resp2); 387 cmd->response[2] = readl(&mmchost->reg->resp1); 388 cmd->response[3] = readl(&mmchost->reg->resp0); 389 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", 390 cmd->response[3], cmd->response[2], 391 cmd->response[1], cmd->response[0]); 392 } else { 393 cmd->response[0] = readl(&mmchost->reg->resp0); 394 debug("mmc resp 0x%08x\n", cmd->response[0]); 395 } 396 out: 397 if (error < 0) { 398 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 399 mmc_update_clk(mmc); 400 } 401 writel(0xffffffff, &mmchost->reg->rint); 402 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, 403 &mmchost->reg->gctrl); 404 405 return error; 406 } 407 408 static int sunxi_mmc_getcd(struct mmc *mmc) 409 { 410 struct sunxi_mmc_host *mmchost = mmc->priv; 411 int cd_pin; 412 413 cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no); 414 if (cd_pin == -1) 415 return 1; 416 417 return !gpio_direction_input(cd_pin); 418 } 419 420 static const struct mmc_ops sunxi_mmc_ops = { 421 .send_cmd = mmc_send_cmd, 422 .set_ios = mmc_set_ios, 423 .init = mmc_core_init, 424 .getcd = sunxi_mmc_getcd, 425 }; 426 427 struct mmc *sunxi_mmc_init(int sdc_no) 428 { 429 struct mmc_config *cfg = &mmc_host[sdc_no].cfg; 430 431 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); 432 433 cfg->name = "SUNXI SD/MMC"; 434 cfg->ops = &sunxi_mmc_ops; 435 436 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 437 cfg->host_caps = MMC_MODE_4BIT; 438 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 439 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I) 440 cfg->host_caps |= MMC_MODE_HC; 441 #endif 442 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 443 444 cfg->f_min = 400000; 445 cfg->f_max = 52000000; 446 447 if (mmc_resource_init(sdc_no) != 0) 448 return NULL; 449 450 mmc_clk_io_on(sdc_no); 451 452 return mmc_create(cfg, &mmc_host[sdc_no]); 453 } 454