1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Aaron <leafy.myeh@allwinnertech.com> 5 * 6 * MMC driver for allwinner sunxi platform. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/mmc.h> 19 #include <asm-generic/gpio.h> 20 21 struct sunxi_mmc_host { 22 unsigned mmc_no; 23 uint32_t *mclkreg; 24 unsigned fatal_err; 25 struct sunxi_mmc *reg; 26 struct mmc_config cfg; 27 }; 28 29 /* support 4 mmc hosts */ 30 struct sunxi_mmc_host mmc_host[4]; 31 32 static int sunxi_mmc_getcd_gpio(int sdc_no) 33 { 34 switch (sdc_no) { 35 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); 36 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); 37 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); 38 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); 39 } 40 return -1; 41 } 42 43 static int mmc_resource_init(int sdc_no) 44 { 45 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 46 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 47 int cd_pin, ret = 0; 48 49 debug("init mmc %d resource\n", sdc_no); 50 51 switch (sdc_no) { 52 case 0: 53 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; 54 mmchost->mclkreg = &ccm->sd0_clk_cfg; 55 break; 56 case 1: 57 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; 58 mmchost->mclkreg = &ccm->sd1_clk_cfg; 59 break; 60 case 2: 61 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; 62 mmchost->mclkreg = &ccm->sd2_clk_cfg; 63 break; 64 case 3: 65 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; 66 mmchost->mclkreg = &ccm->sd3_clk_cfg; 67 break; 68 default: 69 printf("Wrong mmc number %d\n", sdc_no); 70 return -1; 71 } 72 mmchost->mmc_no = sdc_no; 73 74 cd_pin = sunxi_mmc_getcd_gpio(sdc_no); 75 if (cd_pin != -1) { 76 ret = gpio_request(cd_pin, "mmc_cd"); 77 if (!ret) 78 ret = gpio_direction_input(cd_pin); 79 } 80 81 return ret; 82 } 83 84 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) 85 { 86 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 87 88 if (hz <= 24000000) { 89 pll = CCM_MMC_CTRL_OSCM24; 90 pll_hz = 24000000; 91 } else { 92 #ifdef CONFIG_MACH_SUN9I 93 pll = CCM_MMC_CTRL_PLL_PERIPH0; 94 pll_hz = clock_get_pll4_periph0(); 95 #else 96 pll = CCM_MMC_CTRL_PLL6; 97 pll_hz = clock_get_pll6(); 98 #endif 99 } 100 101 div = pll_hz / hz; 102 if (pll_hz % hz) 103 div++; 104 105 n = 0; 106 while (div > 16) { 107 n++; 108 div = (div + 1) / 2; 109 } 110 111 if (n > 3) { 112 printf("mmc %u error cannot set clock to %u\n", 113 mmchost->mmc_no, hz); 114 return -1; 115 } 116 117 /* determine delays */ 118 if (hz <= 400000) { 119 oclk_dly = 0; 120 sclk_dly = 7; 121 } else if (hz <= 25000000) { 122 oclk_dly = 0; 123 sclk_dly = 5; 124 } else if (hz <= 50000000) { 125 oclk_dly = 3; 126 sclk_dly = 5; 127 } else { 128 /* hz > 50000000 */ 129 oclk_dly = 2; 130 sclk_dly = 4; 131 } 132 133 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | 134 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 135 CCM_MMC_CTRL_M(div), mmchost->mclkreg); 136 137 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", 138 mmchost->mmc_no, hz, pll_hz, 1u << n, div, 139 pll_hz / (1u << n) / div); 140 141 return 0; 142 } 143 144 static int mmc_clk_io_on(int sdc_no) 145 { 146 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 147 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 148 149 debug("init mmc %d clock and io\n", sdc_no); 150 151 /* config ahb clock */ 152 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); 153 154 #ifdef CONFIG_SUNXI_GEN_SUN6I 155 /* unassert reset */ 156 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); 157 #endif 158 #if defined(CONFIG_MACH_SUN9I) 159 /* sun9i has a mmc-common module, also set the gate and reset there */ 160 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET, 161 SUNXI_MMC_COMMON_BASE + 4 * sdc_no); 162 #endif 163 164 return mmc_set_mod_clk(mmchost, 24000000); 165 } 166 167 static int mmc_update_clk(struct mmc *mmc) 168 { 169 struct sunxi_mmc_host *mmchost = mmc->priv; 170 unsigned int cmd; 171 unsigned timeout_msecs = 2000; 172 173 cmd = SUNXI_MMC_CMD_START | 174 SUNXI_MMC_CMD_UPCLK_ONLY | 175 SUNXI_MMC_CMD_WAIT_PRE_OVER; 176 writel(cmd, &mmchost->reg->cmd); 177 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { 178 if (!timeout_msecs--) 179 return -1; 180 udelay(1000); 181 } 182 183 /* clock update sets various irq status bits, clear these */ 184 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); 185 186 return 0; 187 } 188 189 static int mmc_config_clock(struct mmc *mmc) 190 { 191 struct sunxi_mmc_host *mmchost = mmc->priv; 192 unsigned rval = readl(&mmchost->reg->clkcr); 193 194 /* Disable Clock */ 195 rval &= ~SUNXI_MMC_CLK_ENABLE; 196 writel(rval, &mmchost->reg->clkcr); 197 if (mmc_update_clk(mmc)) 198 return -1; 199 200 /* Set mod_clk to new rate */ 201 if (mmc_set_mod_clk(mmchost, mmc->clock)) 202 return -1; 203 204 /* Clear internal divider */ 205 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 206 writel(rval, &mmchost->reg->clkcr); 207 208 /* Re-enable Clock */ 209 rval |= SUNXI_MMC_CLK_ENABLE; 210 writel(rval, &mmchost->reg->clkcr); 211 if (mmc_update_clk(mmc)) 212 return -1; 213 214 return 0; 215 } 216 217 static void sunxi_mmc_set_ios(struct mmc *mmc) 218 { 219 struct sunxi_mmc_host *mmchost = mmc->priv; 220 221 debug("set ios: bus_width: %x, clock: %d\n", 222 mmc->bus_width, mmc->clock); 223 224 /* Change clock first */ 225 if (mmc->clock && mmc_config_clock(mmc) != 0) { 226 mmchost->fatal_err = 1; 227 return; 228 } 229 230 /* Change bus width */ 231 if (mmc->bus_width == 8) 232 writel(0x2, &mmchost->reg->width); 233 else if (mmc->bus_width == 4) 234 writel(0x1, &mmchost->reg->width); 235 else 236 writel(0x0, &mmchost->reg->width); 237 } 238 239 static int sunxi_mmc_core_init(struct mmc *mmc) 240 { 241 struct sunxi_mmc_host *mmchost = mmc->priv; 242 243 /* Reset controller */ 244 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 245 udelay(1000); 246 247 return 0; 248 } 249 250 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) 251 { 252 struct sunxi_mmc_host *mmchost = mmc->priv; 253 const int reading = !!(data->flags & MMC_DATA_READ); 254 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : 255 SUNXI_MMC_STATUS_FIFO_FULL; 256 unsigned i; 257 unsigned byte_cnt = data->blocksize * data->blocks; 258 unsigned timeout_msecs = 2000; 259 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); 260 261 /* Always read / write data through the CPU */ 262 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); 263 264 for (i = 0; i < (byte_cnt >> 2); i++) { 265 while (readl(&mmchost->reg->status) & status_bit) { 266 if (!timeout_msecs--) 267 return -1; 268 udelay(1000); 269 } 270 271 if (reading) 272 buff[i] = readl(&mmchost->reg->fifo); 273 else 274 writel(buff[i], &mmchost->reg->fifo); 275 } 276 277 return 0; 278 } 279 280 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, 281 unsigned int done_bit, const char *what) 282 { 283 struct sunxi_mmc_host *mmchost = mmc->priv; 284 unsigned int status; 285 286 do { 287 status = readl(&mmchost->reg->rint); 288 if (!timeout_msecs-- || 289 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { 290 debug("%s timeout %x\n", what, 291 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); 292 return TIMEOUT; 293 } 294 udelay(1000); 295 } while (!(status & done_bit)); 296 297 return 0; 298 } 299 300 static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 301 struct mmc_data *data) 302 { 303 struct sunxi_mmc_host *mmchost = mmc->priv; 304 unsigned int cmdval = SUNXI_MMC_CMD_START; 305 unsigned int timeout_msecs; 306 int error = 0; 307 unsigned int status = 0; 308 unsigned int bytecnt = 0; 309 310 if (mmchost->fatal_err) 311 return -1; 312 if (cmd->resp_type & MMC_RSP_BUSY) 313 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); 314 if (cmd->cmdidx == 12) 315 return 0; 316 317 if (!cmd->cmdidx) 318 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 319 if (cmd->resp_type & MMC_RSP_PRESENT) 320 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; 321 if (cmd->resp_type & MMC_RSP_136) 322 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; 323 if (cmd->resp_type & MMC_RSP_CRC) 324 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; 325 326 if (data) { 327 if ((u32) data->dest & 0x3) { 328 error = -1; 329 goto out; 330 } 331 332 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; 333 if (data->flags & MMC_DATA_WRITE) 334 cmdval |= SUNXI_MMC_CMD_WRITE; 335 if (data->blocks > 1) 336 cmdval |= SUNXI_MMC_CMD_AUTO_STOP; 337 writel(data->blocksize, &mmchost->reg->blksz); 338 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); 339 } 340 341 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, 342 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); 343 writel(cmd->cmdarg, &mmchost->reg->arg); 344 345 if (!data) 346 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 347 348 /* 349 * transfer data and check status 350 * STATREG[2] : FIFO empty 351 * STATREG[3] : FIFO full 352 */ 353 if (data) { 354 int ret = 0; 355 356 bytecnt = data->blocksize * data->blocks; 357 debug("trans data %d bytes\n", bytecnt); 358 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 359 ret = mmc_trans_data_by_cpu(mmc, data); 360 if (ret) { 361 error = readl(&mmchost->reg->rint) & \ 362 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; 363 error = TIMEOUT; 364 goto out; 365 } 366 } 367 368 error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); 369 if (error) 370 goto out; 371 372 if (data) { 373 timeout_msecs = 120; 374 debug("cacl timeout %x msec\n", timeout_msecs); 375 error = mmc_rint_wait(mmc, timeout_msecs, 376 data->blocks > 1 ? 377 SUNXI_MMC_RINT_AUTO_COMMAND_DONE : 378 SUNXI_MMC_RINT_DATA_OVER, 379 "data"); 380 if (error) 381 goto out; 382 } 383 384 if (cmd->resp_type & MMC_RSP_BUSY) { 385 timeout_msecs = 2000; 386 do { 387 status = readl(&mmchost->reg->status); 388 if (!timeout_msecs--) { 389 debug("busy timeout\n"); 390 error = TIMEOUT; 391 goto out; 392 } 393 udelay(1000); 394 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); 395 } 396 397 if (cmd->resp_type & MMC_RSP_136) { 398 cmd->response[0] = readl(&mmchost->reg->resp3); 399 cmd->response[1] = readl(&mmchost->reg->resp2); 400 cmd->response[2] = readl(&mmchost->reg->resp1); 401 cmd->response[3] = readl(&mmchost->reg->resp0); 402 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", 403 cmd->response[3], cmd->response[2], 404 cmd->response[1], cmd->response[0]); 405 } else { 406 cmd->response[0] = readl(&mmchost->reg->resp0); 407 debug("mmc resp 0x%08x\n", cmd->response[0]); 408 } 409 out: 410 if (error < 0) { 411 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 412 mmc_update_clk(mmc); 413 } 414 writel(0xffffffff, &mmchost->reg->rint); 415 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, 416 &mmchost->reg->gctrl); 417 418 return error; 419 } 420 421 static int sunxi_mmc_getcd(struct mmc *mmc) 422 { 423 struct sunxi_mmc_host *mmchost = mmc->priv; 424 int cd_pin; 425 426 cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no); 427 if (cd_pin == -1) 428 return 1; 429 430 return !gpio_get_value(cd_pin); 431 } 432 433 static const struct mmc_ops sunxi_mmc_ops = { 434 .send_cmd = sunxi_mmc_send_cmd, 435 .set_ios = sunxi_mmc_set_ios, 436 .init = sunxi_mmc_core_init, 437 .getcd = sunxi_mmc_getcd, 438 }; 439 440 struct mmc *sunxi_mmc_init(int sdc_no) 441 { 442 struct mmc_config *cfg = &mmc_host[sdc_no].cfg; 443 444 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); 445 446 cfg->name = "SUNXI SD/MMC"; 447 cfg->ops = &sunxi_mmc_ops; 448 449 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 450 cfg->host_caps = MMC_MODE_4BIT; 451 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; 452 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 453 454 cfg->f_min = 400000; 455 cfg->f_max = 52000000; 456 457 if (mmc_resource_init(sdc_no) != 0) 458 return NULL; 459 460 mmc_clk_io_on(sdc_no); 461 462 return mmc_create(cfg, &mmc_host[sdc_no]); 463 } 464