1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Aaron <leafy.myeh@allwinnertech.com> 5 * 6 * MMC driver for allwinner sunxi platform. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/mmc.h> 20 #include <asm-generic/gpio.h> 21 22 struct sunxi_mmc_priv { 23 unsigned mmc_no; 24 uint32_t *mclkreg; 25 unsigned fatal_err; 26 struct sunxi_mmc *reg; 27 struct mmc_config cfg; 28 }; 29 30 /* support 4 mmc hosts */ 31 struct sunxi_mmc_priv mmc_host[4]; 32 33 static int sunxi_mmc_getcd_gpio(int sdc_no) 34 { 35 switch (sdc_no) { 36 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); 37 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); 38 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); 39 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); 40 } 41 return -EINVAL; 42 } 43 44 static int mmc_resource_init(int sdc_no) 45 { 46 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; 47 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 48 int cd_pin, ret = 0; 49 50 debug("init mmc %d resource\n", sdc_no); 51 52 switch (sdc_no) { 53 case 0: 54 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; 55 priv->mclkreg = &ccm->sd0_clk_cfg; 56 break; 57 case 1: 58 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; 59 priv->mclkreg = &ccm->sd1_clk_cfg; 60 break; 61 case 2: 62 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; 63 priv->mclkreg = &ccm->sd2_clk_cfg; 64 break; 65 case 3: 66 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; 67 priv->mclkreg = &ccm->sd3_clk_cfg; 68 break; 69 default: 70 printf("Wrong mmc number %d\n", sdc_no); 71 return -1; 72 } 73 priv->mmc_no = sdc_no; 74 75 cd_pin = sunxi_mmc_getcd_gpio(sdc_no); 76 if (cd_pin >= 0) { 77 ret = gpio_request(cd_pin, "mmc_cd"); 78 if (!ret) { 79 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP); 80 ret = gpio_direction_input(cd_pin); 81 } 82 } 83 84 return ret; 85 } 86 87 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) 88 { 89 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 90 91 if (hz <= 24000000) { 92 pll = CCM_MMC_CTRL_OSCM24; 93 pll_hz = 24000000; 94 } else { 95 #ifdef CONFIG_MACH_SUN9I 96 pll = CCM_MMC_CTRL_PLL_PERIPH0; 97 pll_hz = clock_get_pll4_periph0(); 98 #else 99 pll = CCM_MMC_CTRL_PLL6; 100 pll_hz = clock_get_pll6(); 101 #endif 102 } 103 104 div = pll_hz / hz; 105 if (pll_hz % hz) 106 div++; 107 108 n = 0; 109 while (div > 16) { 110 n++; 111 div = (div + 1) / 2; 112 } 113 114 if (n > 3) { 115 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no, 116 hz); 117 return -1; 118 } 119 120 /* determine delays */ 121 if (hz <= 400000) { 122 oclk_dly = 0; 123 sclk_dly = 0; 124 } else if (hz <= 25000000) { 125 oclk_dly = 0; 126 sclk_dly = 5; 127 #ifdef CONFIG_MACH_SUN9I 128 } else if (hz <= 50000000) { 129 oclk_dly = 5; 130 sclk_dly = 4; 131 } else { 132 /* hz > 50000000 */ 133 oclk_dly = 2; 134 sclk_dly = 4; 135 #else 136 } else if (hz <= 50000000) { 137 oclk_dly = 3; 138 sclk_dly = 4; 139 } else { 140 /* hz > 50000000 */ 141 oclk_dly = 1; 142 sclk_dly = 4; 143 #endif 144 } 145 146 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | 147 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 148 CCM_MMC_CTRL_M(div), priv->mclkreg); 149 150 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", 151 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); 152 153 return 0; 154 } 155 156 static int mmc_clk_io_on(int sdc_no) 157 { 158 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; 159 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 160 161 debug("init mmc %d clock and io\n", sdc_no); 162 163 /* config ahb clock */ 164 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); 165 166 #ifdef CONFIG_SUNXI_GEN_SUN6I 167 /* unassert reset */ 168 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); 169 #endif 170 #if defined(CONFIG_MACH_SUN9I) 171 /* sun9i has a mmc-common module, also set the gate and reset there */ 172 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET, 173 SUNXI_MMC_COMMON_BASE + 4 * sdc_no); 174 #endif 175 176 return mmc_set_mod_clk(priv, 24000000); 177 } 178 179 static int mmc_update_clk(struct sunxi_mmc_priv *priv) 180 { 181 unsigned int cmd; 182 unsigned timeout_msecs = 2000; 183 184 cmd = SUNXI_MMC_CMD_START | 185 SUNXI_MMC_CMD_UPCLK_ONLY | 186 SUNXI_MMC_CMD_WAIT_PRE_OVER; 187 writel(cmd, &priv->reg->cmd); 188 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) { 189 if (!timeout_msecs--) 190 return -1; 191 udelay(1000); 192 } 193 194 /* clock update sets various irq status bits, clear these */ 195 writel(readl(&priv->reg->rint), &priv->reg->rint); 196 197 return 0; 198 } 199 200 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) 201 { 202 unsigned rval = readl(&priv->reg->clkcr); 203 204 /* Disable Clock */ 205 rval &= ~SUNXI_MMC_CLK_ENABLE; 206 writel(rval, &priv->reg->clkcr); 207 if (mmc_update_clk(priv)) 208 return -1; 209 210 /* Set mod_clk to new rate */ 211 if (mmc_set_mod_clk(priv, mmc->clock)) 212 return -1; 213 214 /* Clear internal divider */ 215 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 216 writel(rval, &priv->reg->clkcr); 217 218 /* Re-enable Clock */ 219 rval |= SUNXI_MMC_CLK_ENABLE; 220 writel(rval, &priv->reg->clkcr); 221 if (mmc_update_clk(priv)) 222 return -1; 223 224 return 0; 225 } 226 227 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv, 228 struct mmc *mmc) 229 { 230 debug("set ios: bus_width: %x, clock: %d\n", 231 mmc->bus_width, mmc->clock); 232 233 /* Change clock first */ 234 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) { 235 priv->fatal_err = 1; 236 return -EINVAL; 237 } 238 239 /* Change bus width */ 240 if (mmc->bus_width == 8) 241 writel(0x2, &priv->reg->width); 242 else if (mmc->bus_width == 4) 243 writel(0x1, &priv->reg->width); 244 else 245 writel(0x0, &priv->reg->width); 246 247 return 0; 248 } 249 250 static int sunxi_mmc_core_init(struct mmc *mmc) 251 { 252 struct sunxi_mmc_priv *priv = mmc->priv; 253 254 /* Reset controller */ 255 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); 256 udelay(1000); 257 258 return 0; 259 } 260 261 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc, 262 struct mmc_data *data) 263 { 264 const int reading = !!(data->flags & MMC_DATA_READ); 265 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : 266 SUNXI_MMC_STATUS_FIFO_FULL; 267 unsigned i; 268 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); 269 unsigned byte_cnt = data->blocksize * data->blocks; 270 unsigned timeout_usecs = (byte_cnt >> 8) * 1000; 271 if (timeout_usecs < 2000000) 272 timeout_usecs = 2000000; 273 274 /* Always read / write data through the CPU */ 275 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); 276 277 for (i = 0; i < (byte_cnt >> 2); i++) { 278 while (readl(&priv->reg->status) & status_bit) { 279 if (!timeout_usecs--) 280 return -1; 281 udelay(1); 282 } 283 284 if (reading) 285 buff[i] = readl(&priv->reg->fifo); 286 else 287 writel(buff[i], &priv->reg->fifo); 288 } 289 290 return 0; 291 } 292 293 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc, 294 uint timeout_msecs, uint done_bit, const char *what) 295 { 296 unsigned int status; 297 298 do { 299 status = readl(&priv->reg->rint); 300 if (!timeout_msecs-- || 301 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { 302 debug("%s timeout %x\n", what, 303 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); 304 return -ETIMEDOUT; 305 } 306 udelay(1000); 307 } while (!(status & done_bit)); 308 309 return 0; 310 } 311 312 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, 313 struct mmc *mmc, struct mmc_cmd *cmd, 314 struct mmc_data *data) 315 { 316 unsigned int cmdval = SUNXI_MMC_CMD_START; 317 unsigned int timeout_msecs; 318 int error = 0; 319 unsigned int status = 0; 320 unsigned int bytecnt = 0; 321 322 if (priv->fatal_err) 323 return -1; 324 if (cmd->resp_type & MMC_RSP_BUSY) 325 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); 326 if (cmd->cmdidx == 12) 327 return 0; 328 329 if (!cmd->cmdidx) 330 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 331 if (cmd->resp_type & MMC_RSP_PRESENT) 332 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; 333 if (cmd->resp_type & MMC_RSP_136) 334 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; 335 if (cmd->resp_type & MMC_RSP_CRC) 336 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; 337 338 if (data) { 339 if ((u32)(long)data->dest & 0x3) { 340 error = -1; 341 goto out; 342 } 343 344 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; 345 if (data->flags & MMC_DATA_WRITE) 346 cmdval |= SUNXI_MMC_CMD_WRITE; 347 if (data->blocks > 1) 348 cmdval |= SUNXI_MMC_CMD_AUTO_STOP; 349 writel(data->blocksize, &priv->reg->blksz); 350 writel(data->blocks * data->blocksize, &priv->reg->bytecnt); 351 } 352 353 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no, 354 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); 355 writel(cmd->cmdarg, &priv->reg->arg); 356 357 if (!data) 358 writel(cmdval | cmd->cmdidx, &priv->reg->cmd); 359 360 /* 361 * transfer data and check status 362 * STATREG[2] : FIFO empty 363 * STATREG[3] : FIFO full 364 */ 365 if (data) { 366 int ret = 0; 367 368 bytecnt = data->blocksize * data->blocks; 369 debug("trans data %d bytes\n", bytecnt); 370 writel(cmdval | cmd->cmdidx, &priv->reg->cmd); 371 ret = mmc_trans_data_by_cpu(priv, mmc, data); 372 if (ret) { 373 error = readl(&priv->reg->rint) & 374 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; 375 error = -ETIMEDOUT; 376 goto out; 377 } 378 } 379 380 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, 381 "cmd"); 382 if (error) 383 goto out; 384 385 if (data) { 386 timeout_msecs = 120; 387 debug("cacl timeout %x msec\n", timeout_msecs); 388 error = mmc_rint_wait(priv, mmc, timeout_msecs, 389 data->blocks > 1 ? 390 SUNXI_MMC_RINT_AUTO_COMMAND_DONE : 391 SUNXI_MMC_RINT_DATA_OVER, 392 "data"); 393 if (error) 394 goto out; 395 } 396 397 if (cmd->resp_type & MMC_RSP_BUSY) { 398 timeout_msecs = 2000; 399 do { 400 status = readl(&priv->reg->status); 401 if (!timeout_msecs--) { 402 debug("busy timeout\n"); 403 error = -ETIMEDOUT; 404 goto out; 405 } 406 udelay(1000); 407 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); 408 } 409 410 if (cmd->resp_type & MMC_RSP_136) { 411 cmd->response[0] = readl(&priv->reg->resp3); 412 cmd->response[1] = readl(&priv->reg->resp2); 413 cmd->response[2] = readl(&priv->reg->resp1); 414 cmd->response[3] = readl(&priv->reg->resp0); 415 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", 416 cmd->response[3], cmd->response[2], 417 cmd->response[1], cmd->response[0]); 418 } else { 419 cmd->response[0] = readl(&priv->reg->resp0); 420 debug("mmc resp 0x%08x\n", cmd->response[0]); 421 } 422 out: 423 if (error < 0) { 424 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); 425 mmc_update_clk(priv); 426 } 427 writel(0xffffffff, &priv->reg->rint); 428 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, 429 &priv->reg->gctrl); 430 431 return error; 432 } 433 434 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc) 435 { 436 struct sunxi_mmc_priv *priv = mmc->priv; 437 438 return sunxi_mmc_set_ios_common(priv, mmc); 439 } 440 441 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd, 442 struct mmc_data *data) 443 { 444 struct sunxi_mmc_priv *priv = mmc->priv; 445 446 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data); 447 } 448 449 static int sunxi_mmc_getcd_legacy(struct mmc *mmc) 450 { 451 struct sunxi_mmc_priv *priv = mmc->priv; 452 int cd_pin; 453 454 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no); 455 if (cd_pin < 0) 456 return 1; 457 458 return !gpio_get_value(cd_pin); 459 } 460 461 static const struct mmc_ops sunxi_mmc_ops = { 462 .send_cmd = sunxi_mmc_send_cmd_legacy, 463 .set_ios = sunxi_mmc_set_ios_legacy, 464 .init = sunxi_mmc_core_init, 465 .getcd = sunxi_mmc_getcd_legacy, 466 }; 467 468 struct mmc *sunxi_mmc_init(int sdc_no) 469 { 470 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; 471 struct mmc_config *cfg = &priv->cfg; 472 473 memset(priv, '\0', sizeof(struct sunxi_mmc_priv)); 474 475 cfg->name = "SUNXI SD/MMC"; 476 cfg->ops = &sunxi_mmc_ops; 477 478 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 479 cfg->host_caps = MMC_MODE_4BIT; 480 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) 481 if (sdc_no == 2) 482 cfg->host_caps = MMC_MODE_8BIT; 483 #endif 484 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 485 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 486 487 cfg->f_min = 400000; 488 cfg->f_max = 52000000; 489 490 if (mmc_resource_init(sdc_no) != 0) 491 return NULL; 492 493 mmc_clk_io_on(sdc_no); 494 495 return mmc_create(cfg, mmc_host); 496 } 497